DE4017533C2 - - Google Patents

Description

The invention relates to a system for carry control signals and monitoring signals. The The invention is particularly concerned with a bidirection control / supervisory signal transmission system, the a central station and at least one local or local station contains that of the central station is remotely located and shared with her Data signal transmission line is connected. The local The station contains at least one instrument, one device or a machine to be controlled and monitored and only called a controlled device in the following becomes. Control signals in the central station in Parallel form are generated, a parallel / series Implemented and then serialized to the local station transferred, there again a series / parallel implementation subjected and the controlled devices in parallel guided. On the other hand, in the local station, Über Guard signals generated that the different operating display the status of the controlled devices. These Monitoring signals are generated after a parallel / series Transfer serial to the central station, and via a common data signal transmission line. In the central station the serial arriving Monitoring signals for evaluation in parallel signals transferred.

The following is a description of the prior art.

In the field of automatic control widely used a signal transmission system the control signals from a control station including  a sequence controller, a programmable controller, of a computer or the like to control a number ter devices are transmitted, for example elek electric motors, moving coils, electromagnetic valves, Relays, thyristors, lamps and / or the like that are on locations away from the control station are installed. The control signals are used to control the operation of these devices. On the other hand, in the tax devices using sensor devices About watch signals detected, the states of the controlled Specify devices. About these sensor devices count for example reed switch, microswitch, key switch or the like. Two-state or on / off State sensor signals are sent to the control station wear and there to evaluate the operating conditions of the controlled devices.

The conventional control / monitoring signal over Support systems of the above type require a number of Transmission lines, such as energy transmission lines, Control / supervisory signal transmission lines, clock signal lines, ground potential (reference) lines and other lines between the control station and the controlled devices as well as between the tax station and the individual sensors are switched. A such a system necessarily involves a very large one Amount of hardware for wiring the transmission line and is therefore extremely expensive. There is today a tendency to control the devices more and more to miniaturize and arrange in high density. With this tendency is linked to the difficulty of how to should make access to these devices because the available space is limited and therefore the ver wiring becomes more complicated and laborious.

In a typical known control / monitoring signal transmission system are the control station and the controlled devices via a power transmission  line interconnected, via the electrical Energy is transferred to the controlled devices where electrical energy is data or information signals are superimposed. It also contains the connection a ground potential line. In this regard, for example, the Japanese patent publication No. 4239/1986. This transmission system However, has the difficulty that one for the Transfer or transfer of data or information signals between the control station and a variety of the controlled devices takes a long time and that a mechanism for acquiring addresses is required this is because in the transferred information signals Address information is contained, each of several Bits.

There has been no shortage of attempts at the above known transmission system described occurring To eliminate difficulties.

Please refer to DE 38 30 730 A1 and DE 38 33 004 A1. With those over there systems described is the control signal or Monitoring signal together with a clock signal wear, being from a single power transmission line Is used to transmit electrical Energy is used to drive the controlled devices. This way it is possible to set the amount of hardware for the wiring between a control station and the ge controlled devices as well as between the control station and the individual sensors or monitoring elements in to a considerable extent.

For a better understanding of the invention, the remote control system of a series / parallel converter known from DE 38 30 730 A1 is described with reference to FIG. 10 of the accompanying drawings, which essentially corresponds to FIG. 1 of this document.

The system shown in FIG. 10 contains a central station 95 and a local or local station 96 , which has a start bit unit 97 and a conversion unit 98 . Data relating to a control command are externally input into the central station 95 from a controller, for example from a sequence controller (not shown). The data entered in parallel form via a suitable input unit (not shown) arrive at a parallel / series conversion circuit 951 . The parallel-to-serial conversion circuit 951 converts the input data bits into serial signal pulses, timing a clock signal generated by a clock signal generator (OSC) 952 . The generated serial signal pulses arrive together with the clock pulses to a signal conversion circuit 953 . The signal conversion circuit 953 has the function of superimposing the serial signal pulses and the clock pulses of a DC supply energy. The DC voltage energy of the serial signal pulses and the clock pulses are superimposed and which is output by the signal conversion circuit 953 , then passes to a line 954 as a serial output signal "OUT", which has a waveform, as shown in Fig. 10 at (A ) is presented.

Furthermore, the signal conversion circuit 953 is laid out so that it generates a start signal "START" in synchronism with the start of the pulse train, which is superimposed on the energy in the manner described above. With regard to the start signal, reference is made to the illustration according to FIG. 10 at (B). The start signal is given on line 955 . A ground potential line 956 is also present .

The DC voltage energy output from the signal conversion circuit 963 thus has a waveform as shown at (A) in FIG. 1. In particular, a level or value V _{x represents} the voltage value of the DC voltage energy (in volts), V _x / 2 represents the voltage value which corresponds to the command or control signal pulse with the logic value "0", and 0 (zero) represents that Voltage value (0 volts), which corresponds to the command or control signal pulse with the logical value of "1". The signals with the logical values "1" and "0" occur individually in synchronism with the clock pulses.

Upon receipt of the pulse superimposed energy "OUT" by the local station 96 over line 994 , a load drive energy recovery circuit 972 generates energy with a voltage value that is substantially equal to the level or value V _x . This energy voltage value, which is obtained by eliminating the pulse components from the supplied pulse-superimposed energy signal, is used to supply energy or to drive devices or loads which are connected to output circuits 988 and 989 . The applied pulse superimposed energy is also supplied to stabilized constant voltage power generation circuits or voltage converters (KS) 971 and 981 , which generate a constant voltage (with a level or value less than V _x ). This constant voltage serves as the supply voltage for various component circuits of the local station, all of which are electronic circuits with low energy consumption. The output of the load drive energy recovery circuit 972 is connected to a line V _d which in turn is connected to power input terminals of the output circuits 988 and 989 to which the devices or loads (not shown) to be controlled are connected. The power line V _d may additionally be connected to a terminal 974 of a DC power supply for emergency, so that the loads can be operated even if the power supply from the central control station 95 should be interrupted for any reason. A start signal detection circuit 973 , which forms part of the start bit unit 97 and is supplied with energy from the constant voltage power supply circuit 971 , detects the start signal st, which is supplied via line 955 in synchronism with a first pulse t 1 with the logic value "1" (see Fig. 10 at (A)). The detected start pulse is supplied to a signal distribution circuit 983 . On the other hand, a signal extracting circuit 982 , which is connected to the power line 954 , detects the superimposed data signal pulses differentially with respect to the pulse level or pulse values and accordingly delivers clock pulses and data signal pulses dt with the logic level of "1" and / or "0".

The clock pulses ck go to the signal distribution circuit 983 and allow the signal output from the start signal detection circuit 973 with the logical value of "1" of the start signal to the signal distribution circuit 983 and then at the output terminal Q 1 of a first stage of the signal distribution circuit 983 the pulse with the logic level or value "1" occurs, which is then fed to a clock input terminal CP of a latch or memory circuit 984 .

Thus, with the timing of the clock pulse ck, the first data pulse from the logic value "1" (pulse t 1 shown in Fig. 10 at (A)) to a control pulse input terminal D of the latch circuit 984 and held there or stored. The result of this is that an output signal occurs at an output terminal Q of the latch circuit 984 which turns on the output circuit 988 , which may be a switch. Thus, the electrical energy output from the energy recovery circuit 972 is supplied to the device connected to the output circuit 988 to be electrically activated. This device can be the solenoid of an electric valve, an electric motor, a relay or the like.

At time t₂ occurs accordingly on line 954 as shown in FIG. 10 at (A), a pulse train, which has the logical value "0". Accordingly, the pulse extracting circuit 982 generates the outputs on the one hand the clock pulse ck and on the other hand the data signal pulse dt with the logic value "0". The clock pulse CK arrives at the signal distribution TIC 983 with the result that which contained in the first stage of the signal distribution circuit 983 logical data "1" that has been inputted thereto at the time t₁, is fed to a second stage of the circuit 983 ver, so that now the data signal pulse with the logic value "1" occurs at an output connection Q 2 and arrives at a clock input connection CP of a latch or memory circuit 985 . The result of this is that the logic "0" signal pulse output from the pulse extracting circuit 982 is latched by the latch circuit 985 . In this case, no output signal occurs at the output terminal Q of the latch circuit 985 . As a result, output circuit 989 remains idle or inactive.

Simultaneously with the output of the clock pulse from the output terminal Q 2 of the signal distribution circuit 983 , a subsequent stage start signal generation circuit 987 is driven in response to a signal that appears at an output terminal ₂ of the signal distribution circuit 983 . The consequence of this is that the start signal is fed to the subsequent conversion unit.

With reference to the above, it can thus be seen that the control data pulse train which is serially transmitted over the transmission line 954 is subjected to a serial / parallel conversion in the conversion unit 98 of the local station, whereby the output circuits 988 and 989 , which are connected to the Output side of the conversion unit 98 are connected, as well as those of the subsequent conversion unit (not shown in FIG. 10) to the states "ON", "OFF", "ON", "OFF" and "OFF", respectively, as Response to the control data pulse train shown in Fig. 10 at (A), assuming that three output circuits and three latch or latch circuits are provided in the subsequent conversion unit, the signal distribution circuit consisting of three stages. The above-mentioned state is maintained until the next control data pulse train is issued by the central station 95 .

From the above explanation it is apparent that the subject of DE 38 30 730 A1 is directed to a transmission system which is intended to transmit a control signal from a central station to remote devices which are to be controlled. On the other hand, a monitoring signal transmission system is known from DE 38 33 004 A1, which serves to transmit various monitoring signals to a central station in order to be processed and evaluated there with regard to the operating states of the devices. This transmission system is based on a concept that is similar to the concept explained above with reference to FIG. 10. The following should also be added. In the transmission system according to DE 38 33 004 A1, a clock signal including a series of clock pulses is transmitted from a central control station to a local or local station which is equipped with sensors for monitoring the states of controlled devices, the transmission of the clock signal in one of the energy superimposed state via an energy transmission line. In the local station, the energy for power supply or for driving the sensors and other circuits that are part of the local station is restored while the clock signal is extracted. In accordance with the states of the sensors that are sensed with the timing of the clock pulses, voltage values or voltage levels on the transmission line at clock pulse positions are modulated so that the voltage in accordance with the sensor output has the logic value "1" (display of the ON state the assigned controlled device) and the logic value "0" (display of the OFF state) assumes a voltage of 0 volts or V _x / 2 volts. The voltage levels are sequentially detected synchronously with the clock signal in the central station for the purposes of evaluation or monitoring. For further details, reference is expressly made to the publications listed.

Now combine the above described above systems with the aim that both the tax (data) signals as well as the monitoring (sensor) signals via can be worn, you need a pair of separate Transmission lines, d. H. one for transferring the Control signals from the central control station to the local station and another to transmit the Monitoring or sensor signals that indicate the states of the controlled devices view from local Station to the central station. This means that corresponding mechanisms for generating the clock signal and the start signal superimposed on the energy in the central station separately for both systems must be provided. This is a remarkable one Increase in the amount of hardware and the com complexity in the connection between the central  Control station and local stations or sensors increases. This has the disadvantage of high costs.

If you connect a variety of local stations the central station in the system specified above, the local stations are based on a Displacement technology operated, when receiving the Start signal from the previous stage the steering signal (the energy superimposed and from it at the moment the clock signal extracted) of the front stage the devices (or sensors) to be controlled in fed to each of the local stations. In this way are local stations as well as the individual ge controlled devices (or sensors) addresses assigned, each to the ordinal numbers of the impulses of the clock signals correspond. This should be based on an example are explained. It is assumed that the first local station on ten devices to be controlled points. The first to tenth clock pulse signals that be delivered from the central station therefore sequentially the devices in this series sequence supplied (the first clock pulse signal is syn chron with the start signal or provides the start signal and each clock signal carries control information tion), whereas the devices with the two ten local station, starting with the eleventh clock pulse can be driven sequentially.

Then if a structural modification or reissue should be made, for example by Add or remove device to be controlled or sensors, must necessarily also the addresses assigned to the devices be modified accordingly. This be in turn indicates that the program, which is based on a pro programmable control that runs in the central Station is involved or connected to it, must be modified. As a result, this means that  a system-based system change in a simple manner cannot be realized.

In addition, the known have shown Systems have the following disadvantage. The clock pulse signal, which is synchronized with the start signal, both of them will be generated in the central station by the received first local station, then in the after Completion or termination of control of the device services belonging to the first local station, the Start signal is generated in the first local station, which is then the second station to start the se quantitative control of the assigned devices is fed. Consequently, the start signal must the loka len stations are fed in succession, thus the control information (carried by the clock pulse signals) to the local stations sequentially. Consequently, transmission lines need to start signal between the central station and the first local station as well as between the adjacent loka len stations may be provided. This means again that the amount of hardware for wiring in after must be increased in part.

The object of the invention is therefore to provide a tax / To create heartbeat transmission system at where the problems outlined above are solved and at which the control signal and the monitoring signal a single data transmission line can be transmitted can.

Furthermore, a redesign or modification should the system structure, for example adding and / or the removal of controlled devices and / or Sensors that can be easily implemented.

Preferably, the start signal line, which at known systems is required to be saved can. Furthermore, the amount of work and the cost considerable for the wiring of the transmission system can be reduced.  

Contains to achieve the object of the invention a bidirectional control / monitoring signal transmission system for transmitting control signals from a Control to controlled devices and for transmission of monitoring signals from sensors that control the Monitor th devices to control via a common data signal line a send / receive time Handing or timing device with a timing generator gate for generating a timing signal, with an ener Power supply circuit for generating an energy supply supply voltage with a predetermined constant Level, and with a voltage converter circuit for Um form the power supply voltage in a row pulse-like voltage signals that have a voltage level have different from that of the energy supply voltage differs, and that under the control of the Output timing signals on the data signal line be one with the controller and the transmit / receive Time control device connected via the data signal line their first unit group with one with the data signal line connected first transmitter unit for modulating the level of the serial pulse-like voltage signals with those supplied by the controller in parallel Control data under the timing of the timing signal and with one with the controller and the send / receive time control device via the common signal data line connected first receiving unit for extracting the from serial monitoring signals originating from the sensors from the data signal line to supply the monitoring signals to the controller in parallel, and one with second connected to the transmit / receive timing device Unit group with one with the controlled devices and the second signal connected to the data signal line unit for demodulating the level of the first Transmitting unit, serial pulse-like chip voltage signals for the purpose of extracting the ge  controlled devices to leading control data and with one with the sensors and the data signal line connected second transmitter unit for modulating the Level of the serial pulse-like voltage signals with the over supplied by the sensors in parallel guard data signals for the purpose of transmitting them Signals to the first receiving unit.

According to an advantageous development of the Er The invention contains each of the transmission units and the Receiving units a first power generation circuit to generate a power supply voltage with con constant level from the pulse-like voltage signal to Purpose of electrical power supply to the scarf which form each unit and a second energy generating device for generating an energy supply voltage from the pulse-like voltage signal to electrically driving the controlled devices or the sensors.

Alternatively, the controlled devices and the sensors also directly from an energy supplier transmission circuit device of the transmission / reception time control device via a power transmission line are electrically powered.

In a preferred development of the invention can the first transmission unit of the first unit group and the second receiving unit of the second units group each in a number of m (where m <1) pair be provided, these units in one One-to-one correspondence assigned to each other and with the data signal line in a predetermined sequence are connected in the respective unit groups. Likewise, the first receiving unit can be the first Unit group and the second transmitter unit of the second Unit group each in a number of n (where n <1) can be provided in pairs, the units assigned to each other in a one-to-one correspondence  are and with the data signal line in a predetermined th sequence in the respective unit groups are. In this case, the assigned send and Receiving units are operated sequentially to the Control data signals and the monitoring signals gradually from the respective controlled devices and sensors transfer under the control of the timing signal.

According to a further preferred development of the The invention includes the transmit / receive timing device a first start signal generator, while each of the Sending units and the receiving units a second Start signal generator contains, so that a first pair the assigned transmitting unit and receiving unit in the transfer operation in response to the first start signal can be triggered and upon completion or End of operation of the first pair of broadcast and receiving units the second start signal generator the second start signal to trigger the transfer operation a subsequent pair of transmit and receive units can generate units. This operation is repeated until the last pair of sending and receiving units has been triggered in transfer mode.

In the above development of the invention can the sending units and the receiving units with each other be connected via a start signal line which the second start signals, whereas the first start signal to the first pair of transmitting and receiving units via the data signal line with a distinguishable Waveform can be transmitted. On the other hand the transmission / reception timing device, the transmission units and the receiving units with each other Start signal lines connected to the above he mentioned start signals.

In another advantageous development of the Invention can transmit and receive units in the first and second unit groups arbitrarily pre-selected  given points with the common data signal line be connected. In this case, the send / receive Time control device to generate a start signal generator gen a start signal, which in a distinguishable Waveform over the data signal line to the Transmitting or receiving units is transmitted. Other On the one hand, the sending and receiving units can be one Circuit for extracting a clock signal from the contain modulated pulse-like voltage signal, a counter for counting the clock signal as Ant word on the start signal and an address setting circuit to hold or save an address that belongs to the other unit is assigned. If the count of the count has reached a value that represents the address, the associated unit begins with the send or Receiving operation. In this case, the start line be saved. In addition, a change or Modification of the system structure made easier.

According to a further preferred development of the Invention includes control / supervisory signal transmission a termination or termination unit that installed after the last stage of the units is in a predetermined sequence within the first and second group are connected to each other. The Termination unit includes means for generating a signal of a predetermined waveform at Be completion or completion of the operation of all units that belong to the assigned group. On the other hand, that contains Transmit / receive timing device a test circuit for Check the line status of the data signal line as Response to the signal above.

Finally, another preferred Further development of the invention numerous receiving units be assigned to a unit group with the same address, so that the numerous receiving units at the same time one of the transmission units of the other group operated can be.  

In the following the invention on the basis of Drawings are explained by way of example. It shows:

Fig. 1 is a block diagram of the basic structure of a control / monitoring signal transmission system, which is an embodiment of the invention.

Fig. 2 is a diagram showing the basic structure of a control (or monitoring) signal transmission unit and a control-monitoring signal receiving unit that allocation type in a control / monitor signal transmission system from the address to an embodiment of OF INVENTION be applied dung according to,

Fig. 3 shows the basic circuit configuration of a control (or monitoring) signal-receiving unit and a control (or monitoring) signal transmitting unit, the play in a control / monitor signal transmission system from the start line type according to another Ausführungsbei the invention can be applied,

Fig. 4 is a diagram showing the configuration of a transmission / reception timing apparatus according to an execution example of the invention,

Fig. 5 (a) is a diagram showing the construction of the control (or monitoring) signal-receiving unit of the control / monitor signal transmission system of the Adreßzuord voltage type according to an embodiment of the invention,

Fig. 5 (b) is a diagram showing the structure of a control (or monitoring) signal transmission unit of the transmission system from the Adreßzuordnungstyp according to another embodiment of the invention,

Fig. 6 (a) is a diagram showing the structure of a control (or monitoring) signal-receiving unit of a control / monitor signal Übertragungssytems from the start line type according to an embodiment of the invention,

Fig. 6 (b) is a diagram showing the structure of a control (or monitoring) signal transmitting unit of a Übertra supply system from the start line type according to another embodiment of the invention,

Fig. 7 is a diagram showing the construction of a terminal unit, which is used in the transmission system,

Fig. 8 (a) and 8 (b) a timing chart for illustrating lichung of operations in the control / monitor signal cross-tragungssystem,

Fig. 9 time courses to illustrate processes in the connection unit, and

Fig. 10 is a circuit diagram of a previously described transmission system according to the prior art.

Fig. 1 is a block diagram illustrating the basic structure of a control / monitoring signal transmission system, which is an exemplary embodiment of the invention. The system shown includes a controller 10 , a monitoring signal reception unit 11 , a control signal transmission unit 12 , a transmission / reception timing device 13 , a control signal reception unit 14 , a monitoring signal transmission unit 15 , a group of devices 16 to be controlled, a Group of monitoring sensors 17 and connection units 18 and 19 . Also shown are an information or data signal line D, a ground potential or ground line G, a start signal line S and a power supply line P. These lines may be required if necessary, as described below.

Although only one monitoring signal receiving unit 11 is shown in FIG. 1, n of these receiving units may be present, n1. Equally, there can be m control signal transmission units 12 , m1. Correspondingly, the control signal receiving units 14 can be provided in the number m and the monitoring signal transmission units 15 in the number n. Below, for the sake of simplicity, the monitoring signal reception unit 11 and the control signal transmission unit 12 together are also called the first unit group. Likewise, the control signal receiving unit 14 and the monitoring signal transmitting unit 15 are jointly also called the second unit group.

The transmission / reception timing device 13 includes an oscillator (OSC) 131 , a timing generator 132 for generating a clock pulse signal and a start signal, a setting circuit 133 and a test circuit 134 .

Fig. 2 shows the basic structure of the receiving unit and the transmitting unit of an embodiment of the invention for a control / monitoring signal transmission system of the address assignment type. The reception unit 30 shown is representative of the monitoring signal reception unit 11 or the control signal reception unit 14 according to FIG. 1, and the transmission unit 31 shown represents the control signal transmission unit 12 or the monitoring signal transmission unit 15 according to FIG. 1.

On the other hand, FIG. 3 shows the basic structure of a receiving unit and a transmitting unit of a further exemplary embodiment of the invention for a control / monitoring signal transmission system of the start line type. The reception unit 20 shown corresponds to either the monitoring signal reception unit 11 or the control signal reception unit 14 according to FIG. 1, and the transmission unit 21 shown represents either the control signal transmission unit 12 or the monitoring signal transmission unit 15 according to FIG. 1.

According to a basic concept of the invention, as in the illustrated embodiments is, the control signal is transmitted from the Control to the controlled devices as well Transmission of the monitoring (sensor) signals from the Sensors for control via the transmission system by appropriate modulation of the level of the clock pulse signals supplied as a superimposition on the energy of the transmit / receive timing device according to the logic  values of "1" (ON) and "0" (OFF) of the control signal and of the monitor signal at each corresponding clock pulse position. For this purpose, the send / emp catch timing device means for generating a pulse-superimposed energy in addition to that Device for generating the start signal and the mass potential (earth) signals. The beat signal reception unit and the control signal transmission unit are fundamental Lich between the transmission line and the controller provided while the monitoring signal transmission unit between the transmission line and the sensors is switched, and the control signal receiving unit between the transmission line and the controlled Devices is provided.

As can be seen from Fig. 1, the output signal of the clock oscillator (OSC) 131 , which forms part of the transmit / receive timing control device 13, is supplied to an input terminal of the timing generator 132 , whereby a clock signal cp with a predetermined frequency is generated and then by means of a mixing circuit, which is only shown conceptually, a supply voltage V _{x is} superimposed, so that as a result a data / voltage signal D is produced which has a duty cycle of 50% and which assumes the level V _x during the front half of a period and assumes the V _x / 2 level (clock pulse level) during the rear half of the period. This data / voltage signal is supplied from a terminal 13 a of the data signal line D. Furthermore, a ground potential signal is output from a terminal 13 b to the ground line G. Furthermore, in the case of the control / monitoring signal transmission system of the start line type, a start signal (S) from the transmit / receive timing device 13 via a connector 13 c or 13 d to the start signal line S is given as shown in broken lines. On the other hand, in the case of the control / monitor signal transmission system of the address assignment type, the start signal (S) is given to the data signal line D in the form of a signal having a waveform or a waveform which is different from that of the data or information carrying clock pulse signal. Since in the latter case the start signal (S) is transmitted together with the data or information signal via the data signal line D, the start signal line can be saved. For this reason, the start signal line is only shown in dashed lines in Fig. 1.

Electrical energy for operating the controlled devices 16 , which are connected to the control signal receiving unit 14 , and the sensors 17 , which are connected to the monitoring signal transmission unit 15 , can be transmitted from the transmission / reception timing device 13 via a connection 13 e Supply or power transmission line P are supplied. It should be noted that this energy transmission line as the drive voltage supply source for driving or operating the devices to be controlled and the sensors to be monitored is only to be provided when the energy load required for this is large. In general, this load is small, so that the electrical energy derived from the data signal line is sufficient. This means that the energy transmission line P can be saved depending on the type of devices to be controlled or the type of sensors. Therefore, the power supply line P is also shown in dashed lines.

The data signal line D is connected directly to the receiving and transmitting units of the first and second unit groups. Each of the transmitting and receiving units contains a circuit for regenerating the drive or operating energy from the data signal line, a clock signal extracting circuit and a data signal extracting circuit (only in the case of the receiving units), in a manner similar to that in the known transmission system according to FIG. 10 is the case, although the circuit measures mentioned above are not shown in FIG. 1.

Furthermore, each of the transmitting and receiving units contains a shift register which corresponds to the shift register contained in the signal distribution circuit 983 according to FIG. 10 and serves to sequentially shift the signal pulse with the logical "1" in response to the start signal or trigger signal. In response to each output of the shift register, the transmitter unit individually extracts the parallel data pulse signals to thereby modulate the level of V _x / 2 of the corresponding clock pulses to a voltage level of zero volts or a voltage level of V _x / 2 volts depending thereon whether the extracted data signal is a logic "1" or a logic "0". On the other hand, the corresponding receiving unit distinguishes the levels of the clock pulses on the data signal line D in the same amount of time as in the above-mentioned modulation of the clock pulse level in order to connect the signals with levels of a logic "1" and / or "0" at the output terminal to generate, as indicated by the logic "1" signal that outputs the associated shift register.

Regarding the operation of the overall system, a numerical value is initially set or entered in the setting circuit 133 of the transmission / reception timing device 313 , which represents the number of data (each date corresponds to one clock) to be transmitted during a transmission period. If the start signal (a discrete or individual signal on the start signal line or a signal that is superimposed on the data-carrying clock pulse and is transmitted via the data signal line D and has a time profile or a waveform that differs from that of the data signal) simultaneously with When the output of the data signal is generated from the transmission / reception timing device 13 , the control signal transmission unit 12 , into which parallel control signals from the controller 10 are input via an input / output channel 102 , selects and sends the front one of the numerous input signals the data signal line D in the form of the correspondingly modulated voltage level.

The signal on the data signal line D is extracted in the control signal receiving unit 14 selected by the start signal (S), the output corresponding to a logic "1" or a logic "0" for holding in the control signal receiving unit 14 is generated and simultaneously output to the group of controlled devices 16 so that the corresponding one of these devices (not shown) is actuated when the output is a logic "1", or alternatively is decommissioned or switched off when the output is a logic Is "0". A similar operation is carried out sequentially in response to the other control signals which are transmitted or transmitted by the control signal transmission unit 12 , in which case the control signals are also supplied to the other corresponding output connections of the control signal reception unit 14 and are kept by them . It can thus be seen that the input connections of the control signal transmission unit 12 are in a one-to-one correspondence to the output connections of the control signal reception unit 14 . Accordingly, the number of input ports of the former unit is equal to the number of output ports of the latter unit.

For the following consideration it is assumed that a control signal transmission unit 12 is provided in combination with a control signal reception unit 14 . Then, when the transmission of the control signals between the control signal transmission unit 12 and the control signal reception unit 14 has been completed in the manner described above, then the monitoring signal transmission unit 15 , into which the monitoring or sensor signals in parallel form from each assigned sensors 17 are input in response to the start signal (S) provided by the control signal receiving unit 14 or triggered by a start device which is contained in the monitoring signal transmitting unit 15 , as will be described below with reference to FIG Fig. 2 will be explained while at the same time the monitoring signal receiving unit 11 , which serves to transmit the monitoring signal via an input / output channel 101 to the controller 10 in response to that supplied by the control signal transmission unit 12 of the previous stage Start signal put into operation or by one in the Monitoring signal receiving unit 11 itself included starting device ( Fig. 2) triggered in operation. The transmission of the monitoring signals is carried out in accordance with the principle described above in connection with the transmission of the control signals, with only a difference in the direction of transmission.

The monitoring or sensor signals, which the monitoring signal transmission unit 15 receives from the associated sensors 17 in parallel, are serially output on the data signal line D and detected by the monitoring signal receiving unit 11 for sequential len recording in a holding device in the monitoring signal receiving unit 11 . The monitoring signals are then transferred to the controller 10 via the I / O channel 101 .

When the transmission of the control signals and the monitoring signals between the associated transmitting and receiving units ( 12, 14; 15, 11 ) has ended, the timing generator 132 supplies a number of clock pulses to the test circuit 134 . The test circuit 134 differentiates or checks the signal states on the data signal line D for each clock pulse.

The completion or termination unit 19 is provided at the last stage of the second unit group for detecting the clock pulse signal on the data signal line D after the completion of the transmission of the control signals and the monitoring signals. After the completion of the transmission is detected, the termination unit 19 generates a predetermined output signal for test purposes, which is supplied to the transmission / reception timing control unit 13 to trigger the operation of the test circuit provided therein.

In the arrangement described above, although the termination unit 19 is provided on the second unit group side, it should be noted that the termination unit may also be provided on the first unit group side, as described with reference to the termination unit 18 in FIG. 1 is shown in dashed lines. In this case, the termination unit 19 could then be saved.

Fig. 2 shows the basic structure of the control signal or monitoring signal transmission unit and the control signal or monitoring signal receiving unit, which are used in the control / monitoring signal transmission system of the address assignment type, in which the start signal line S is saved, the individual units can be addressed by the counters contained therein. The units are connected at predetermined locations to at least two lines (namely the data signal line D and the ground potential line G), the start signal (S) from the transmit / receive timing device 13 being given to the data signal line D with a time course or a waveform is that differs from that of the data-carrying clock pulses det.

The control signal or monitoring signal reception unit shown in FIG. 2 represents either the control signal reception unit 14 or the monitoring signal reception unit 11 according to FIG. 1, and the control signal or monitoring signal transmission unit shown in FIG. 2 represents either the control signal transmission unit 12 or the monitoring signal transmission unit 15 according to FIG. 1.

The units 30 and 31 contain driving energy regenerating circuits 307 and 317 as well as stabilized constant voltage generating circuits 301 and 311 . Each of the circuits regenerating or restoring the driving energy serves to restore the driving energy P _d (a voltage with a level of approximately V _x ) from the data-superimposed energy signal with the signal curve (D) shown in FIG. 1. This data-superimposed energy signal is supplied via the data signal line D. The driving energy P _d derived from this signal is fed to the controlled devices and the sensors.

The stabilized constant voltage regenerating circuit is used to generate a constant voltage (lower than the voltage level V _x ) from the smoothed energy P _d . The constant voltage generated in this way serves to activate the component circuits of the units 30 and 31 . On the other hand, the signal extracting circuit 302 of the receiving unit 30 is formed so that it not only extracts the clock signal ck and the data signal dt, but also a start signal st by detecting the above-mentioned start signal (S), the timing or waveform of which is different of the clock pulse signal and which can have a level V _x which remains constant over a predetermined period of time. Likewise, the transmission unit 31 contains a signal extracting circuit 312 , which serves not only to extract the clock pulse ck, but also the signal which has the waveform which is different from the clock signal, in order to obtain a start signal st in this way.

In operation, when the control shown in FIG. 2 / supervisory signal receiving unit 30, the signal extracting circuit 302, first, the start signal ST from the data signal line D is detected, this start signal is st to a counter 303 supplied to the st to this start signal characterized responds that it has a counting starts to count the clock pulses ck, which are provided by the signal extracting circuit 302 . When the content of the counter 303 has reached a count value as previously entered or set in a setting circuit 304 , an operation start signal c with the logic level of "1" is generated at the output terminal of the counter 303 , with the result that the signal is supplied to a shift register 305 with the logic level "1". The logic signal "1" is shifted by the shift register 305 (in the illustration according to FIG. 2 in the right direction), specifically whenever the clock pulse ck appears, whereby an AND circuit 306 is enabled or controlled to do so by the Signal extracting circuit 302 to supply data signal dt with the logical value "1" or "0". The output of the AND circuit 306 is put into a hold circuit 308 and held (stored) therein.

It is important to know that the value previously placed in the setting circuit 304 represents the address assigned to the control / monitoring signal receiving unit 30 in which the setting circuit 304 is located. If the numerical value u is set in the setting circuit 304 and if the unit 30 is equipped with k output connections, the output data signal of this unit 30 at the first output connection (in the illustration according to FIG. 2 the leftmost connection of the parallel output connections) as Response to the u-th clock pulse generated, the remaining data pulses then follow sequentially in response to the (u + 1) -th clock pulse.

Similarly, in the case of the control / monitor signal transmission unit 31, a counter 313 is activated in response to the start signal st from the signal extracting circuit 312 to start counting the clock pulse ck. If the content of the counter 313 has reached a value which corresponds to the value previously set in the setting circuit 314 , a signal c is generated which commands the start of the operation of the shift register 315 , in which case the shifting process is then carried out. The consequence of this is that the control signal or the monitoring signal is emitted on the data signal line D. The numerical value placed in the setting circuit 313 represents the address assigned to the unit 31 . The data signals, the number of which corresponds to the number ℓ of the parallel inputs, are sent to the data signal line D for transmission.

In the above description, referring to FIG. 2, it was assumed, as part of an example, that the transmitting unit and the receiving unit are provided in a one-to-one correspondence. It was therefore desired to be noted that, in the case of the control / supervisory signal transmission system of the address assignment type, the control signal or supervisory signal generated by a single transmission unit can be transmitted to a plurality of reception units. In an address assignment type control / supervisory signal transmission system in which any given unit of the units connected to the data signal line detects the start signal and can also count the clock pulses derived from the data signal line D and can start the transmission or reception operation when the number of the clock pulses counted one has reached the preset value, it is possible to assign the same address to several receiving units. A single transmitter unit is therefore able to output data to a plurality of receiver units simultaneously. With a single transmitter unit and a plurality of receiver units in a one-to-n correspondence ratio, a so-called multi-directional branch transmission system can thus be implemented.

With the above system arrangement it is therefore possible Lich, the connections between the transmitter units and to change the receiving units or to modifi adorn and the number of these units in simpler and thereby extremely advantageously to increase or to reduce that in the associated law circuits set numerical values be set accordingly. Furthermore, it is from Advantage that the start signal line is saved can be.

Fig. 3 shows in block diagram form the basic circuit structure of a receiving unit and a transmitting unit, which are used in a control / monitoring signal transmission system in which the individual start signal line S, which is shown in dashed lines in Fig. 1, is actually used. This system training is called a control / monitoring signal transmission system of the start line type. With regard to this type of system, the start signal line is therefore drawn as a solid line in FIG. 3. As displayed in this figure, reception unit 20 represents either the control signal receiving unit 14 or the monitoring signal receiving unit 14 or the supervisory signal receiving unit 11 of FIG. 1, the transmission shown whereas unit 21, either the control signal transmission unit 12 or the monitor signal transmission unit 15 shown in FIG. 1.

In this transmission system of the start line type, the individual transmission units and reception units are connected to one another sequentially via the data signal line D, the start signal line S and the ground potential line G. In each of the first and second unit groups, the front transmission unit and the front reception unit, which are driven first, are connected to the transmission / reception timing device 13 . The power supply line P may optionally also be present if present, as indicated in FIG. 3 by a dashed line. There would then be a total of four lines.

The transmission unit 21 contains a drive energy regenerating or restoring circuit 215 for restoring the drive energy P _d (a voltage with a level of approximately V _x ) from the data-transmitted energy signal with a waveform (D) shown in FIG. 1. This data-superimposed energy signal is supplied via the data signal line D, and the drive energy P _d derived therefrom _is supplied to the controlled devices 26 . There is also a stabilized constant voltage regenerating circuit or a voltage converter 211 for generating a constant voltage (lower than the voltage level V _x ) from the smoothed energy P _d . The constant voltage obtained in this way is used to supply the component circuits of the transmitter unit 21 with energy.

As has already been mentioned in connection with the description of FIG. 1, it may happen that when the driving energy P _d for the controlled devices is derived from the data signal line D, the energy P _d for driving the controlled devices or the sensors is insufficient, in particular when these devices or sensors are present in large numbers or when their total capacity is excessively large. In such a case, the electrical energy can be provided separately via the separately provided energy transmission line P and supplied separately to the controlled devices or sensors. The circuit 215 for restoring the driving energy can then be omitted.

The start signal (S), which is supplied via the start signal line S via the transmission / reception timing device 13 ( FIG. 1) or from the unit of the preceding stage on the right in FIG. 3, arrives at an input terminal of a shift register 213 and becomes there in response to the clock signal ck, which is extracted by the signal extracting circuit 212 from the data signal line D, set in the first stage of the shift register. A logic signal "1" thus appears at the output of the first stage of the shift register 213 and is supplied to an input of an AND circuit 214 . Consequently, the AND circuit 214 outputs to the data signal line D a signal level which corresponds to the first input signal, which at this time is supplied to the transmission unit 21 by the controller ( 10 in FIG. 1) or a sensor. Then, under the control of the next clock pulse ck, the logic signal "1" is shifted by the shift register 213 , so that now a logic "1" at the output terminal 2 of the second stage of the shift register occurs, causing the signal level corresponding to the second input signal is output on the data signal line D. Through similar processes, the entire parallel signal supplied is converted into a series signal, which is output on the data signal line D in the form of distinguishable levels or amplitudes by means of the individual clock pulses. After completion of the parallel / series conversion, the start signal (S) occurs at the last stage of the shift register 213 and is fed to the adjacent receiving unit 20 .

The receiving unit 20 , which can be either the control signal receiving unit 14 or the monitoring signal receiving unit 11 according to FIG. 1, contains a driving energy regenerating circuit 206 , a stabilized constant voltage generating circuit 201 and a signal extracting circuit 202 , and as in the case of the transmission unit 21 described above, wherein the signal extracting circuit 202 serves to extract the clock signal ck from the data signal line D and at the same time to extract the data signal dt with a logical "1" or a logical "0", namely by discriminating the signal level of the control signal or monitoring signal supplied from the other transmission unit.

The receiving unit 20 further includes a shift register 203 which is provided so that it receives the start signal (S) of the transmission unit of the previous stage and at the same time receives the clock signal ck from the signal extracting circuit 202 , so that the shift register at its individual stage outputs connections sequentially outputs a logical "1".

Consequently, an AND circuit 204 is enabled or switched in response to each output pulse with a logic "1" that the shift register 203 supplies to an input of the AND circuit, so that output pulses are obtained which are a logic "1" and one logical "0" of the data signal (discrimination output signal), which the signal extracting circuit 202 provides. The output pulses of the AND circuit 204 are sequentially placed in a hold circuit 205 and held (stored) therein. In this way, the series / parallel conversion is carried out, the result of this conversion being held (stored) in the holding circuit 205 until the next cycle.

Next follows a detailed description of the transmission / reception timing device, the control / monitoring signal reception unit and transmission unit of the address assignment type transmission system, the control / monitoring signal reception unit and transmission unit of the start line type transmission system and the termination unit, in the aforementioned Order with reference to FIGS. 4 to 9. Here, FIG. 4 shows the circuit diagram of the structure of a transmit / receive timing control device according to an exemplary embodiment of the invention. FIG. 5 (a) shows the circuit diagram of the structure of a control signal or monitoring signal. Receiving unit used in the address assignment type transmission system, Fig. 5 (b) is the circuit diagram of the structure of a control signal or supervisory signal transmission unit used in the address assignment type transmission system, Fig. 6 (a) is the circuit diagram of the structure a control signal or monitoring signal reception 6 which is used in the start line type transmission system, FIG. 6 (b) is the circuit diagram of the structure of a control signal or monitor signal transmission unit used in the start line type transmission system, FIG. 7 is the circuit diagram of the termination unit structure, FIG. Fig. 8 (a) and 8 (b) a time chart for illustrating the operation of the control / monitor signal cross-tragungssystems and Fig. 9 a timing chart for illustrating the operation of the lichung termination unit.

The structure and operation of the transmission / reception timing device, which is denoted by 13 in Fig. 1, will be described in detail below with reference to Fig. 4 in conjunction with Figs. 8 (a) and 8 (b).

In Fig. 4, a power supply circuit 40 is shown, which is connected to an external power supply line, for example, 24 volts. This power supply circuit provides a supply voltage V _cc , which is supplied to the individual electronic circuits, which are part of the transmit / receive timing device. The data signal line D is also supplied with a voltage of 24 volts (corresponding to V _x , as shown in FIG. 1) from this power supply circuit.

An oscillator 44 ( 131 in Fig. 1) generates clock pulses which, as is apparent from the figure, a counter 43 , a shift register 45 and a flip-flop circuit 46 are supplied. Beginning with the pulse representing the start signal, the counter 43 begins counting the clock pulses. The number of clock pulses required to transmit the data signal is input to a setting circuit. If the count value in the counter 43 coincides with the number of pulses set in the setting circuit 41 , a coincidence circuit 42 supplies a logic output signal "1" which is fed to the shift register 45 via a connection labeled "DATA".

The shift register 45 generates sequential timing signals at connections (p + 1) to (p + 4) for checking the line states (for example short-circuit state). In response to these timing signals, error check circuits 471 through 474 check the line conditions. The function of the error checking circuits is described in detail below in connection with the termination circuit ( Fig. 7). At the time of the last output (p + 4) of the shift register 45 , the counter 43 is cleared, whereupon the counting of the next period is started. Please refer to Fig. 8 (b) at (2).

The output of the oscillator 44 is also supplied via a NOR circuit 486 and an OR circuit 487 to amplifier circuits 484 and 485 . The amplifier circuit 484 is fed through another input terminal with a voltage of 12 volts, whereas the amplifier circuit 585 is fed with another voltage terminal with a voltage of 24 volts. Depending on the respective control, the amplifier circuits 484 and 485 thus deliver an output voltage of 12 volts or 24 volts, the voltage of 24 volts being superimposed on the clock pulses in such a manner as is shown in FIG. 8 (a) in ( 2) is shown, and on the data signal line D is output.

NOR circuit 486 and OR circuit 487 also cooperate to obtain the start signal with a waveform in which the level of 24 volts remains constant for a predetermined period of time (e.g., a period that is 1.5 times longer) than that of the clock signal) in the case of the address assignment type transmission system. With regard to the start signal, the outputs (p + 3) and (p + 4) of the shift register 45 are used. Reference is made to Fig. 8 (b) at (2) regarding the line "D".

In the event that both or one of the first unit group and the second unit group (see. Fig. 1) transmit / receive units of the start line type (connected to the data signal line D, the ground potential line G and the start signal line S) contains from made use of a structure in which the start signal is supplied to the start signal line. When the output (p + 4) is generated at the last stage of the shift register 45 , the flip-flop circuit 46 supplies the signal with the logic level "1" over a period of the clock signal, the result being the start signal with a level of 0 volt, which the clock signal remains constant during a period is generated by drivers 481 and 482 . This vibration form of the start signal is shown in Fig. 8 (a) at (1) and in Fig. 8 (b) at (1) and occurs on line "S".

Since the voltage of 24 volts corresponds to the data signal (D) is superimposed by the transmit / receive timing output device, each of the units the electrical energy from the data signal line D. for driving the controlled devices and the sen regenerate sensors. However, the burden is high Capacity, one can see the power line of 24 volts the transmit / receive timing device to each Sending and receiving units, the controlled devices as well as the sensors as required is. However, it should be noted that the power line P of 24 volts is not essential.

Next, with reference to Figs. 5 (a) and 5 (b), the address assignment type receiving and transmitting units will be described. It should be remembered that these units operate in accordance with the principle explained above in connection with FIG. 2.

The control signal or monitoring signal receiving unit shown in Fig. 5 (a) is equipped with terminals D, G and P, which are connected to the common data signal line D, the ground potential line G and the power line P (available if necessary), and contains circuits for regenerating a supply voltage of 24 volts from the data signal line D, the voltage converter (KS = constant voltage) for generating the stable voltage V _cc for driving the electronic circuits contained in the transmitter unit, the circuit for extracting the clock pulses, the comparator for discriminating identifying the data signal and other parts as previously described. In the case of the address assignment type transmission system, the individual receiving units can be installed at locations which are arbitrarily chosen because there is no relationship between the locations or positions at which the units are to be installed and the addresses to be assigned to the units beforehand , have been created.

In the receiver unit of the address assignment type, a smoothed supply voltage of approximately 24 volts is regenerated from the data signal line D via a filter circuit. This filter circuit consists of a capacitor c₁ and a diode d. The voltage obtained in this way is simultaneously supplied to the power line terminal P and the drive voltage terminal Pd. Furthermore, a stabilized constant voltage generator or voltage converter (KS) 78 converts the voltage of 24 volts into a lower stabilized voltage V _CC , for driving the electronic circuits that make up the unit. The clock pulses are extracted by means of a comparison circuit 75 , while the data signal is extracted by means of a comparison circuit 76 .

If the start signal of 24 volts occurring on the data signal line D, which is generated by the transmit / receive timing device shown in FIG. 4 and has a period that is 1.5 times as long as that of the clock pulse, to a corresponding input connected to the receiving unit, the comparator 75 generates a detection signal by comparing the input voltage with a reference voltage of 16 volts. This detection signal is supplied to a time constant circuit, which consists of a resistor R and a capacitor c₂. This determines the duration of the detection signal. If the duration of the detection signal exceeds a preset period of time, a Schmitt trigger circuit 74 provides an output signal that serves to clear a counter 72 . The clock pulses that follow the one whom the comparator 75 has detected are then counted by the counter 72 .

The counting process of the counter 72 is shown at (3) in Fig. 8 (a). On the other hand, a predetermined address assigned to the receiving unit under consideration is set in an address setting circuit 70 . The count value of the counter 72 wid compared with the previously set address value in a coincidence circuit 71 . When the count value has reached the preset address value, the coincidence circuit 72 supplies a coincidence output signal to an output terminal OUT. This coincidence output signal is then fed into a shift register 73 via a connection S _i . Thereupon the operation of the receiving unit is started. Specifically, in the shift register 73 due to the clock pulses which occur successively as a logic signal "1", the logic signal "1" is pushed so that at output terminals Q₀, Q₁, Q₂,. . . Q _{n of} the shift register 73 in succession the logic signal "1" occurs, so that as a result data with a logic "1" and / or a logic "0" of the data signal extracted by the comparator 76 are held or stored by corresponding flip-flops 77 . Due to the output from the last stage Q _{n of} the shift register 73 , the data output operation to the controller ( 10 in Fig. 1) or to the devices to be controlled ( 16 in Fig. 1) is performed.

In connection with the address assignment type receiving unit, it should be noted that the same address can be assigned to a number of receiving units and input to the relevant setting circuits 70 . In this case, a single datum (data unit) supplied by the transmitting unit and appearing on the data signal line can be transferred in parallel to a multiplicity of receiving units. In this way it is possible to control devices installed in a variety of different locations with a single control signal. The single sending unit can either be a unit of the address assignment type or of the start line type.

The transmitting unit shown in FIG. 5 (b) by the address allocation type is so arranged and constructed that begins upon detection of the start signal with a vorbestimm th waveform (alone or concurrently with other transmitting units), a counter 82 to the counting of the clock pulses. When the count value has reached a numerical value which is stored in a setting circuit 80 and represents the address which is assigned to this transmitting unit, a coincidence circuit 81 generates a coincidence detection signal to which a shift register 83 responds by shifting the logic pulse "1" begins as described above with reference to Fig. 5 (a). Thus, the data signals of the logical value "1" and / or "0" that are sent from the individual input connections IN₀ to IN _n by the controller (if the transmission unit is the control signal transmission unit) or by the sensors (if it is in the transmission unit to the monitoring signal transmission unit) are entered, detected in order to change the level of the corresponding clock pulses on the data signal line D accordingly. In this way, the data signals, which represent the control signals of the controller or the monitoring signals of the monitoring sensors, are transmitted to the devices to be controlled or to the controller via the assigned receiving units.

Next, referring to Figs. 6 (a) and 6 (b), the sending unit and the receiving unit used in the start line type control / supervisory signal transmission system will be described. It should be recalled that these units operate according to the principle which has been described with reference to FIG. 3.

The receiving unit shown in Fig. 6 (a) is via the start signal line S, the data signal line D, the ground potential line G and the power line P (which serves as a power supply for driving the controlled devices or sensors) with the transmit / receive time control device ( 13 in Fig. 1) or connected to the transmitter unit of the preceding stage (not shown), which are provided to the left of the unit shown. A smoothed voltage of about 24 volts is derived via a filter circuit consisting of a capacitor c and a diode d from the data signal line D and the power line P and at the same time to the connection Pd for driving the controlled devices or the monitoring sensors. A voltage converter (KS) 53 is also supplied with the voltage of 24 volts, with the aim of obtaining a stabilized voltage V _cc for driving the electronic circuits, which are the shift registers and other parts form the reception unit.

Furthermore, the clock pulses (with an amplitude level of 12 volts or about 0 volts) are extracted from the data signal line D. This is done with the aid of a comparison with a voltage signal of 16 volts in a comparator 15 . The extracted clock pulses cp are fed to an input terminal CP of a shift register 54 . Furthermore, the data signal superimposed on the clock pulses is extracted from the data signal line D by comparison with a voltage of 8 volts in a comparator 52 which provides a logic signal "1" (ON signal) when that Data signal is about 0 volts, and otherwise provides a logic signal "0" (OFF signal).

The start signal applied to the start signal line S is fed to an input terminal S _{i of} the shift register 54 via an amplifier 50 . The first stage of the shift register 54 then outputs a logic signal "1". This logic signal "1" is then shifted through the successive stages of the shift register. This logic signal "1" is supplied to an assigned flip-flop circuit 55 . The consequence of this is that logic signals "0" and / or "1" of the data signal are stored in the flip-flop circuit 55 , in accordance with the identification by the comparator 52 . Thus, the flip-flop circuit 55 is loaded with the data corresponding to the data signal on the data signal line D.

When the signals with waveforms as shown in FIG. 8 (a) at (4) appear, the flip-flop circuits 55 thus generate the output signals OUTignale to OUT _n with waveforms as shown in FIG. 8 (a) at (5) are shown. These output signals are used to control the controlled devices which are connected via drivers to the output connections OUT₀ to OUT _n , in the event that the receiving unit is connected to the controlled devices, as is shown in FIG. 1 for the control signal Receiving unit 14 is illustrated, whereas the output signals OUT₀ to OUT _n are fed directly to the controller ( 10 in FIG. 1) when the receiving unit serves as a monitoring signal receiving unit 11 according to FIG. 1.

The last stage Q _{n of} the shift register 54 generates, via an inverter 57, the start signal which is output on the start signal line S leading to the subsequent unit.

Referring to FIG. 6 (b) is integral connected to the control signal or over wachungssignal sending unit through the power line P, the start signal line S, the data signal line D and the ground potential line G with the adjacent A, wherein the power line P is only provided if is necessary for the reasons already described above. A smoothed voltage of approximately 24 volts is derived from the data signal line D by means of a filter circuit consisting of a capacitor c and a diode d, which is supplied to the power line P and at the same time to the connection P _d for driving the controlled devices or the monitoring sensors, which are connected to the considered transmission unit. A voltage converter (KS) 63 supplies a voltage V _cc for activating the electrical devices that form the unit.

This voltage is derived from the voltage of 24 volts. The start signal, which is provided by the adjacent unit (provided on the left side of the unit shown in Fig. 6 (b)), comes to an input terminal S _{i of} a shift register 64 which performs a shift operation in response to clock pulses. These clock pulses are extracted using a comparator 61 in the same manner as previously described in connection with FIG. 5 (a). The outputs from the individual stages Q ₁ to Q _{n of} the shift register 64 are assigned to inputs AND circuits 65 , so that data signals IN₀ to IN _n with logical values of "1" and / or "0", which the controller ( 10 in Fig. 1) or from the monitoring sensors ( 17 in Fig. 1), by means of gate control by the AND circuits 65 on the data signal line D via a NOR circuit 66 , an AND circuit 67 and a driver 62 are output . Thus, the data signal transmitted by this transmission unit represents the control signal if the unit is connected to the controller, or the monitoring signal (status detection signal) if the unit is connected to the monitoring sensors.

An example of the waveform of the data signal thus generated is shown at (4) in Fig. 8 (a). As can be seen, if the signals input to the connections IN₀ to IN _{n of} the transmission unit are of such a waveform, as shown in FIG. 8 (a) at (4), the clock pulses on the data signal line D Values of 12 volts and 0 volts on, in accordance with the logic signal "0" or "1" of the supplied data signal. This means that the data signal of logic value "1" causes the level of the corresponding clock pulse to change from 12 volts to 0 volts, as shown by dashed lines in Fig. 8 (a) at (2), whereas against the data signal with the logic value of "0" allows the associated clock pulse to remain at the 12 volt level.

The conclusion or termination unit will now be described with reference to FIG. 7 and FIG. 9. The termination unit shown in FIG. 7 is implemented in a structure of the start line type and is connected to the start signal line S, the data signal line D and the ground potential line G. Since the termination unit is connected to the last 10335 00070 552 001000280000000200012000285911022400040 0002004017533 00004 10216 stage, the start signal generated by the immediately preceding unit is supplied to a terminal "S". This start signal is shown in Fig. 9 at (S). At this time, if a clock pulse on the data signal line D is detected by a comparator 91 , an AND circuit A1 supplies an output pulse, which is shown in Fig. 9 at (A1). A flip-flop circuit 93 is thereby set, so that a logic signal "1" is present at an output terminal Q of the flip-flop circuit 93 and is supplied to an AND circuit A2. Thereafter, clock pulses, each with a predetermined time period, are given to the AND circuit A2 in rhythm with the clock control.

As long as the clock pulses of the predetermined period are detected, the AND circuit A2 outputs a logic signal "1" in response to the clock pulses of logic value "1", which the comparator 91 supplies. Since the logic pulses "1" have a duration that is shorter than the time constant (c₂R) of a time constant circuit, which is formed by a resistor R and a capacitor C₂, a Schmitt trigger circuit 94 is not modulated. However, if the clock pulse at the 12 volt level lasts for a period of time or period twice as long as that of the ordinary clock pulse as given by (p + 3) and shown in Fig. 9 at (D) the Schmitt trigger circuit 94 turned on and provides an output signal d 1, as shown in Fig. 9 at (d 1), whereby a driver 92 is activated, which then outputs an output signal of 0 volts to the data signal line D. At this time, the flip-flop circuit 93 is reset.

The signal of 0 volts (signal with the logic value of "1") which is output to the data signal line D is checked by an error checking circuit 473 , which is contained in the transmission / reception timing device shown in FIG . If this signal is not detected, it is decided that a malfunction or an error has occurred.

The termination unit can also be implemented with simple modifications in the structure of the address assignment type. Thus, a counter and an address setting circuit are provided, in which an address other than that associated with signal transmission has been entered as the end address, the end address then being detected by a coincidence circuit to produce a corresponding output signal which is then supplied to the AND circuit A 1 so as to set the flip-flop circuit 93 .

The termination unit is connected to the immediately preceding stage via the start signal line S, the data signal line D, the ground potential line G and the power line P (as an auxiliary power source). A smoothed voltage of about 24 volts is derived from the data signal line D by means of a filter circuit which consists of a capacitor c 1 and a diode d. A voltage converter 95 in turn provides a lower voltage V _cc to activate the electronic circuits that form the termination unit.

Next, the error checking operation will be briefly explained in connection with the transmission / reception timing device shown in FIG. 4.

As can be seen in FIG. 4 in connection with FIG. 8 (b), an output occurs at an output connection (p + 1) of the shift register 45 at a point in time (p + 1) which immediately corresponds to the last clock (p- th clock) of the data transmission to the controlled devices or from the sensors follows, whereupon a final test is carried out by means of a fault 1 test circuit 471 . Specifically, at this time, the start signal is generated from the last stage of the shift register included in the last unit of the first unit group provided in association with the controller (see FIG. 1), and this start signal becomes a terminal R of the device presented in Fig. 4 Darge. This start signal is checked by the Error 1 check circuit 471 when clocking or clocking (p + 1). In this context, it should be noted that this function can only be realized if the individual units of the first unit group are of the start line type. If the signal "1" is not detected, this means that the data signal has not been transmitted to all units. In this case, a relay X 477 is controlled via an OR circuit 475 and a driver 476 in order to switch on a monitoring lamp. The arrangement can of course also be provided so that a lamp that is normally switched on is switched off when the error occurs.

On the basis of the second clock pulse (p + 2), a second error check (error 2 check) is carried out to determine whether the level of the data signal line at this time is 12 volts (representing a logic "0"). In detail, the signal level of the data signal line D is compared with a reference voltage of 12 volts using the comparator 483 . If the signal level is lower than 12 volts, a logic "1" is output, otherwise a logic "0". The signal resulting from the inversion or inversion of the above logic signal using an inverse or NOT circuit is supplied to an error 2 test circuit 472 . If the input to this test circuit is a logic "1", it means that the system is operating normally. If the input to circuit 472 is a logic "0", this leads to an error output.

Since the second error check (error 2 check) is carried out at the time at which the data signal transmission to all units has been completed, a logic signal "1" (voltage of 0 volts) should not be present on the data signal line D. However, if the logic signal "1" is detected for any reason (for example a short circuit between the data line and the ground potential line, incorrect address input or the like), this error is detected by error 2 test circuit 472 and displayed.

At the time of the next clock (p + 3), an error 3 test circuit 473 checks whether the signal on the data signal line D is a logic "1" or a logic "0". If it is a logical "0", an error detection is output. In this case, the front half level of 24 volts of the clock signal is not output at the terminal (p + 3) of the shift register of the timing device ( Fig. 4), but the level of 12 volts is maintained as in Fig. 8 (b) (2) is shown. The termination unit shown in FIG. 7 consequently outputs the signal with a level of 0 volt (logical "1") to the data signal line D due to the previously described mode of operation. At this time, the signal on the data line is detected by the comparator 483 and checked on the rising edge of the pulse (p + 4) by means of the error 3 test circuit 473 . If the signal is a logical "0", this means that the transmission cable does not extend to the termination unit, for example due to a line break, short circuit or a similar fault.

At the next clock (p + 4) the counter 43 is reset due to the output at the connection (p + 4) of the shift register. In response to the falling edge of the output (p + 4), the start signal to be supplied to the start line type unit is generated by the flip-flop circuit 46 . The start signal output from a buffer 481 or 482 is detected by an AND circuit 480 and checked by means of an error 4 test circuit 474 . In the event of an abnormality, an error output signal is generated which drives the relay X, as in the case of the occurrence of the other errors.

From the above description regarding the structure of the control / monitoring signal transmission system according to the invention, in which the transmitter units and the Emp capture units with the transmit / receive timing device are connected, which is a power supply chip layered and for the representation of tax data or monitoring information in the level modulated clock  pulse signal on the common data signal line given, it is clear that it is possible to bidirectional signal transmission between the controller and the controlled devices as well as between the control and the monitoring sensors with a simplified Construction.

Furthermore, in the transmission / reception unit from Address assignment type is the number of connection lines tion can be reduced, what with a corresponding Reduction in wiring costs is associated. Consequently can with great advantage the wiring between the individual units can be simplified. Since the assignment The addresses for the individual units are arbitrary units can be added arbitrarily or be taken away. It is also in the transmission address assignment type system possible, a variety of receiving units corresponding to a single one To provide the sending unit, making the same data the same supplied to a large number of receiving units at the same time can be installed in different places are. Furthermore, an error check can be carried out continuously in the The signal transmission run to a Detect errors immediately when performing. This improves the reliability of the transmission system considerably increased.

Claims (16)

1. Control / monitoring signal transmission system for transmitting control signals from a controller to controlled devices and for transmitting monitoring signals from sensors monitoring the controlled devices to the controller via a common data signal line, characterized by :
a transmission / reception timing device ( 13 ) with a timing generator device for generating a timing signal, a power supply device for generating an energy supply voltage of a predetermined constant value and a voltage converter device for converting the energy supply voltage into a series of pulse-like voltage signals having a voltage value that from which the power supply voltage is different, and which are output on the data signal line (D) under the control of the timing signal,
a first unit group ( 11, 12 ), which is connected to the controller ( 10 ) and the transmission / reception timing device via at least the data signal line, and which contains at least one first transmission unit ( 12 ) connected to the data signal line for modulating the value the serial pulse-like voltage signals on the data signal line with control data supplied by the controller in parallel form under the control of the timing signal and at least one first receiving unit ( 11 ) connected to the controller ( 10 ) and the transmission / reception time control device via at least the data signal line (D) ) for extracting the serial monitoring signals from the sensors ( 17 ) from the data signal line under the control of the timing signal in order to supply the monitoring signals to the controller in parallel, and
a second group of units ( 14, 15 ) which is connected to the transmission / reception timing device ( 13 ) and which contains at least one connected to the controlled devices ( 16 ) and the data signal line (D) second reception unit ( 14 ) for demodulating the Values of the serial pulse-like voltage signals supplied by the first transmission unit ( 12 ) via the data signal line (D) and thereby for extracting the control data to be supplied to the controlled devices ( 16 ) under the control of the timing signal and at least one with the sensors ( 17 ) and the data signal line (D) connected to the second transmission unit ( 15 ) for modulating the values of the serial pulse-like voltage signals on the data signal line with monitoring data signals supplied in parallel from the sensors ( 17 ) for the purpose of transmitting these signals to the first receiving unit ( 11 ) under control of the timing signal. 2. Control / monitoring signal transmission system according to claim 1, characterized in that each of the transmitting units ( 12, 15 ) and the receiving units ( 11, 14 ) of the first and second units group a first energy generating device for generating an energy supply voltage of a constant value contains from the pulse-like voltage signal for the purpose of supplying electrical energy to each of the component circuits forming the units. 3. Control / monitoring signal transmission system according to claim 1, characterized in that each of the transmitting units ( 15 ) and each of the receiving units ( 14 ) of the second unit group a second energy generating device for generating an energy supply voltage from the pulse-like voltage signal for the purpose of electrical driving the ge controlled devices ( 16 ) or the sensors ( 17 ) contains. 4. Control / monitoring signal transmission system according to claim 2, characterized in that each of the transmitting units ( 15 ) and each of the receiving units ( 14 ) of the second unit group a second energy generating device for generating an energy supply voltage from the pulse-like voltage signal for the purpose of electrically driving the Controlled devices ( 16 ) or the sensors ( 17 ) contains. 5. Control / monitoring signal transmission system according to claim 1, characterized in that the controlled devices ( 16 ) and the sensors ( 17 ) from the energy supply device of the transmit / receive time control device ( 13 ) via an energy transmission line (P) are electrically driven. 6. Control / supervisory signal transmission system according to claim 1, characterized, that the control data signal and the monitoring signal each because they are binary signals, the value of the impulsarti voltage signals with the binary signals on two dis criminal values is modulated.   7. Control / monitoring signal transmission system according to claim 1, characterized in that the first transmitting unit ( 12 ) of the first unit group and the second receiving unit ( 14 ) of the second unit group in a number of m (where m <1) each provided in pairs are which are assigned to one another in a one-to-one correspondence and are connected to the data signal line in a predetermined sequence in the respective unit group, and in that the first receiving unit ( 11 ) of the first unit group and the second transmitting unit ( 15 ) second unit group in a number of n (where n <1) are each provided in pairs which are assigned to one another in a one-to-one correspondence and are connected to the data signal line in a predetermined sequence in the respective unit group, so that the mutually assigned transmitting and receiving units are operated in succession in the predetermined sequence and the control data ignale and the monitoring signals from and to the respective controlled devices ( 16 ) and sensors ( 17 ) transmitted under the control of the timing signal. The control / supervisory signal transmission system according to claim 7, further characterized by a termination unit ( 18, 19 ) installed in succession to the last stage of the units, which is connected in the predetermined sequence within one of the first and second unit groups, the termination unit includes means for generating a signal of a predetermined waveform upon completion of the operations of all units belonging to the unit group in which the termination unit is installed, and wherein the transmission / reception timing means includes test circuit means for checking the line status of the data signal line in response to the signal of the predetermined waveform. 9. Control / supervisory signal transmission system according to claim 7, characterized, that the timing generator of the transmit / emp catch timing device a first start signal generating device for generating a first start signals contains that each of the transmission units and the Receiving units a second start signal generation device for generating a second start signal contains that the first pair of the associated transmitting unit and receiving unit in the sequence in the first and second unit group based on the first start signal is triggered in the transfer mode that after full ending the operation of the first pair of broadcast and Receiving units the second start signal generation direction the second start signal to trigger the trans operation of a subsequent pair of transmitters and Receiving units in the first and second units group generated, and that the triggering by the second Start signal is repeated until the last pair of Sending and receiving units in the sequence in the Transfer operation is triggered. 10. Control / supervisory signal transmission system according to claim 9, characterized, that the transmitting units and the receiving units together other via a start signal line for routing the second Start signals are connected, the first start signal to the first pair of the transmitter unit and the receiver unit via this data signal line with a below separable waveform is transmitted.   11. Control / supervisory signal transmission system according to claim 9, characterized, that the transmit / receive timing device, the Sending units and the receiving units with each other via start signal lines for carrying the start signals are connected. 12. Control / monitoring signal transmission system according to claim 1, characterized in that the transmitting and receiving units in the first and second unit groups are connected at arbitrarily predetermined locations to the common data signal line,
that the transmission / reception timing control device contains a start signal generating device for generating a start signal which is supplied to the transmitting and receiving units via the data signal line with a distinguishable form of oscillation,
that each of the transmitting and receiving units contains a device for extracting a clock signal from the modulated pulse-like voltage signal, a counter device for counting this clock signal in response to the start signal and an address setting device for holding an address which is assigned to the associated unit, and
that when the count of the counter has reached a value representing this address, the associated unit starts the sending operation or the receiving operation. 13. Control / supervisory signal transmission system according to claim 12, characterized, that a plurality of the receiving units that the first belong to the second unit group, assigned the same address is arranged so that this multitude of receiving units the second group of units simultaneously with one of the Transmitter units can be operated that the first Belong to unit group. 14. Control / supervisory signal transmission system according to claim 12, characterized, that a plurality of the receiving units that the first Belong to the same address group, so that the plurality of receiving units of the first units group operated simultaneously with one of the transmitter units that belong to the second unit group. 15. Control / supervisory signal transmission system according to claim 1, characterized, that the transmitting and receiving units in the first one unit group in a predetermined sequential series follow connected to the common data signal line and that the sending units and the receiving units in the second unit group with the data signal line connected in an arbitrary sequential order are that the transmit / receive timing device includes start signal generating means for generating a start signal that the sending and receiving units the second group via the data signal line with a distinguishable waveform is to be supplied and the Transmitting and receiving unit of the first unit group via a start signal line to start the operation of the transmission and receiving units of the first group in succession in sequential order and that each of the broadcast  and receiving units of the second group of units holds a device for extracting a clock signal from the modulated pulse-like voltage signal, a Counter device for counting the clock signal in response on the start signal and an address setting device for holding an address assigned to the assigned unit is assigned, where if the count is the counter device has reached a value that represents the address represents the assigned unit with the send or Reception starts. 16. Control / supervisory signal transmission system according to claim 1, characterized, that the transmitting and receiving units in the second Unit group via the common data signal line in a predetermined sequential order are connected to each other while the transmitters and the receiving units in the first unit group the data signal line in an arbitrary sequential len order that the transmit / receive Timing device includes a start signal generation device for generating a start signal, the Sending and receiving units of the first unit group via the data signal line in a distinguishable Waveform is to be supplied and the transmit and emp catching unit of the second group via a start signal Line for starting the operation of the transmission and reception units of the second group of units in succession in the sequential order, and that the broadcast and Contain receiving units of the first unit group means for extracting a clock signal from the modulated pulse-like voltage signal, a counter device for counting the clock signal in response the start signal and an address setting device to the Hal th an address assigned to the associated unit  is, when when the count of the counter is one Has reached value that represents this address that associated unit of the first group with the transmit or Reception starts.