DE4003734A1 - Combinatorial logic circuit for incremental encoder error monitoring - checks for typical signal combination and maintenance of encoder supply voltage and current within prescribed limits - Google Patents

Abstract

All signal inputs (2) are referred to a relatively high-impedance voltage divider (4, 5) supplied from a current limiter (11). They are checked by a window comparator (6) against permissible high and low signal levels for input line breakage. Short-circuits are recognised by corresp. truth-table logic (7). Delay stages (20, 21, 13), a level translator (10) and a combinatorial circuit (12) feed a memory (15) with external reset (3) for prodn. of signals denoating whether the encoder is reliable (19) or erroneous (18). USE/ADVANTAGE - Pref. for position or angle sensing in frequency-conversion drives. Rapid error detection is achieved with min. structural complexity.

Description

The invention relates to a circuit arrangement for monitoring egg nes for position detection or rotation angle detection in converters drives, preferably in converters for angle of rotation or rotation sequence detection used incremental encoder for wire break, Lei Closing or failure of the active encoder part.

It is known to avoid serious consequential damage Rapid detection of an actual value encoder fault due to failure of the encoder, due to a wire break or short circuit in the encoder cable from great importance.

The object of the invention is a circuit arrangement to create the type mentioned, which with minimal construction wall allows a quick detection of a fault.

According to the invention the object is achieved in that all encoder signals le on compliance with a defined signal level, the logical sig signals (signal combination) to a combination typical for the encoder and the encoder supply voltage and current consumption on compliance  nes minimum or maximum value monitored and the output signals le of the individual monitoring circuits for a signal "sensor failure" or "Encoder ready for operation".

Further features of the invention emerge from the subclaims.

The invention is explained in more detail below with the aid of the block diagram purifies.

All signal inputs 2 are connected to a high-impedance voltage source 4 , 5 measured with respect to the internal resistance of the encoder, which sets the signal input to the level of voltage source 4 , 5 when the input is open or the signal line is broken. This is preferably achieved by a voltage divider which halves the H signal level 1 . By means of a window comparator 6 , the respective input signal is checked for compliance with the permissible H or L signal level. As a result, detection of a line break in the input signals 2 is given. The detection of line short-circuit of the signal lines is realized via a corresponding evaluation logic 7 (truth table) and accordingly checking the temporal signal sequence.

By limiting the encoder supply current via current limitation 11 and monitoring 11 a and by monitoring the encoder supply voltage 9 to minimum or greater than the maximum permissible values, monitoring of the active encoder part or closure of the encoder supply line 1 is ensured.

The corresponding link 12 of the individual monitoring components enables reliable detection of a “sensor fault” message 12 a, 18 or “ready for operation” message 19 . All possible sources of error for a "sensor fault" are thus recorded.

A further improvement in the circuit arrangement is achieved by introducing the memory element 15 by storing the signal 12 a or 13 a. The memory element 15 can be reset externally via the signal 3 . The outputs of the memory element 15 represent the signals "sensor fault" 18 and "sensor ready" 19 .

By adding the delay element 13 as a filter, an improvement with regard to the interference immunity of the circuit arrangement is achieved.

To further improve the circuit arrangement, it is expedient to suppress encoder-related tolerances and signal falsifications as a result of long encoder lines 2 , which feed the output signals 6 , 7 via the additional supply elements 20 , 21 .

In order to better adapt the signal evaluation logic 6 , 7 , 8 , 20 , 21 to the sensor supply voltage 1 , it is expedient to couple this evaluation logic to the sensor supply voltage 1 and the signals 8 a, 21 a via a corresponding level converter 10 to the other monitoring logic. For further evaluations of the transmitter signal, this is available at the output of the signal processor 14 .

Claims (5)

1. Circuit arrangement for monitoring an incremental encoder used for position detection or rotation angle detection in converter drives, preferably in converters for rotation angle or rotation frequency detection, for line break, line short or failure of the active encoder part, characterized in that all encoder signals ( 2 ) are in compliance with a defined signal level ( 6 ), the logic signals (signal combination) for a combination typical for the encoder ( 7 ) and the encoder supply voltage ( 9 ) and current consumption ( 11 ) for compliance with a minimum or maximum value and the output signals of the individual monitoring circuits to a signal "encoder fault" ( 18 ) or "Transmitter ready for operation" ( 19 ). 2. Circuit arrangement according to claim 1, characterized in that the signal "transmitter fault" ( 18 ) for better evaluation is stored in a memory element ( 15 ). 3. Circuit arrangement according to claim 1 and 2, characterized in that the signal "sensor failure" ( 12 a) for suppressing sensor tolerances and line-related signal delays before evaluation or storage via a delay element ( 13 ) leads GE. 4. Circuit arrangement according to claim 1 to 3, characterized in that for better suppression of encoder tolerances and lei line-related signal delays each signal of the individual monitoring circuits before linking to the signal "encoder fault" ( 18 ) or "encoder ready" ( 19 ) via delay elements ( 20 , 21 ) is performed. 5. Circuit arrangement according to claim 1 to 4, characterized in that the signal monitoring ( 6 , 7 , 8 , 20 , 21 ) is coupled to the sensor supply voltage and is performed for further evaluation via a corresponding level shifter ( 10 ).