DE3928027C2 - Absolute encoder - Google Patents

Description

The invention relates to an absolute encoder with a ko dated disc, which is provided with a first track, wel che carries an absolute drawing pattern and with detector unit ten, which are arranged so that a relative movement between between them and the encoded disc along the first track can be generated.

Linear or rotating type encoders are shown in extensively as detectors to control overfeeds and to stop the positions of various actuators used. If you classify them in any other way, These encoders fall into two broad categories: the incre mental type and the absolute type. The encoder from the incre mental type captures and provides increase and decrease values with a relative movement between a coding element and a detector. The absolute type encoder reads the Re relative position between a coding element and a detector by making a completely periodic arrangement of a Mu sequence (absolute character pattern) on the coding element used. After suitable further processing, the Relative position output as an absolute position.  

A common absolute encoder is, for example, in the Japanese patent publication with the disclosure number 57-175211 and another in Japanese Utility model with publication number 60-152916 described. Encoders of this type work in the following way. In a coding device is a absolute character pattern on a coding element as single track trained. Along this track is one A plurality of detectors arranged at fixed intervals. A binary combination code of readings made by the Magnetic or optical detectors relative to the sign pattern will be brought into an absolute position implemented.

These usual absolute encoders require if they like be operated netically or optically, the arrangement of such many contactless detectors than the number of Bits in the combination code mentioned above. This is done to consist of 1 values and 0 values Make readings that are the absolute drawing pattern form. The distance between the detectors must be exactly Consistent with the gradation level sequence of the absolute Character pattern of the track. This is a requirement Problem with it: It is very difficult to use the encoder Build up and adjust accuracy. Absolute encoder of this type have another problem. If the Direction of the relative movement between the coding element and the detector is reversed, the output signal is off get exactly coded readings of the encoder, after passing a certain number of gradation levels ran. Those attributable to this limitation Reading errors are a difficult hurdle to overcome if the encoder is in bidirectional applications should be used.  

U.S. Patent No. 4,628,298 describes an absolute encoder that has an encoder disc on which two separate absolute encodings are provided to form egg pair of two different tracks on the disc. The Coding on one track is for a shift or Clockwise rotation thought and the other coding on the other track is for a shift or rotation thought counterclockwise. The two codes who taken from different detectors, each on the different tracks are arranged.

The invention has for its object an absolute code rer with the introduction and in the preamble of claim 1 to provide the specified features of the above Problems and limitations with usual absolute coding linked, overcomes and overcomes the need for order of many detectors at fixed intervals along one Track eliminated and a precisely coded signal for the Abso lutposition gives by recording the absolute drawing sters in two places on a drawing pattern track.

This object is achieved according to the invention with the Features from the characterizing part of patent claim 1. Advantageous developments of the invention are in the depend described claims.

A typical embodiment of an encoder for detection solution of the absolute position according to the invention is in the shown following description.

According to the present invention, an encoder is for Detection of an absolute position provided with a knockout dierelement, on which a track with a gradation trained absolute character pattern is arranged and ent with detectors for detecting a relative movement long the track. In particular, to solve the main task the encoder sits a first and a second detector, which are arranged at fixed intervals along the track Interpretation means for recognizing the direction of the relative movement between coding element and detector as forward or backwards as well as a serial / parallel data converter for Conversion of the serial data of the detectors into parallel Output  Data. More specifically, the serial / parallel data is obtained converter separate serial from the first and second detector Data about the relative movement in forward and backward downward direction by moving the data in opposite directions conditions are shifted depending on the output signal of the means of interpretation. The serial thus obtained Data are given in parallel with a given data Number of bits converted for the purpose of forming one Output signal.

When moving relative to the coding element make the two detectors of the invention solutcoder readings of 0 values and 1 values of absolute character pattern in the form of binary coded serial data. The means of interpretation generates a separated output signal depending on the Forward or backward direction of the relative movement between coding element and detector. If the relative Movement in the forward direction becomes serial Data successively from the first detector to the Inter pretation agent supplied. Because the means of interpretation in synchronization with the data transmission Ver push operation in either direction, the serial data of the first detector successively into an output signal from parallel data converted with a predetermined number of bits. If the relative movement is in the backward direction serial data successively from the second detector Means of interpretation supplied. Because the interpretations medium in synchronization with data transmission Shift operation in the other direction causes the serial data of the second detector successively into an output signal from parallel data converted with the given number of bits.  

The absolute character pattern of the coding element provides a completely periodically arranged sequence of signal values coded in binary form with four bits in units of a step sequence of gradations, while a relative movement takes place between the coding element and the detector. In this case, the first and the second detector are arranged at a distance of four step sequences of gradations along the track. The gradations of gradations mean the smallest readable units of the sequence. In the expression

2 ^n-1 <X ≦ 2 ⁿ (1)

in which X is the number of step sequences of the gradation of the indicates absolute character pattern on the coding element the distance from gradation to gradation is generally given by n times λ if λ is the length or the angular range of the Character pattern of a single gradation along the track represents.

In an example in which the means of interpretation by a four-bit shift register with serial input and parallel output is embodied, causes a re relative movement in the forward direction that of the first detector outgoing serial data the input of the register reach that associated with a shift to the right is. There the serial data are consecutively in four-bit parallel data in units of gradation changes. Meanwhile, the second detector detects every time a drawing pattern after five gradations. The one in this Data captured in this manner is effectively the same as that Data shifted out of the shift register if there is a right shift operation carries out. If the movement of the coding element reversed and the relative movement accordingly backwards  runs, a direction identification signal causes the is given by the means of interpretation that the serial data from the second detector which has a shift input of the shift register assigned to the left be fed. The shift register then tracks one left shift operation. this means effectively that the data involved in the shift operation were pushed right out of the register immediately after reversing the movement of the coding element sequentially return to the register by pressing the Follow left shift operation. This has to Consequence that the step sequence is read precisely without a mismatch on the reversal of the relative movement the gradation follows. There is no need to stress that the same functional sequences apply if the return backward movement to the original forward movement returns.

The serial / parallel data converter described above works in synchronization with a signal from serial Data coming from the detectors. At this facility a synchronization signal is used. Typically can this signal be obtained by a detector the binary character arranged at regular intervals samples patterns that run on another parallel Track of the coding element are arranged. In this case something is removed from the detector, which is the output signal of phase A can be designated, and from that another detector becomes an output signal of phase B decreased, the two output signals having a phase have a difference of 90 °. The above mentioned Inter pretation means can contain logic circuits, which is the phase relationship between the two phases detect to obtain a direction identification signal hold.  

According to the present invention, the absolute Character pattern of the coding element in two places by two separated, at a suitable distance from each other ordered detectors read. That of each of the two Serial data obtained through detectors are separated by one of the two data inputs of the shift register and subjected to a shift operation. The direction the shift and the data input become dependent speed of the relative movement between detector and coding element selected in forward or reverse direction. in the The serial data are successive to each other following in parallel data with a predetermined number converted from bits and output as an output signal. This arrangement avoids the possibility of exit errors of the encoder based on a reversal of the relative movement between the coding element and the detector. There, where an absolute drawing pattern is read along a track should be eliminated, a facility after the lying invention the need along the track to provide as many detectors as there are the number of bits which corresponds to the data acquired from the reading form. Only a minimal number of detec is necessary gates to readings with sufficient accuracy receive. These advantages make it easy built absolute encoder to produce the relative can be easily set up and adjusted.

The above mentioned as well as other tasks, features and Advantages of the invention will appear in the description that follows and the accompanying drawings.

The drawings show:  

Fig. 1A is a schematic plan view of an encoded disc for an optical type absolute encoder according to the invention;

Fig. 1B is a circuit diagram of signal processing circuitry for processing the output from detectors due to acquired data output signals;

Fig. 2 is a view for explaining how a shift operation of a shift register used in the encoder is performed;

A view for explaining, as converted by the detector read off serial data in the absolute encoder according to the present invention into parallel data Fig. 3;

Fig. 4 is a view showing several examples of binary gradation arrangements, each of which forms an absolute character pattern with which an absolute position detection signal having a different number of bits is obtained.

In FIGS. 1A and 1B, an embodiment of the present invention is shown in which an absolute encoder elements of the optical type with photoelectric converter operates as detectors.

According to FIG. 1A, a coded disc 1 has a first circular track 2 and a second circular track 3 which are concentrically arranged. The first circular track 2 has an absolute character pattern, which is composed of gradations with 0 values and 1 values, each of which is given by transparent and opaque parts. The second circular track 3 has an incremental drawing pattern, which is given by 16 identical parts, opaque and transparent parts alternating in succession.

The absolute character pattern arranged on the first circular track 1 delivers a signal in the four-bit absolute code in a completely periodic arrangement. The code signal is formed by 16 equally divided sections of the circumference of the track (a section corresponds to π / 8 rad.). The first circular track 2 in FIG. 1A has four adjoining 0 values or transparent gradations, clockwise from the 12 o'clock position, two adjoining 1 values or opaque gradations, a single 0 value or transparent gradation, a single 1-value or opaque gradation, a single 0-value or transparent gradation, four adjacent 1-values or opaque gradations, two adjacent 0-values or transparent gradations and a single 1-value or opaque gradation. This means that the step sequence of this character pattern is formed as:

0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 1

In Fig. 1A λ, the length of a single gradation of the steps referred to in sequence along the track 2. Since the number of gradations in the embodiment according to FIG. 1A is 16, one gradation corresponds to 22.5 ° angular degrees (= 360 ° / 16; π / 8 rad.).

The second inner track 3 has an incremental character pattern, through which a clock signal for synchronization between the interpreting signal and the above-described process of converting serial to parallel data is obtained. Track 3 has 16 identical parts, with opaque and transparent parts appearing alternately and each part having the length of a single gradation λ (angular range). The 16 gradations thus form the incremental drawing pattern.

The encoded disk 1 has optical sensors 4 R, 4 L, 5 A and 5 B, each of which has a light source and a photoelectric conversion element on the opposite side of the disk. The encoded disk 1 and the detectors can rotate relative to one another about a central axis of rotation 6 . The first optical sensor 4 R and the second optical sensor 4 L are arranged offset from one another at a distance of 4λ along the track 2 and are used to read the absolute character pattern. The optical sensors 5 A and 5 B form a pair and are arranged at a distance λ / 2 offset from one another along the track 3 . They are used to read the incremental character pattern.

Fig. 1B is a block diagram showing a typical signal processing circuit for processing the output signals obtained from the readings of the optical sensors 4 R, 4 L, 5 A and 5 B. The output signal of the optical sensor 4 R and the output signal of the sensor 4 L are each improved by a pulse shaper stage 10 R and a pulse shaper stage 10 L with respect to their waveform. This process gives rise to serial data which are based on the absolute character pattern and represent a square wave signal. The serial data of the optical sensor 4 R arrive at the input of a shift register 12 assigned to a shift to the right. The serial data of the optical sensor 4 L reach the input of this shift register assigned to a shift to the left.

In the meantime, a signal with phase A, the output signal of the optical sensor 5 A, and a signal with phase B, the output signal of the optical sensor 5 B, are each in the same way by a pulse shaper stage 10 A and a pulse shaper stage 10 B improved in their waveform. The signals arrive in an interpreting circuit 14 . The interpreting circuit 14 provides a "1" to the shift register when the phase A signal leads the phase B signal. Circuit 14 provides a "0" to register 12 when the phase B signal leads the phase A signal. Either the signal with phase A or the signal with phase B triggers a monostable multivibrator 16 . A pulse is generated there on the front and rear edges of the signal. The pulse train is supplied to the shift register 12 as shift clock pulses which correspond to the 16 gradations on the circumference of the encoded disk 1 . In the present case, the timing for the rise and fall of the triggering signal triggering is preferably synchronized with the approximate center of the pulse width of a single square wave. This means that the trigger signal is a signal which triggers the flip-flop 16 to generate the shift clock signal. The pulse width, whose un dangerous center, as mentioned above, is preferred for synchronization, results as a square wave, which corresponds to the smallest effective reading unit in the serial data, which arrive at the inputs of the shift register 12 assigned to the shift to the right and to the left . The synchronization described above is intended to address the growing possibility that unsuitable data will enter shift register 12 when more serial data is supplied to register 12 with a timing closer to the leading or trailing edge of a square wave of the serial data . The appropriate timing can easily be selected by a suitable determination of the phase difference between two combinations of the arrangement of the detectors on the tracks, namely track 2 for the absolute character pattern with the detectors 4 R and 4 L and track 3 for the incremental Pattern with detectors 5 A and 5 B.

When a clock pulse arrives, shift register 12 takes the serial data described above bit by bit through its inputs for right and left shift. The data is stored in an inner stage of the register after shifting to the right or left, depending on the input used. The shift input and the shift direction are selected using a direction identification signal provided by the interpreting circuit 14 . If the direction identification signal has the value "1", the shift register accepts serial data from the detector 12 R 4, and performs a shift operation to the right. When the direction identification signal is "0", the shift register 12 takes serial data from the detector 4 L and performs a shift operation to the left. If the shift register is of the four-bit type, as in this example, it has four stages. At the mutually parallel outputs 20 a, 20 b, 20 c and 20 d of the stages, an output signal appears with four-bit parallel data and the timing of the clock pulses described above. In this way, the four outputs 20 a-d deliver a four-digit binary-coded signal in a different 0-1 combination for each section of π / 8 rad. on the coded disc 1 .

Fig. 2 shows how the serial data is transferred to the shift register 12 , the register performing its right or left shift operation as the relative movement between the encoded disc and the detectors is switched in their direction. In the present case, the movement is considered as forward movement when the track 2 of the encoded disc 1 moves to the left with respect to the fixed detectors. (In Fig. 1A, the relative movement that occurs when the encoded disc 1 moves counterclockwise is considered the forward direction.) The relative movement is considered backward when it is in the opposite direction.

In Fig. 2, the letters A, B, C,. . . I the absolute track 2 0 values and 1 values. As shown below the absolute track 2 , displacement pulses from the monostable multivibrator 16 hit in the order a, b, c,. . . i with a center of each gradation correspond to the timing when the encoded disc 1 moves in the forward direction. When the coded disc 1 moves backwards, the pulses hit in the order i ', h', g ',. . . a 'a.

When the encoded disc 1 moves in the forward direction, the shift register 12 takes serial data from the first detector 4 R through its leftmost stage to successively perform shift operations to the right in accordance with the above-described shift clock pulses a, b, c,. . . i. When the relative movement is backward, the shift register 12 takes serial data from the second detector 4 L through its rightmost stage to perform successive left shift operations in accordance with the shift clock pulses i ', h', g ',. . . a '. This procedure is also shown in FIG. 2.

In the sub- figure ( 1 ) of Fig. 2, the contents of the four-bit shift register 12 are shown at the time in which the detector 4 R is positioned at position A of track 2 and at clock pulse a the value A in the am furthest left stage of the shift register 12 sends. When the track 2 moves in the forward direction, the shift register 12 performs shift operations to the right on the shift clock pulses b to d, and the register contents change to the state shown in sub- figure ( 2 ) of FIG. 2. The address code corresponding to the detector 4 R as it is arranged is DCBA. If the coded disc 1 moves further in the forward direction, the register contents change according to sub-figure ( 3 ) for the shift clock pulses and corresponding to sub-figure ( 4 ) for the shift clock pulse f. At this time, the second detector 4 L reaches the point B on the track 2 and outputs the data signal B. Part B represents the data part that has just been shifted out of the shift register, as shown in FIG. 2. When the encoded disc 1 with the contents shown in sub-figure ( 4 ) moves backward, the shift register 12 performs a shift operation to the left, which is based on a direction identification signal output from the interpreter circuit 14 . The incoming clock pulse displacement movement immediately after the reversal of the relative f 'causes the shift register 12, the data B in its rightmost stage by the second detector 4 L take over. The resulting contents of the register are shown in sub-figure ( 5 ). In follow the backward movement of the shift clock pulses e effect ', d', etc. that the data A and the following data from the detector 4 L in the shift register 12 via its right lying farthest stage are taken, as shown in Sub-figure (6) . The data is shifted to the left within the register. In this way, the outputs 20 a-d, which are assigned to the corresponding stages of the shift register 12 , always show correct output signals from the encoder.

The absolute character pattern is explained below. In the embodiment according to FIG. 1 with N = 4, the number of gradations is 16 (= 2 ^N ) as described above. As can be seen from Fig. 1A, the absolute character pattern on the track 2 is arranged such that whenever four adjacent gradations are gradually shifted along the circumference of the encoded disk 1 , the entire rotation of the encoded disk 1 is never the same 0-1 combination for the code signal is formed by these four gradations. In this way you get for the absolute character pattern described above:

0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 1

If output 20 a is assigned to number 2 ⁰ , output 20 b to number 2 ¹ , output 20 c to number 2 ² and output 20 d to number 2 ³ , the relative rotation angle of π / 8 rad appears at intervals . a four-bit absolute signal with different contents. In Fig. 3 a each absolute signal associated with the output value is represented in hexadecimal notation to the right.

As can be seen from FIG. 3, the binary digits corresponding to all combinations of four adjacent gradations form 16 hexadecimal values if they are used unchanged in the format of a four-bit binary code.

When the coded disk 1 is rotated through 360 °, none of the combinations of adjacent four gradations forms the same value. This means that an absolute encoder is provided.

An absolute character pattern is made in the following way arranged. If the number of bits and the number of Gradations are sufficiently small for an absolute code the absolute character pattern can be found by trying. As these numbers grow, it becomes necessary Use computers to arrange the drawing pattern.

If a four-bit absolute code signal is desired, can the procedure for arranging the absolute character pattern in in the following way. There are more necessary wise a case where all four meet adjacent bits represent 0 values. Therefore appears always the combination of four adjacent 0 values. Should a fifth "0" appear, the same combination can be encoded. For this reason a "1" to the four adjacent 0 values consequences. In this way, a "0" or a "1" following each individual gradation shift four-bit combination added without doing the same Bit combination is generated.

The result of the calculations described above with a computer is shown in sub-figures (a) to (d) of FIG. 4.

Sub- figure (a) of Fig. 4 shows a case in which the binary gradations compose a five-bit absolute code with N = 5. Sub-figure (b) of FIG. 4 represents a six-bit absolute code which is formed from binary gradations with N = 6. Sub- figure (c) of Fig. 4 shows an eight-bit absolute code formed from binary gradations with N = 8. Sub-figure (d) of Fig. 4 shows a 10-bit absolute code, which is made of binary gradations with N = 10 ago .

The sub-figures (b), (c) and (d) of FIG. 4 each show a gradation arrangement in which the last gradation of each line is connected without interruption to the first bit of the next line, so that a single absolute code is formed.

When each of these gradation arrangements in Fig. 4 is applied to a rotating encoder, the last gradation of the last line follows the first gradation of the first line without interruption, so that a loop is formed.

When using any of the grada described above it is possible to make an absolute sign to form patterns on a single track. This means, that an absolute encoder according to the present invention apparently the same size as the comparable one incremental encoder.

In addition to the rotating encoder, its preferred Embodiment described above is the invention also on linear encoders for reading positions along a straight line direction applicable. In this case, a coding element, that moves relative to the detectors, an absolute one Character pattern that is linear in the direction of Relative movement runs. The invention is not just based on Optical type encoder as described in that  Embodiment applicable, but also to absolute Magnetic type encoders and other types using different reception principles work.

Claims (5)

1. absolute encoder with a coded disc which is provided with a first track which transmits an absolute Zeichenmu art and that relative movement between them and co-founded disc can be generated with detector units, which are arranged along the first track terized by , a first detector ( 4 R) and a second detector ( 4 L) as detector units which are arranged at a predetermined distance from one another along the first track ( 2 ) bearing the absolute character pattern;

• 1. an evaluation unit ( 14 ) for detecting whether the direction of the relative movement between the detectors ( 4 R, 4 L) and the coded disc ( 1 ) is forward by the disc ( 1 ) from the second detector ( 4 L) the first detector ( 4 R) is moved towards or backwards by moving the disk ( 1 ) from the first detector ( 4 R) towards the second detector ( 4 L);
• 2. a serial / parallel data converter ( 12 ) for the selective reception and shifting of serial data from one of the detectors ( 4 R, 4 L) depending on an output signal of the evaluation unit ( 14 ) for converting the shifted serial data into parallel data with a predetermined number of bits as an output signal such that the serial data of the first detector ( 4 R) are selectively received and shifted in the forward direction when the relative movement is in the forward direction, and that the serial data of the second detector ( 4 L) is selective received and shifted in the backward direction when the relative movement is in the backward direction.

2. Absolute encoder according to claim 1, characterized in that the serial / parallel data converter has a shift register ( 12 ) with serial input and parallel output, which has a pair of shift inputs for mutually opposite displacements, serial data from the first detector ( 4 R) one shift input (R / 1) and serial data from the second detector ( 4 L) to the other shift input (L / 1) of the shift register ( 12 ). 3. Absolute encoder according to claim 1 or 2, characterized by

• 1. a second track ( 3 ) which carries an incremental binary character pattern and is arranged parallel to the first track ( 2 ) on the encoded disc ( 1 );
• 2. additional detectors ( 5 A, 5 B) for generating a periodic square-wave signal corresponding to the relative movement by reading the binary character pattern from the second track ( 3 );
• 3. a unit ( 16 ) for generating clock pulses for synchronizing the square-wave signal with the operation of the serial / parallel data converter ( 12 ).

4. Absolute encoder according to claim 3, characterized in that the additional detectors ( 5 A, 5 B) each emit a square-wave signal with phase A and a square-wave signal with phase 8 , which are phase-shifted by 90 ° relative to one another, and the evaluation unit ( 14 ) the phase difference between the square wave signal with phase A and the square wave signal with phase B detected to generate a direction detection signal using a logic circuit. 5. Absolute encoder according to claim 3 or 4, characterized in that the unit ( 16 ) for generating clock pulses generates a clock pulse which is approximately synchronized to the center of the pulse width of a single square wave, which is the smallest effective reading unit in the serial / Parallel data converter ( 12 ) corresponds to incoming serial data.