DE3870593D1 - Zweistufige synchronisiereinrichtung. - Google Patents

Zweistufige synchronisiereinrichtung.

Info

Publication number
DE3870593D1
DE3870593D1 DE8888310990T DE3870593T DE3870593D1 DE 3870593 D1 DE3870593 D1 DE 3870593D1 DE 8888310990 T DE8888310990 T DE 8888310990T DE 3870593 T DE3870593 T DE 3870593T DE 3870593 D1 DE3870593 D1 DE 3870593D1
Authority
DE
Germany
Prior art keywords
stage synchronizer
synchronizer
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888310990T
Other languages
English (en)
Inventor
Martin W Sanner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
Original Assignee
Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Application granted granted Critical
Publication of DE3870593D1 publication Critical patent/DE3870593D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
DE8888310990T 1987-11-30 1988-11-21 Zweistufige synchronisiereinrichtung. Expired - Fee Related DE3870593D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/126,997 US4821295A (en) 1987-11-30 1987-11-30 Two-stage synchronizer

Publications (1)

Publication Number Publication Date
DE3870593D1 true DE3870593D1 (de) 1992-06-04

Family

ID=22427796

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888310990T Expired - Fee Related DE3870593D1 (de) 1987-11-30 1988-11-21 Zweistufige synchronisiereinrichtung.

Country Status (6)

Country Link
US (1) US4821295A (de)
EP (1) EP0319184B1 (de)
JP (1) JP2641276B2 (de)
AU (1) AU616217B2 (de)
CA (1) CA1310711C (de)
DE (1) DE3870593D1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1301260C (en) * 1988-01-21 1992-05-19 Norio Yoshida Synchronizer for establishing synchronization between data and clock signals
US5796781A (en) * 1993-07-09 1998-08-18 Technitrol, Inc. Data receiver having bias restoration
US5533054A (en) * 1993-07-09 1996-07-02 Technitrol, Inc. Multi-level data transmitter
US5530727A (en) * 1994-02-28 1996-06-25 Unisys Corporation Half synchronizer circuit interface system
US5539784A (en) * 1994-09-30 1996-07-23 At&T Corp. Refined timing recovery circuit
US5606276A (en) * 1994-10-05 1997-02-25 Altera Corporation Method and apparatus for creating a large delay in a pulse in a layout efficient manner
US5721886A (en) * 1995-11-30 1998-02-24 Ncr Corporation Synchronizer circuit which controls switching of clocks based upon synchronicity, asynchronicity, or change in frequency
US5818886A (en) * 1996-08-22 1998-10-06 Unisys Corporation Pulse synchronizing module
KR100853465B1 (ko) * 2006-06-29 2008-08-21 주식회사 하이닉스반도체 내부리드신호 생성회로와 이를 포함하는 반도체 메모리장치
US7925912B1 (en) * 2006-07-31 2011-04-12 Marvell International Ltd. Method and apparatus for fine edge control on integrated circuit outputs

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5577255A (en) * 1978-12-06 1980-06-10 Mitsubishi Electric Corp Timing correction circuit
GB8328951D0 (en) * 1983-10-29 1983-11-30 Plessey Co Plc Frequency and phase synchronising arrangements
GB8506100D0 (en) * 1985-03-08 1985-04-11 Int Computers Ltd Decoder
US4700346A (en) * 1985-05-10 1987-10-13 Tandem Computers Incorporated Self-checking, dual railed, leading edge synchronizer
ATE58026T1 (de) * 1985-08-19 1990-11-15 Siemens Ag Synchronisierungseinrichtung.
US4663769A (en) * 1985-10-02 1987-05-05 Motorola, Inc. Clock acquisition indicator circuit for NRZ data
JPS62222731A (ja) * 1986-03-25 1987-09-30 Mitsubishi Electric Corp 非同期入力信号同期化回路
JPH084262B2 (ja) * 1986-03-31 1996-01-17 日本電気株式会社 ビツト同期回路及び方法
JPH0671257B2 (ja) * 1986-06-02 1994-09-07 テクトロニックス・インコ−ポレイテッド 位相選択可能なフリップ・フロップ

Also Published As

Publication number Publication date
AU616217B2 (en) 1991-10-24
AU2490888A (en) 1989-06-01
EP0319184A1 (de) 1989-06-07
EP0319184B1 (de) 1992-04-29
US4821295A (en) 1989-04-11
JP2641276B2 (ja) 1997-08-13
CA1310711C (en) 1992-11-24
JPH022236A (ja) 1990-01-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee