DE3853708D1 - Gerät zur Korrektur von einfachen Bitfehlern und zur Erkennung von doppelten Bitfehlern bei Datenübertragung. - Google Patents
Gerät zur Korrektur von einfachen Bitfehlern und zur Erkennung von doppelten Bitfehlern bei Datenübertragung.Info
- Publication number
- DE3853708D1 DE3853708D1 DE3853708T DE3853708T DE3853708D1 DE 3853708 D1 DE3853708 D1 DE 3853708D1 DE 3853708 T DE3853708 T DE 3853708T DE 3853708 T DE3853708 T DE 3853708T DE 3853708 D1 DE3853708 D1 DE 3853708D1
- Authority
- DE
- Germany
- Prior art keywords
- bit errors
- correction
- detection
- data transmission
- during data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/102,519 US4868829A (en) | 1987-09-29 | 1987-09-29 | Apparatus useful for correction of single bit errors in the transmission of data |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3853708D1 true DE3853708D1 (de) | 1995-06-08 |
DE3853708T2 DE3853708T2 (de) | 1995-09-07 |
Family
ID=22290290
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3853708T Expired - Lifetime DE3853708T2 (de) | 1987-09-29 | 1988-07-19 | Gerät zur Korrektur von einfachen Bitfehlern und zur Erkennung von doppelten Bitfehlern bei Datenübertragung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4868829A (de) |
EP (1) | EP0310220B1 (de) |
JP (1) | JP2732862B2 (de) |
CA (1) | CA1314998C (de) |
DE (1) | DE3853708T2 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5539754A (en) * | 1992-10-05 | 1996-07-23 | Hewlett-Packard Company | Method and circuitry for generating syndrome bits within an error correction and detection circuit |
JP2003529998A (ja) * | 2000-03-31 | 2003-10-07 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | エラー訂正集積回路および方法 |
JP2002082813A (ja) | 2000-06-26 | 2002-03-22 | Nippon Computer:Kk | プログラムロジック装置 |
FR2823035B1 (fr) * | 2001-04-03 | 2003-07-11 | St Microelectronics Sa | Code de detection et/ou de correction d'erreurs a haute efficacite |
US7103832B2 (en) | 2003-12-04 | 2006-09-05 | International Business Machines Corporation | Scalable cyclic redundancy check circuit |
FR2892576A1 (fr) * | 2005-10-25 | 2007-04-27 | Univ Paris Sud | Procede et dispositif de correction d'erreur dans des circuits electroniques de traitement de donnees. |
DE102007023803B4 (de) | 2007-05-21 | 2009-11-05 | Schott Ag | Verfahren zur Herstellung von Schichtsystemen mit Zwischenschichten sowie Gegenstand mit Schichtsystem mit Zwischenschichten |
KR101860809B1 (ko) | 2015-09-30 | 2018-07-06 | 서울대학교산학협력단 | 메모리 시스템 및 메모리 에러 정정 방법 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3623155A (en) * | 1969-12-24 | 1971-11-23 | Ibm | Optimum apparatus and method for check bit generation and error detection, location and correction |
US3601798A (en) * | 1970-02-03 | 1971-08-24 | Ibm | Error correcting and detecting systems |
US3648239A (en) * | 1970-06-30 | 1972-03-07 | Ibm | System for translating to and from single error correction-double error detection hamming code and byte parity code |
US3825893A (en) * | 1973-05-29 | 1974-07-23 | Ibm | Modular distributed error detection and correction apparatus and method |
JPS5144767A (ja) * | 1974-10-14 | 1976-04-16 | Aisin Seiki | Chiruteingubarubu |
DE3122381A1 (de) * | 1981-06-05 | 1982-12-23 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren und einrichtung zur erzeugung von pruefbits zur sicherung eines datenwortes |
JPS60142430A (ja) * | 1983-12-28 | 1985-07-27 | Fujitsu Ltd | 誤り訂正・検出装置 |
-
1987
- 1987-09-29 US US07/102,519 patent/US4868829A/en not_active Expired - Lifetime
-
1988
- 1988-07-19 DE DE3853708T patent/DE3853708T2/de not_active Expired - Lifetime
- 1988-07-19 EP EP88306590A patent/EP0310220B1/de not_active Expired - Lifetime
- 1988-09-28 CA CA000578735A patent/CA1314998C/en not_active Expired - Lifetime
- 1988-09-28 JP JP63243729A patent/JP2732862B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH01112826A (ja) | 1989-05-01 |
JP2732862B2 (ja) | 1998-03-30 |
EP0310220B1 (de) | 1995-05-03 |
US4868829A (en) | 1989-09-19 |
EP0310220A3 (de) | 1991-03-06 |
CA1314998C (en) | 1993-03-23 |
DE3853708T2 (de) | 1995-09-07 |
EP0310220A2 (de) | 1989-04-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE), |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE |