DE3850896D1 - Vector access to memory. - Google Patents

Vector access to memory.

Info

Publication number
DE3850896D1
DE3850896D1 DE3850896T DE3850896T DE3850896D1 DE 3850896 D1 DE3850896 D1 DE 3850896D1 DE 3850896 T DE3850896 T DE 3850896T DE 3850896 T DE3850896 T DE 3850896T DE 3850896 D1 DE3850896 D1 DE 3850896D1
Authority
DE
Germany
Prior art keywords
memory
vector access
vector
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850896T
Other languages
German (de)
Other versions
DE3850896T2 (en
Inventor
Masayuki C O Fujitsu Lim Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3850896D1 publication Critical patent/DE3850896D1/en
Publication of DE3850896T2 publication Critical patent/DE3850896T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
DE3850896T 1987-03-13 1988-03-11 Vector access to memory. Expired - Fee Related DE3850896T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62059484A JPS63225837A (en) 1987-03-13 1987-03-13 System for vector access with distance

Publications (2)

Publication Number Publication Date
DE3850896D1 true DE3850896D1 (en) 1994-09-08
DE3850896T2 DE3850896T2 (en) 1994-12-22

Family

ID=13114624

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850896T Expired - Fee Related DE3850896T2 (en) 1987-03-13 1988-03-11 Vector access to memory.

Country Status (7)

Country Link
US (1) US5134695A (en)
EP (1) EP0282070B1 (en)
JP (1) JPS63225837A (en)
KR (1) KR910007026B1 (en)
AU (1) AU599762B2 (en)
CA (1) CA1295423C (en)
DE (1) DE3850896T2 (en)

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EP0346031B1 (en) * 1988-06-07 1997-12-29 Fujitsu Limited Vector data processing apparatus
CA2086229A1 (en) * 1990-06-27 1991-12-28 Warren Marwood Number theory mapping generator for addressing matrix structures
JP2899986B2 (en) * 1990-08-08 1999-06-02 株式会社日立製作所 Data storage method, vector data buffer device and vector data processing device
JP2718254B2 (en) * 1990-10-02 1998-02-25 日本電気株式会社 Vector processing equipment
JP2625277B2 (en) * 1991-05-20 1997-07-02 富士通株式会社 Memory access device
US5377340A (en) * 1991-06-18 1994-12-27 Hewlett-Packard Company Method and apparatus for memory interleaving using an improved hashing scheme
JPH05210573A (en) * 1992-01-31 1993-08-20 Fujitsu Ltd Address generating method
US5379393A (en) * 1992-05-14 1995-01-03 The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations Cache memory system for vector processing
US5463749A (en) * 1993-01-13 1995-10-31 Dsp Semiconductors Ltd Simplified cyclical buffer
US5513364A (en) * 1993-03-09 1996-04-30 Matsushita Electric Industrial Co., Ltd. Data transfer device and multiprocessor system
JP2875448B2 (en) * 1993-03-17 1999-03-31 松下電器産業株式会社 Data transfer device and multiprocessor system
US5537156A (en) * 1994-03-24 1996-07-16 Eastman Kodak Company Frame buffer address generator for the mulitple format display of multiple format source video
ES2116852B1 (en) * 1994-08-29 1999-03-16 Univ Catalunya Politecnica SYNCHRONIZATION OF MEMORY ACCESS IN VECTOR MULTIPROCESSORS.
WO1996037050A1 (en) * 1995-05-15 1996-11-21 Advanced Hardware Architectures, Inc. Reconfigurable interleaver/deinterleaver and address generator for data streams interleaved according to one of a plurality of interleaving schemes
SE514348C2 (en) 1995-06-09 2001-02-12 Saab Dynamics Ab Memory structure adapted for storing and retrieving vectors
US6507629B1 (en) 1998-04-07 2003-01-14 Sony Corporation Address generator, interleave unit, deinterleave unit, and transmission unit
US6295575B1 (en) * 1998-06-29 2001-09-25 Emc Corporation Configuring vectors of logical storage units for data storage partitioning and sharing
US6912616B2 (en) * 2002-11-12 2005-06-28 Hewlett-Packard Development Company, L.P. Mapping addresses to memory banks based on at least one mathematical relationship
GB2415336B (en) * 2004-06-18 2006-11-08 Toshiba Res Europ Ltd Bit interleaver for a mimo system
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7464225B2 (en) 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US8356138B1 (en) * 2007-08-20 2013-01-15 Xilinx, Inc. Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)
US20100199067A1 (en) * 2009-02-02 2010-08-05 International Business Machines Corporation Split Vector Loads and Stores with Stride Separated Words
EP2466472A1 (en) * 2010-12-17 2012-06-20 ST-Ericsson SA Vector-based matching circuit for data streams
US10180829B2 (en) * 2015-12-15 2019-01-15 Nxp Usa, Inc. System and method for modulo addressing vectorization with invariant code motion

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US3597745A (en) * 1969-08-19 1971-08-03 Kaiser Aluminium Chem Corp Method for arrangement and indexing of digital data in storage
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US4055851A (en) * 1976-02-13 1977-10-25 Digital Equipment Corporation Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle
US4333160A (en) * 1978-11-20 1982-06-01 Victor Company Of Japan, Ltd. Memory control system
US4352165A (en) * 1979-12-17 1982-09-28 The Gerber Scientific Instrument Company Apparatus for storing and retrieving data
US4370732A (en) * 1980-09-15 1983-01-25 Ibm Corporation Skewed matrix address generator
US4598403A (en) * 1981-04-16 1986-07-01 Sony Corporation Encoding method for error correction
US4438512A (en) * 1981-09-08 1984-03-20 International Business Machines Corporation Method and apparatus for verifying storage apparatus addressing
DD208499A3 (en) * 1982-10-26 1984-05-02 Adw Ddr MULTI-DIMENSIONAL PARALLEL MEMORY
US4613935A (en) * 1983-02-02 1986-09-23 Couleur John F Method and apparatus for pipe line processing with a single arithmetic logic unit
US4727474A (en) * 1983-02-18 1988-02-23 Loral Corporation Staging memory for massively parallel processor
US4901230A (en) * 1983-04-25 1990-02-13 Cray Research, Inc. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
JPS6069746A (en) * 1983-09-26 1985-04-20 Fujitsu Ltd Control system of vector data processor
JPS60156151A (en) * 1983-12-23 1985-08-16 Nec Corp Memory access controlling device
JPS60136870A (en) * 1983-12-26 1985-07-20 Hitachi Ltd Vector processor
FR2573888B1 (en) * 1984-11-23 1987-01-16 Sintra SYSTEM FOR THE SIMULTANEOUS TRANSMISSION OF DATA BLOCKS OR VECTORS BETWEEN A MEMORY AND ONE OR MORE DATA PROCESSING UNITS
US4855903A (en) * 1984-12-20 1989-08-08 State University Of New York Topologically-distributed-memory multiprocessor computer
US4819152A (en) * 1985-04-05 1989-04-04 Raytheon Company Method and apparatus for addressing a memory by array transformations
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US4727510A (en) * 1985-05-24 1988-02-23 Unisys Corporation System for addressing a multibank memory system
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JPH0628051B2 (en) * 1986-04-25 1994-04-13 株式会社日立製作所 Memory control method

Also Published As

Publication number Publication date
CA1295423C (en) 1992-02-04
DE3850896T2 (en) 1994-12-22
EP0282070B1 (en) 1994-08-03
KR910007026B1 (en) 1991-09-16
US5134695A (en) 1992-07-28
EP0282070A2 (en) 1988-09-14
JPS63225837A (en) 1988-09-20
AU1277788A (en) 1988-09-15
KR880011677A (en) 1988-10-29
AU599762B2 (en) 1990-07-26
EP0282070A3 (en) 1990-10-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee