DE3824510A1 - Read-write memory - Google Patents

Read-write memory

Info

Publication number
DE3824510A1
DE3824510A1 DE19883824510 DE3824510A DE3824510A1 DE 3824510 A1 DE3824510 A1 DE 3824510A1 DE 19883824510 DE19883824510 DE 19883824510 DE 3824510 A DE3824510 A DE 3824510A DE 3824510 A1 DE3824510 A1 DE 3824510A1
Authority
DE
Germany
Prior art keywords
read
memory cells
row
memory
column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19883824510
Other languages
German (de)
Inventor
Norbert Dipl Ing Budnik
Wilhelm Dipl Ing Doerr
Manfred Dipl Ing Schmid
Rudolf Ing Grad Morlang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bosch Telecom GmbH
Original Assignee
ANT Nachrichtentechnik GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ANT Nachrichtentechnik GmbH filed Critical ANT Nachrichtentechnik GmbH
Priority to DE19883824510 priority Critical patent/DE3824510A1/en
Publication of DE3824510A1 publication Critical patent/DE3824510A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Read-write memory for digital information storage in electrical communication engineering. In known read-write memories, one memory cell is provided for storage of each bit. The memory cells are arranged in rows and columns. For writing and reading the information, only one memory cell at a time is addressed. The intention is to extend the technology of writing and reading by the new read-write memory. Optionally, all memory cells of one row or column are addressed. The data word to be written or read contains as many bits as there are memory cells in one row or column, and such a data word is written to all memory cells of a row or column, or read from the memory cells of a row, simultaneously.
DE19883824510 1988-07-20 1988-07-20 Read-write memory Withdrawn DE3824510A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19883824510 DE3824510A1 (en) 1988-07-20 1988-07-20 Read-write memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19883824510 DE3824510A1 (en) 1988-07-20 1988-07-20 Read-write memory

Publications (1)

Publication Number Publication Date
DE3824510A1 true DE3824510A1 (en) 1990-01-25

Family

ID=6359056

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19883824510 Withdrawn DE3824510A1 (en) 1988-07-20 1988-07-20 Read-write memory

Country Status (1)

Country Link
DE (1) DE3824510A1 (en)

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