DE3816845C1 - Binary correlator - Google Patents

Abstract

The invention concerns a binary correlator (1), to determine the agreement or correlation in time of two binary signals (S1, S2), which are written into two shift registers (3, 4). The contents of the shift registers are compared with each other in a comparison circuit (7-i), and a counter circuit (8-i, 9-i) and an evaluation circuit (10-i, 11-i, 12) are connected in series after this comparison circuit. According to the invention, it is proposed that all outputs of the memory positions of the second shift register (4) and the output of the first shift register (3) are connected to coincidence gates (7-i), to each of which a resettable binary counter (8-i) and then a buffer register (10-i) are connected in series. The buffer registers are read via multiplexers under the control of a microcomputer (12). After each transfer of the contents of the binary counter (8-i) into the buffer registers (10-i), the binary counters are reset and set to a new counter state, with the advantage that the content of the buffer registers (10-i), except the last bit, is written into the counters. The period at which the counter states are reset can be chosen by the microcomputer (12). A decay time of the memory is thus implemented in the binary correlator. <IMAGE>

Description

The invention relates to a binary correlator according to the Oberbe handle of claim 1.

Such a binary correlator is known from DE-PS 26 29 740. This Binary correlator has two parallel shift registers into which the both signals are written after corresponding analog / digital conversion will. The shift registers have a different number of storage locations, preferably one shift register each because one memory location has more than the other shift register. Only the last memory location of the two shift registers is after the Full letter combined with the input of the assigned shift register which, at the same time the outputs of the analog / digital converter from the Inputs of the shift registers are separated. The one in the two shoots Binary signal sequences present in registers are clocked in the way in circulation that in the manner of a gear transmission with two wheels of at least one tooth with different numbers of teeth a binary signal sequence delayed by at least one bit same binary signal sequence revolves. The revolving bits of the binary Ren signal sequences are serial with each other in a comparison scarf tion, in the simplest case compared in a coincidence gate. The An The number of matching bits per revolution are counted. Every circulation thus corresponds to a different local assignment of the Spei places in the two shift registers corresponding to one under different temporal shift of the two signals to each other. The Number of the circulation in which the largest number of matches moods then corresponds to the time shift, at which the maximum degree of correlation of the two signals is present.

This binary correlator has a simple circuit structure, however the disadvantage that the comparison of the two binary signal sequences several  Round trips, d. H. Requires shifts within the shift registers. Each according to the number of available storage spaces in the shift registers and the round trips necessary for the correlation result therefore last the comparison process more or less long. Besides, it is not possible, another signal sequence into the during the comparison process Register shift registers so that the effective time during the the signal sequences can be written into the shift register, is shortened accordingly.

In the book of the NATO ADVANCED STUDY INSTITUTE on "Signal Processing with emphasis on underwater acoustics ", published by Center d'´tude des ph´nomènes al´atoires de Grenoble are a series of pre lazily printed at a conference in Grenoble between the 14th and September 26, 1964. On pages 141 ff. Is a Correlator specified, in which a temporally parallel correlation two signal sequences occur; see. in particular Fig. 6 on p. 146 with associated description. The signal to be examined is at this Correlator assigned to the individual memory locations of a shift register leads, each memory location is connected to a tap. These taps are each led to a multiplier, the information of a reference signal corresponding to second outputs be forwarded. The output of each multiplier is one Low pass filter connected to the results of each multiplication rers integrated. The low-pass filters are turned off via a multiplexer asked. With this arrangement, the one in a query process Displacement of the two signals can be determined at which the correlation has a maximum.

This partially analog structure of a parallel correlator has the Advantage over a purely digital structure that the low-pass filter have a decay time predetermined by the time constant, so that each more or less signals depending on the size of this decay time previous comparison cycles when querying the low-pass filter be done. The size of the time constant defines the "Ge  memory "or the" memory time "of the correlator.

The aforementioned correlator according to DE-PS 26 29 740 has because of the pure digital circuitry no such cooldown, although this is for practice is essential.

The invention has for its object to suit a binary correlator ben, on which a cooldown of the memory rea can be lized.

This object is according to the invention by the in the characterizing part of claim 1 specified features solved.

In such an embodiment of a binary correlator, on the one hand a temporally parallel correlation of the two signals at difference Lichen local allocations of the storage spaces in the two slides register according to different time shifts of the two signals to each other, like this one in principle Correlator according to the literature from SIGNAL PROCESSING is known.

On the other hand, the back is in a purely digital circuit design interconnection of counters and buffer registers manage the cooldown of the memory of the binary correlator the setting of the averaging time constant for the respective user adapt and vary. The counter readings of the binary counters are periodically transferred to buffer registers and with the help of Off read out multiplexers. After resetting the Counters are reloaded, preferably by the fact that the Contents of the buffer register with the exception of the last bit as new The counter reading can be written into the binary counter. By that measure The meter reading is halved with each new setting. The period, with which the meter readings are read out and reset is for The averaging time constants can be varied freely.  

The binary correlator according to the invention is made by a microcomputer controlled. The preferred reset of the counter readings to half The content of the buffer register hardly loads and enables the microcomputer nevertheless the adjustment of the averaging time constant. In addition, through this resetting the counting process is hardly interrupted. The shorter the Period with which to reset, the smaller the averaging time constant and the faster it happens through the repeated halfie Ren of the counter reading also the decay of the "memory" of the binary correlators. With such a selectable averaging time constant can also be a correlation adapted to the respective application result can be determined. Is namely the time difference between the If the two signal sequences are approximately stationary, then a high averaging can also occur time constant selected and accordingly the binary counters only relative rarely be reset. However, the time difference changes exercise between the two signal sequences, the counter reading is removed reset more frequently, d. H. before the shift itself has changed significantly, which is due to a low averaging time constant is determined.

As an application example for the use of a binary correlator according to the Invention, for. B. mentioned an acoustic DF sensor. This consists in simplest case from two sound recorders with a signal preprocessing beitungselektronik, the binary correlator according to the invention and one Microcomputer. In active and semi-active applications, there is still one Sound transmitter added.

The function of the acoustic DF sensor is passive and half active applications in noise sources or noise reflectors due to the different duration of the noise signals to the sound Bearing sensors is a so-called correlation bearing. With ak tive applications comes the distance determination of noise ref due to the duration of the noise signals.

Properties and performance characteristics of the sound transmitter, the sound recording  mer, the signal preprocessing electronics and the microcomputer hang strongly depends on the application and area of application. These components are however available in any desired version on the market.

Further areas of application and application for a binary correlator according to the invention are e.g. B. ultrasound diagnostics in medicine, the Ultrasonic testing of materials and materials, the ultrasonic order input scanning as a blind aid, use with passive and in ultra active acoustic alarm devices operating in the sound area Object protection, passive direction finders for localizing noise sources in environmental protection, but also in the military area, as well as pas active and active acoustic seekers in the military sector.

A binary correlator according to the invention is not only available because of its range of application, but also because of its structure for integra tion. It processes the signals purely digitally, has a bus structure and can be operated directly with a microcomputer. The binary correla The gate is preferably modular and consists essentially of simple shift registers, coincidence gates and binary counters.

The invention is in one embodiment based on the single figure explained in more detail, in which a block diagram of a binary correlator is posed.

In order to compare two signals S 1 and S 2 in a binary correlator 1 , the first signal S 1 is possibly written into a first shift register 3 , which has (n + 1) memory locations, via an upstream register 2 . Only the last memory location with the number (n + 1) is shown here. The second signal S 2 is also written into a second shift register 4 after analog-digital conversion, which has (2 n + 1) memory locations. Only the memory locations 1, 2 and (2 n + 1) are indicated. The last memory location with the number (n + 1) of the first shift register 3 has a tap 5 , whereas all memory locations of the second shift register are each provided with a tap 6 - i . The taps 6-1, 6-2 and 6- (2 n + 1) for the associated memory locations are shown. These taps are each fed to a coincidence gate 7 - i , the second input of which is connected to the tap 5 of the first shift register. Also in the coincidence gates, similar to the following circuit elements, only the gates associated with memory locations 1, 2 and (2 n + 1) are shown. Each coincidence gate 7 - i is followed by a programmable m -bit binary counter 8 - i , whereby binary counters 9 - i can optionally be provided between the coincidence gates 7 - i and the programmable binary counters 8 - i in order to achieve the counter clock at very high clock frequencies the programmable binary counter. Each programmable binary counter 8 - i is followed by a buffer register 10 - i , likewise with m digits, the outputs of which are each connected to an output multiplexer 11 - i .

The described binary correlator 1 is controlled by a microprocessor 12 which specifies the clock for the writing and evaluation of the signals S 1 and S 2 . The binary counters 8 - i , the buffer registers 10 - i and the output multiplexers 11 - i are controlled via a decoder 13 , which is connected to the bus system 14 of the microcomputer 12 , specifically there with address and control lines 15 and 16 . The counters of the programmable binary counters 8 - i are periodically taken over for all binary counters simultaneously in the associated buffer registers 10 - i and then successively read out via the output multiplexer 11 - i controlled by the microcomputer 12 via data lines 17 of the bus system 14 . The binary counters are then reset to a new counter reading by writing the contents of the buffer register into the binary counters with the exception of the last bit. The period with which the counter readings are read out and reset is selectable by the microprocessor 12, depending on the application. If the correlation peak moves slowly, the period with which the binary counters are reset is extended accordingly, which corresponds to a "long memory" of the binary correlator, if the correlation peak moves quickly, then this period is chosen to be shorter.

The two signals S 1 and S 2 are clocked and written into the two shift registers 3 and 4 , a known time delay between the two signals being able to be compensated for by the ballast register 2 . With the clock, the content of the last memory location (n + 1) of the first shift register and the respective content of all memory locations of the second shift register are fed to the coincidence gates 7 - i . At the inputs of the coincidence gate 7 - i there are therefore two bits from the bit sequence of the two binary signals S 1 and S 2 , which are shifted by (- n) clock pulses. At the input of the second coincidence gate 7-2 , the shift is (- n + 1) etc. until this shift at the last coincidence gate 7- (2 n + 1) is exactly n clocks. This corresponds to a temporal shift of the two signal sequences to one another symmetrically in both directions.

If the two bits at the inputs of a coincidence gate are the same, the associated binary counter 8 - i or the counter arrangement from the two counters 9 - i and 8 - i continues to count by one. The contents of the binary counters 8 - i are transferred into the buffer registers after a number of clock cycles determined by the microcomputer 12 . Their contents are then read out successively by the microcomputer 12 via the output multiplexers.

The entire binary correlator with the microcomputer is a module in in tegrierter circuit design, so that a variety of applications possible. The single module of the binary correlator is through the broken lines on both sides of the circuit slide gram limited. In this way, both sides of this module the same modules are connected, so that the binary correlator can be enlarged almost arbitrarily without the signal processing changes something.

Claims (5)

1. Binary correlator for determining the correspondence or temporal correlation of two binary signals, each consisting of a bit sequence, with two shift registers for writing the first or second signal into successive memory locations, a comparison circuit with taps at memory locations of the two shift registers is connected to compare the bits written in the one shift register with the bits written in the other shift register with different local assignments of the memory locations in the two shift registers corresponding to different temporal shifts of the two signals to one another, and with a counting and evaluation circuit for Counting and evaluating the match of the bits of both signals depending on the different local assignments of the memory locations in the two shift registers, characterized in that all outputs of the memory locations of the second shift register are ers ( 4 ) and the output of the first shift register ( 3 ) are connected to coincidence gates ( 7 - i) that the coincidence gates ( 7 - i) each have a resettable binary counter ( 8 - i) and this one buffer register ( 10 - i ) is connected downstream, which can be read out via multiplexers, and that the binary counters ( 8 - i) can be reset with a selectable period and a part of the contents of the buffer registers ( 10 - i) can then be written into them. 2. Binary correlator according to claim 1, characterized in that the new counter reading of the binary counter ( 8 - i) the content of the associated buffer register ( 10 - i) with the exception of the last bit (halved counter status) in the respective binary counter ( 8 - i ) can be registered. 3. Binary correlator according to claim 1 or 2, characterized in that the programmable binary counters ( 8 - i) each have a binary counter ( 9 - i) connected in front to reduce the counting cycle. 4. Binary correlator according to one of the preceding claims, characterized in that the binary correlator ( 1 ) with a microcomputer ( 12 ) for controlling the counter ( 8 - i) , the buffer register ( 10 - i) and the multiplexer ( 11 - i) is provided. 5. Binary correlator according to one of the preceding claims, characterized in that the first shift register ( 3 ) (n + 1) and the second shift register ( 4 ) (2 n + 1) have memory locations.