DE3813154C2 - - Google Patents

Description

The invention relates to a circuit with the The preamble of claim 1 features specified.

In the case of known synchronous counters, the changes to Counter value available counter outputs exactly when the rising (or falling) occurs Edges of the counting pulses. After a certain number of Counts, which depend on the number of bits of the counter and the entered via the counter's preset inputs Depends on the preset value, the synchronous counter gives one Overflow pulse. If you want to re-synchronize the counter load with a preset value, this must Charging isochronously with the next rising one (or falling) edge of the counting pulse happen.  

From the book "Digital Circuits and Circuits" by Prof. Dr.-Ing. Manfred Seifart, edited by Dr. Alfred Hüthig Verlag Heidelberg in 1982, pp. 172-174, a presettable counter is already known. To the flip-flops of this Counting units of the counter set so that at the beginning of the Count the preset number is stored. From the counters count from this preset number backwards to the count position 0. When the Counting position 0 generates an overflow pulse and the Charging input of the counter fed so that the counter can be preset again immediately.

Furthermore, from Japanese patent application 63-9229 Frequency counter known in which the loading of the Preselection depending on one not closer certain phase signal (phase signal) takes place.

The invention has for its object a circuit of the type specified in the preamble of claim 1 to further develop that a isochronous new loading of the Synchronous counter is always ensured.  

This task is carried out in a circuit according to the Preamble of claim 1 by the in the characterizing Part of claim 1 specified features solved. A advantageous use of the in claim 1 described circuit is described in claim 2.

The advantages of the claimed circuit exist in particular in that by the in claim 1 Linking of the (inverted) counting pulses described generates a charge enable pulse with the overflow pulse throughout its duration, the one Corresponds to the occurrence of the next rising (or falling) edge of the Counting pulse is serviced. This edge serves as temporal reference for the next count cycle. Farther when this edge occurs, the counter is marked with a desired value is preset.

Further properties of the claimed circuit result from the exemplary explanation of the invention with reference to FIGS. 1 and 2.

It shows

Fig. 1 is a block diagram of the claimed circuit, and

Fig. 2 is a diagram for describing the operation of the circuit shown in Fig. 1.

Fig. 1 shows a block diagram of the claimed circuit. This contains a synchronous counter 1 , a D flip-flop 2 and an inverter 3 .

The synchronous counter 1 has a counting pulse input T 1 , a charging pulse input L, preset inputs V ₁ . . . V ₄ counter outputs Q ₁ ... Q ₄ and an output Ü for an overflow pulse.

The D-Fip-Flop 2 has a clock signal input T 2 , a data input D and an output Q.

The counting pulses Z are present at the input of the circuit shown in FIG. 1. These are fed directly to the counting pulse input T 1 of the synchronous counter 2 and to the clock signal input T 2 of the D flip-flop 2 via the inverter 3 .

The output Ü of the synchronous counter 1 is connected to the data input D of the D flip-flop 2 and the charge pulse input L of the synchronous counter 1 to the data output Q of the D flip-flop 2 .

The mode of operation of the circuit shown in FIG. 1 is described below with the aid of FIG. 2.

FIG. 2a shows the counting pulses Z applied to the input of the circuit, that of FIG . . . 17 are numbered. FIG. 2b shows the inverted Z counts, the 2 of the D flip-flop 2 are supplied as clock signal to the clock input T. The signals Q ₁ , Q ₂ , Q ₃ and Q ₄ shown in FIGS. 2c, 2d, 2e and 2f describe the current count of the synchronous counter 1 . The overflow pulse can be seen from FIG. 2g. The signal shown in FIG. 2h finally shows the charge enable pulse present at the output Q of the D flip-flop 2 or at the input L of the synchronous counter 2 .

The overflow pulse is generated when all of the signals Q ₁ , Q ₂ , Q ₃ and Q _{4 have} a logic LOW level. This is the case in the time interval between t ₀ and t ₂ . This overflow pulse is present at the data input D of the D flip-flop 2 .

When the next rising plank of the inverted count pulse, which is present at the clock signal input T 2 of the D flip-flop 2 , ie at time t ₁ , the charge enable pulse is generated at the output Q of the D flip flop 2 and the charge pulse input L of the synchronous counter 1 fed. The charge enable pulse remains until the next rising edge of the inverted count pulse, which occurs at time t ₃ . The charge release pulse is thus present for the entire time interval between t ₁ and t ₃ . During this entire time interval is basically charging the synchronous counter one of his load inputs _V1. . . V ₄ possible.

The charging process takes place when the rising edge of the (first) counting pulse Z occurs within the time interval between t ₁ and t _3. According to FIG. _{2 a,} this rising edge occurs at time t ₂ and is therefore in the middle of the available time interval t ₁ and t ₃ . This ensures that there is enough time to prepare for the charging process. Consequently, even if there are slight time shifts between the pulses, it is ensured that the charging process takes place synchronously with the counting pulse. Such time shifts could be caused, for example, by inaccuracies in level changes (transitions from HIGH to LOW and vice versa), while undefined or illegal states always occur during their duration.

The aforementioned time t ₂ thus serves as a reference time at which the synchronous counter 1 uses its preset inputs V ₁ . . . V _{4 is} loaded with an externally definable preset value. In the present example, a HIGH level is present as a preset value at all preset inputs, which corresponds to the decimal number 15. The counter begins to count from this preset value. Are at all counter outputs Q ₁ . . . Q ₄ LOW level again (time interval t ₄ to t ₆ ), the next overflow pulse Ü is generated. When the next rising edge of the inverted count pulse occurs at time t ₅ , the next charge enable pulse L is generated which lasts until time t ₇ . During this time interval between t ₅ and t ₇ , the next rising edge of the count pulse Z is waited for. This occurs at time t ₆ . The time t ₆ is thus the next reference time at which the synchronous counter 1 is reloaded and from which the counter starts to count again, etc.

A preferred application example is the use of the claimed circuit in a video recorder with image memory. By means of the image memory, for example, a television picture reproduced from a magnetic tape is to be compressed in such a way that it can be superimposed as a small picture on the screen of a television receiver connected to the video recorder. For this purpose, the reproduced television picture is divided into a plurality of blocks, each of which consists of m × n pixels. Data is reduced within each block. For this data reduction, the values stored in the image memory must be read from the image memory block by block and line by line within each block using a suitable addressing circuit. This addressing circuit requires presettable address counters, the presetting value having to be changeable from counting cycle to counting cycle in order, for example, to be able to jump from one memory area to another. Furthermore, this address counter must work without jitter and without clock loss. All of this can be achieved if the circuit described in connection with FIGS. 1 and 2 is used.

Claims (2)

1. Circuit for controlling the loading of a counting pulse input, a charging pulse input, preset inputs, counter outputs and an output for a synchronous counter having an overflow pulse, characterized in that

• - The overflow pulse () fed to the data input (D) of a flip-flop ( 2 ),
• - the counting pulses () are inverted in an inverter ( 3 ),
• - The inverted counting pulses () are fed to the clock signal input (T 2 ) of the flip-flop ( 2 ), and
• - The signal received at the output (Q) of the flip-flop ( 2 ) is fed as a charge enable pulse () to the charge pulse input (L) of the synchronous counter.

2. Circuit according to claim 1, characterized characterized that they are at the Addressing an image memory is used.