EP0242446B1 - Duty ratio measuring system for variable frequency pulses - Google Patents

Description

The invention is based on a system for measuring the pulse duty factor of pulses of variable frequency, in particular in electronically controlled fuel injection systems for internal combustion engines.

Methods have been known for measuring the pulse duty factor (pulse width / period), in particular in the case of electronically controlled fuel injection systems for internal combustion engines, in which two separate counters are used. The period is determined using the first counter, while the pulse width is measured using the second counter. The quotient of the two measurement results is then formed by an arithmetic operation.

When using this method, it is necessary to determine the resolution of the result in advance depending on the incoming frequency. In particular, if the frequency of the pulses to be measured is subject to large fluctuations, the counter must be designed for the period with a very large capacity because of the low frequencies, so that no overflow occurs if one wishes to achieve a still satisfactory resolution at high frequencies.

The object of the invention is to provide a system for measuring the pulse duty factor of pulses of variable frequency, in which a measurement with a required resolution can be carried out with the least possible technical effort within a wide frequency range.

The system according to the invention is characterized in that clock pulses are derived, the frequency of which corresponds to a predetermined multiple of the frequency of the pulses (input pulses), and that the pulse duty factor is determined by counting the clock pulses during each pulse.

The system according to the invention has the advantage that the pulse duty factor can be measured in a wide frequency range with the same resolution, with counters and other digital circuits being designed only for the number of digits required for the required resolution.

According to a first development of the invention, the frequency of the clock pulses can be derived by measuring the period of the pulses and forming the reciprocal of the measurement result and multiplying it by a constant that corresponds to the multiple.

A second development of the invention consists in that a controllable oscillator, a frequency and phase comparison circuit and a frequency divider are provided for deriving the clock pulses. This enables, for example, the use of commercially available modules, in particular a PLL circuit.

An advantageous embodiment of the invention is given in that the clock pulses are fed to a first input and the input pulses to a second input of an AND gate and that a counter is connected to the output of the AND gate.

A further embodiment of the invention is characterized in that a D register is connected to the output of the counter, which is clocked with pulses which are derived from the input pulses and fed to the D register via a second OR gate. In particular, the D register enables a measured value to be available during the entire period of the pulses to be measured.

In some applications of the system according to the invention, in particular when used in electronically controlled injection systems, it can happen that the pulse duty factor becomes either 0% or 100%. With a duty cycle of 0% there are no pulses, but only a DC voltage with a "0" level and with a duty cycle of 100% a DC voltage with a "1" level. In both cases, no period or pulse frequency can be determined.

A further development of the invention therefore provides that means are provided for determining whether a pulse duty factor of 100% is present and that a predetermined value is output at a pulse duty factor of 100%.

Various configurations are possible for this purpose. It can be assumed that, in particular, circuits in accordance with the developments mentioned serve to determine a pulse duty factor of 100%, and that at a pulse duty factor of 0%, the counter remains at 0 anyway due to the lack of input pulses.

Another development is that the pulse width is determined independently of the pulse frequency and that a duty cycle of 100% is assumed when a limit value is exceeded and that the limit value is derived from the pulse width of a previous pulse.

This development allows a determination of whether there is a duty cycle of 100% even with strongly fluctuating frequencies and pulse widths, although it is assumed that these fluctuations are subject to a certain inertia. However, these requirements are met in the envisaged applications of the system according to the invention further developed.

• Fig. 1 ein erstes Ausführungsbeispiel, bei dem die Periodendauer mit Hilfe von arithmetischen Operationen gemessen wird,
• Fig. 2 ein zweites Ausführungsbeispiel mit einer PLL-Schaltung, wobei die Regelspannung der PLL-Schaltung zur Ermittlung, ob Eingangsimpulse anliegen, verwendet wird,
• Fig. 3 ein drittes Ausführungsbeispiel ebenfalls mit einer PLL-Schaltung, bei welcher jedoch mittels eines Zählers ein Tastverhältnis von 100 % erkannt wird, und
• Fig. 4 ein viertes Ausführungsbeispiel, bei welchem eine adaptive Ermittlung des Tastverhältnisses von 100 % erfolgt.

The invention allows numerous embodiments. Four of them are shown schematically in the drawing using several figures and described below. It shows:

• 1 shows a first embodiment in which the period is measured using arithmetic operations,
• 2 shows a second exemplary embodiment with a PLL circuit, the control voltage of the PLL circuit being used to determine whether input pulses are present,
• Fig. 3 shows a third embodiment also with a PLL circuit, in which, however, a pulse duty factor of 100% is detected by means of a counter, and
• Fig. 4 shows a fourth embodiment in which an adaptive determination of the duty cycle of 100% takes place.

Identical parts are provided with the same reference symbols in the figures.

The exemplary embodiment shown in FIG. 1 is supplied with 1 pulses, the pulse duty factor T1 / T of which is to be measured. So that the system can process pulses of both polarities, a switch 2 and a negation stage are provided at input 1. In order to derive clock pulses which correspond to a predetermined multiple of the frequency of the pulses supplied at 1 (input pulses), the pulses are first fed to a circuit 4 for measuring the period T. This can be done, for example, by counting pulses with a significantly higher frequency during a period of the input pulses. The output signal of the circuit 4 is then fed to an arithmetic circuit 5, which calculates the frequency of the pulses supplied at 1 by reciprocal value formation and multiplies the value obtained by a constant C. The constant C is supplied from a corresponding memory 6 to the arithmetic circuit 5.

At the output of the arithmetic circuit 5 there are pulses whose frequency corresponds to a predetermined multiple of the frequency of the input pulses. The value of the multiple depends on the required resolution of the measurement result.

From the circuit 5, the pulses are fed to an input of a triple AND gate 7. The input pulses processed in a pulse shaper 8 are fed to a further input of the triple AND gate 7.

For the further explanations, it is first assumed that a 1 is applied to the third input of the triple AND gate 7. The triple AND gate 7 accordingly causes the clock pulses specified by the circuit 5 to be passed to the n-bit counter 9 only during the occurrence of the input pulses. The counter reading reached after a pulse corresponds to the duty cycle because of the coupling of the frequencies of the clock pulses and the input pulses. The count result V can then be taken from the output of the n-bit counter 9. At the beginning of each input pulse, the n-bit counter 9 is set to 0. For this purpose, a corresponding signal is supplied to the n-bit counter by a control block 10.

In the embodiment shown in FIG. 1, however, the control block has further tasks, which are explained below. Particularly in the case of electronically controlled fuel injection systems, it can happen that the input pulses supplied at 1 either become so wide that they become a continuous voltage (duty cycle 100%) or the injection is switched off completely, so that the duty cycle becomes 0. In this case, the circuits 4 and 5 no longer allow the frequency of the input pulses to be determined, so that no corresponding clock pulses can be derived.

The circuits 11 and 12 together with the control block 10 already mentioned and a level detector 13 are used to record these operating states. The recording of these operating states takes place in the form of a so-called time-out monitoring in a dynamic manner. In the preferred application of the invention it can be assumed that the frequency and the width of the input pulses change only relatively slowly because of the inertia of the internal combustion engine, while a change in the pulse width occurs suddenly when a duty cycle of 100% is reached. For this purpose, the pulse width is first measured in a circuit 11. A limit value is formed from this in the circuit 12, which is at most to be expected for the following pulse. This can be done by addition or multiplication. The width of the following pulse is compared with this value.

If the width of the pulse that follows is greater, it can be concluded that the pulse width is 100%. The control block 10 releases via line 14 an input register of the n-bit counter 9 provided for the constant C, whereby the counter reading assumes the value of the constant C. At the same time, the third input of the triple AND gate 7 is set to a value of 0 by the control block 10 via the line 15, so that the counter remains at the value C.

While the pulse duty factor of the input pulses remains at 100%, the input signal is continuously compared with the limit value which was determined from the last individual pulse before the transition to the pulse duty factor of 100%. This enables a termination of the 100% duty cycle to be recognized and the subsequent individual pulse to be checked again as described.

In order to achieve a correct result even in the event that the pulse width T1 approaches 0, such a case is determined in the level detector 13. The output of the level detector 13 is connected to an input of the control block, from which, in the absence of pulses via a line 16, the n-bit counter 9 is set to 0 and prevents further counting via the line 15 and the triple AND gate 7 becomes. With the level detector 13 it is additionally achieved that the required starting conditions can be created when the system is switched on.

The system shown in FIG. 2 can in turn be used to process pulses of different polarities, for which purpose an input 21 is directly connected and another input 22 is connected via an inverting amplifier 23 and a switch 24. With a frequency divider 25, pulses with half the frequency and with a duty cycle of 50% are generated from the input pulses. These pulses are fed to a PLL circuit 26. The PLL circuit 26 essentially includes a controllable oscillator (VCO) and a frequency and phase comparison circuit.

The output voltage of the controllable oscillator is fed via a frequency divider 27 to an input of the frequency and phase comparison circuit and is compared there with the pulses supplied by the frequency divider 25. A voltage, which represents the result of the comparison, is supplied to the control input of the controllable oscillator via an RC element 28, -29. The described control of the controllable oscillator causes the frequency of the oscillator to assume a value which is greater by the division ratio of the circuit 27 than the frequency of the pulses which are supplied to the PLL circuit 26. The ratio n can be entered at 30 depending on the requirements in individual cases.

The clock pulses are supplied to the counter 32 via the AND circuit 31. The input pulses are fed to a further input of the AND circuit, so that only those clock pulses which occur within a pulse arrive at the counter. The count of the counter 32 thus represents a measure of the duty cycle. The counter reading is written into a D register 33, which in the exemplary embodiment shown is connected to the counter 32 via 8 lines for 1 bit each.

The D register 33 is clocked by the input pulses via an OR circuit 35 and a monostable multivibrator 36. This has the effect that after the counting of the clock pulses the count is transferred to the D register. A delayed reset pulse is generated by the delay circuit 37, which resets the counter to 0 after data has been transferred from the counter 32 to the D register 33.

If there are no input pulses or pulse widths of 100%, the frequency of the signals which are fed to the PLL circuit 26 reaches the value 0. This can be done by monitoring the output voltage of the frequency and phase comparison circuit of the PLL circuit 26 with the aid of a comparator 38 are found. For this purpose, the control voltage of the controllable oscillator is applied to one input of the comparator, while a comparison voltage is supplied to the other input via a voltage divider 39, 40.

If the frequency goes to 0, the output voltage of the comparator 38 assumes the logic value 0, which is fed to an input of the OR gate 41. If the pulse duty factor is 100%, a 0 is present at the other input of the OR gate 41 via the inverter 43. The 0 present at the output of the OR gate 41 causes the counter to be set to the value which corresponds to a pulse duty factor of 100% via the inverting preset input of the counter.

The output voltage of the comparator 38 is also fed to a monostable multivibrator 42, the output signal of which is fed via the OR gate 35 to the clock input of the D register 33. The trailing edge of the output signal of the monostable multivibrator 38 causes the count (100%) to be transferred to the D register 33.

If the pulse duty factor is 0%, a 1 is supplied to the lower input of the OR gate 41 by the inverter 43. Thus there is also a 1 at the output of the OR gate 41, which means that the counter is not set to the preset value, but rather retains the value 0 obtained previously by "Reset". This is then taken over into the D register 33 by the trailing edge of the output signal of the monostable multivibrator 42.

The output of the D register 30 forms the output 34 of the system, from which the measurement result Z can be found.

3, the derivation of a clock signal, the frequency of which corresponds to a multiple of the frequency of the input pulses, the pulse counting, the transfer of the counting result into a D-register and the control of the counter and the D-register as in the system Fig. 2. The determination of whether there is a duty cycle of 100% takes place in a different way in the system according to Fig. 3. For this purpose, a monostable multivibrator 51 generates a pulse of constant width, with which a counter 52 is reset. A signal is fed to the counter 52 as a clock via an input 53 provided for this purpose and via an OR gate 54. The carry output of the counter 52 is connected to a further input of the OR gate 54, so that no further count pulses reach the counter 52 in the event of a carry. The carry signal of the counter 52 is also fed via an inverter 55 to an input of the OR gate 41. Finally, a monostable multivibrator 56 is connected to the carry output of the counter 52, the output of which is connected to an input of the OR gate 35.

The counter 52 is set to 0 at the beginning of each period T of the input signal supplied at 21 and then counts the clock pulses supplied at 53, the frequency of which is substantially higher than that of the input pulses. The capacity of the counter 52 is now selected such that no carry out takes place within a clock period T of the input pulses. As long as the pulse width T1 has not reached 100%, the counter 52 is set to 0 at the beginning of each clock period T. If, however, 100% duty cycle is reached, the reset is not necessary and after a predetermined number of pulses of the clock signal supplied at 53, a 1 is present at the carry output of the counter 52. By returning the carry output of the counter 52 via the OR gate 54, the counter is stopped, so that the carry remains at the output until a reset pulse comes from the input 21 via the monostable multivibrator 51.

The further processing of the information that there is a duty cycle of 100% takes place in the same way as in the system according to FIG. 2, so that a further description of the signal curves after the monostable multivibrator 56 and the inverter 55 is unnecessary.

While a constant pulse width is assumed in the system according to FIG. 3 to determine whether the pulse duty factor is 100%, the in Fig. 4 system provided an adaptive determination. In particular when using the system according to the invention in electronic fuel injection, it can be assumed that both the frequency (corresponding to the engine speed) and the pulse width (duration of the individual injection) do not change suddenly. If a sudden change nevertheless occurs in the pulse width, this allows the conclusion of a transition to a pulse duty factor of 100%.

To carry out this adaptive or sliding determination, the input pulses in the system according to FIG. 4 are fed to a circuit 61 for measuring the period duration. This can be done in a manner known per se by counting pulses during a period, the frequency of the counting pulses being substantially greater than the frequency of the input pulses.

In an arithmetic logic unit 62, the measured period T is multiplied by a constant stored at 63 or this constant is added to the period. Corresponding signals for selection between multiplication and addition can be supplied at the inputs 64 and 65. A constant adapted to the respective application can be entered via input 66.

At the output of the arithmetic logic unit there is then a value Tmax, which corresponds to the period that can be expected as a maximum without a duty cycle of 100% being achieved. This value is delayed at 67 by a period T and compared in a comparator 68 with the period of the following period. If the period T (1) is greater than the maximum period Tmax (0) determined from the previous period, then a 0 is supplied from the comparison circuit 68 to the monostable multivibrator 42 and the OR gate 41, which is already the case in connection with FIG 2 triggers the functions described.

Claims (15)

1. System for measuring the duty ratio of variable-frequency pulses, especially in electronically controlled fuel injection systems for internal-combustion engines, characterised in that clock pulses are derived whose frequency corresponds #o a predetermined multiple of the frequency of the pulses (input pulses) and that the duty ratio is determined by counting the clock pulses during each pulse.

2. System according to claim 1, characterised in that the period of the pulses is measured, and the reciprocal of the measurement result is formed and multiplied with a constant corresponding to the multiple.

3. System according to claim 1, characterised in that a variable oscillator, a frequency and phase comparison circuit and a frequency divider are provided for deriving the clock pulses.

4. System according to one of claims 8 and 9, characterised in that the clock pulses are fed to a first input and the input pulses to a second input of an AND-gate (7, 31) and that a counter (9, 32) is connected to the output of the AND-gate (7, 31).

5. System according to claim 4, characterised in that the counter (9, 32) is resettable with pulses which are derived from the input pulses through a delay arrangement.

6. System according to claim 5, characterised in that the counter (9, 32) is settable to a predetermined value by signals which are fed via a first OR-gate (41).

7. System according to one of claims 4 to 6, characterised in that there is connected to the output of the counts (32) a D-register (33) which is clocked with pulses which are derived from the input pulses and fed to the D-register via a second OR-gate (35).

8. System according to claim 1, characterised in that means are provided for ascertaining whether a duty ratio of 100 % obtains, and that when a duty ratio of 100 % obtains a predetermined value is issued.

9. System according to claims 7 and 8, characterised in that the means are connected to one input of the first OR-gate (41) and via a monostable multivibrator to one input of the second OR-gate (35).

10. System according to claim 8, characterised in that the means for ascertaining whether the duty ratio present is 100 % comprise a comparator (38) to which the output voltage of a frequency and phase comparison circuit (26) is fed on the one hand and a comparison voltage is fed on the other hand.

11. System according to claim 8, characterised in that the means for ascertaining if a duty ratio of 100 % obtains comprise a counter (52) with a transfer output, which is resettable by the input pulses, that the clock input of the counter (52) is connected to the output of an OR-gate (54), that one input of the OR-gate (54) has count pulses applied to it, and that the other input of the OR-gate (54) is connected to the transfer output.

12. System according to claim 8, characterised in that the pulse width is determined independently of the pulse frequency, and that when a limit value is exceeded a duty ratio of 100 % is assumed.

13. System according to claim 12, characterised in that the limit value is derived from the pulse width of a preceding pulse.

14. System according to claim 13, characterised in that deriving is effected by adding/subtracting a predetermined value.

15. System according to claim 13, characterised in that deriving is effected by multiplication with a predetermined value.

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