DE3778549D1 - FAST CLOCK DETECTION FOR PARTIAL RESPONSE SIGNALING. - Google Patents

FAST CLOCK DETECTION FOR PARTIAL RESPONSE SIGNALING.

Info

Publication number
DE3778549D1
DE3778549D1 DE8787116783T DE3778549T DE3778549D1 DE 3778549 D1 DE3778549 D1 DE 3778549D1 DE 8787116783 T DE8787116783 T DE 8787116783T DE 3778549 T DE3778549 T DE 3778549T DE 3778549 D1 DE3778549 D1 DE 3778549D1
Authority
DE
Germany
Prior art keywords
sample
delay
reconstructed data
present
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787116783T
Other languages
German (de)
Inventor
Francois Bernard Dolivo
Gottfried Ungerboeck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3778549D1 publication Critical patent/DE3778549D1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4919—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using balanced multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/497—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

In a receiver for data having been sent or recorded as partial-response (PR) signals, there is a system for generating a timing gradient value for initially acquiring the sampling phase when a signal resulting from the transmission of a known preamble is received. A common input (55) receives signal samples Yn of a transmitted or recorded PR signal. A delay circuit (67) has a delay stage, for accepting the present received signal sample Yn and provides at least one previous received signal sample Yn-i. A second delay circuit (61) has at least two delay stages, for accepting a present reconstructed data sample Xn and provides at least a first previous reconstructed data sample Xn-j. A reconstruction circuit (43) is connected to the common input and to the second delay circuit for generating the present reconstructed data sample Xn in response to the present received signal sample Yn and the first previous reconstructed data sample Xn-j. A timing gradient generation circuit (41) is connected to the common input and to the delay circuits for generating the timing gradient value.
DE8787116783T 1987-11-13 1987-11-13 FAST CLOCK DETECTION FOR PARTIAL RESPONSE SIGNALING. Expired - Fee Related DE3778549D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP87116783A EP0316459B1 (en) 1987-11-13 1987-11-13 Fast timing acquisition for partial-response signalling

Publications (1)

Publication Number Publication Date
DE3778549D1 true DE3778549D1 (en) 1992-05-27

Family

ID=8197442

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787116783T Expired - Fee Related DE3778549D1 (en) 1987-11-13 1987-11-13 FAST CLOCK DETECTION FOR PARTIAL RESPONSE SIGNALING.

Country Status (4)

Country Link
US (1) US4890299A (en)
EP (1) EP0316459B1 (en)
JP (1) JPH01143447A (en)
DE (1) DE3778549D1 (en)

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DE68920739T2 (en) * 1989-08-16 1995-06-29 Ibm Data coding for the immediate start of PRML receivers.
EP0413875B1 (en) * 1989-08-21 1994-06-01 International Business Machines Corporation Timing control for modem receivers
US5200981A (en) * 1990-08-07 1993-04-06 National Semiconductor Corporation Fine timing recovery for QAM modem receiver
EP0470450A3 (en) * 1990-08-07 1992-06-24 National Semiconductor Corporation Fine timing recovery for qam modem receiver
GB9019491D0 (en) * 1990-09-06 1990-10-24 Ncr Co Clock recovery for a wireless local area network station
EP0505657A1 (en) * 1991-03-27 1992-09-30 International Business Machines Corporation Preamble recognition and synchronization detection in partial-response systems
JPH05120813A (en) * 1991-10-25 1993-05-18 Sony Corp Phase lock loop circuit
US5255292A (en) * 1992-03-27 1993-10-19 Motorola, Inc. Method and apparatus for modifying a decision-directed clock recovery system
US5258933A (en) * 1992-08-27 1993-11-02 Quantum Corporation Timing control for PRML class IV sampling data detection channel
US5341249A (en) * 1992-08-27 1994-08-23 Quantum Corporation Disk drive using PRML class IV sampling data detection with digital adaptive equalization
JP2574106B2 (en) * 1992-09-01 1997-01-22 富士通株式会社 Clock recovery circuit for magnetic disk drive
US5359631A (en) * 1992-09-30 1994-10-25 Cirrus Logic, Inc. Timing recovery circuit for synchronous waveform sampling
JP2613532B2 (en) * 1992-10-28 1997-05-28 富士通株式会社 Phase locked loop
US5424881A (en) 1993-02-01 1995-06-13 Cirrus Logic, Inc. Synchronous read channel
US5761212A (en) * 1993-07-01 1998-06-02 Cirrus Logic, Inc. Channel quality
US5586150A (en) * 1993-11-24 1996-12-17 Rajupandaram K. Balasubramaniam Method and apparatus for symbol synchronization in multi-level digital FM radio
GB9405487D0 (en) * 1994-03-21 1994-05-04 Rca Thomson Licensing Corp VSB demodulator
KR950034207A (en) * 1994-04-05 1995-12-26 케네스 리 Method and apparatus for eliminating timing phase step induced by ISI at sector start in PRML digital magnetic data storage channel
US5552942A (en) * 1994-08-23 1996-09-03 Quantum Corporation Zero phase start optimization using mean squared error in a PRML recording channel
US5916315A (en) * 1994-08-23 1999-06-29 Ampex Systems Corporation Viterbi detector for class II partial response equalized miller-squared signals
US5414390A (en) * 1994-09-12 1995-05-09 Analog Devices, Inc. Center frequency controlled phase locked loop system
US5787134A (en) * 1994-09-12 1998-07-28 Analog Devices, Inc. Switched capacitance phase locked loop system
US5459757A (en) * 1994-09-21 1995-10-17 Seagate Technology, Inc. Timing and gain control circuit for a PRML read channel
US5576904A (en) * 1994-09-27 1996-11-19 Cirrus Logic, Inc. Timing gradient smoothing circuit in a synchronous read channel
JPH08138324A (en) * 1994-11-11 1996-05-31 Fujitsu Ltd Phase difference detection circuit for epr4 signal
US5585975A (en) * 1994-11-17 1996-12-17 Cirrus Logic, Inc. Equalization for sample value estimation and sequence detection in a sampled amplitude read channel
US5572558A (en) * 1994-11-17 1996-11-05 Cirrus Logic, Inc. PID loop filter for timing recovery in a sampled amplitude read channel
JPH08147887A (en) * 1994-11-18 1996-06-07 Hitachi Ltd Decoding circuit and reproducing device
US5768320A (en) * 1995-09-05 1998-06-16 Analog Devices, Inc. Read system for implementing PR4 and higher order PRML signals
US5841812A (en) * 1995-09-06 1998-11-24 Analog Devices, Inc. NMOS pass transistor digital signal processor for a PRML system
US6429986B1 (en) 1995-09-07 2002-08-06 International Business Machines Corporation Data storage to enhance timing recovery in high density magnetic recording
US5646968A (en) * 1995-11-17 1997-07-08 Analog Devices, Inc. Dynamic phase selector phase locked loop circuit
JP2830803B2 (en) * 1995-11-17 1998-12-02 日本電気株式会社 Phase detector and magnetic disk device using the same
JP3245343B2 (en) * 1995-12-28 2002-01-15 富士通株式会社 Disk device, phase demodulation device for disk device, and phase demodulation method for disk device
JPH09265729A (en) * 1996-03-25 1997-10-07 Fujitsu Ltd Disk device and recording/reproducing method of the disk device
US5825318A (en) * 1996-12-19 1998-10-20 Quantum Corporation Data and servo sampling in synchronous data detection channel
KR100459879B1 (en) * 1998-04-20 2005-01-15 삼성전자주식회사 Nonlinear signal receiver, particularly with regards to stably recovering a sampling time in consideration of a nonlinear distortion of a reproduction signal when sampling the signal
US6519715B1 (en) 1998-05-22 2003-02-11 Hitachi, Ltd. Signal processing apparatus and a data recording and reproducing apparatus including local memory processor
JP2000195191A (en) * 1998-12-28 2000-07-14 Toshiba Corp Signal processing circuit of disk storage device and signal processing method thereof
US6587529B1 (en) * 1999-02-25 2003-07-01 Texas Instruments Incorporated Phase detector architecture for phase error estimating and zero phase restarting
JP3597433B2 (en) * 1999-12-20 2004-12-08 富士通株式会社 Clock adjustment device and optical disk device in data reproduction system
JP3609721B2 (en) * 2000-12-19 2005-01-12 株式会社東芝 Digital data reproducing apparatus and digital data reproducing method
US6879629B2 (en) * 2001-03-12 2005-04-12 Hitachi Global Storage Technologies Netherlands, B.V. Method and apparatus for enhanced timing loop for a PRML data channel
JP2003022625A (en) * 2001-07-10 2003-01-24 Hitachi Ltd Preamble pattern for magnetic recording, and magnetic recorder
US7349507B2 (en) * 2003-06-09 2008-03-25 Intel Corporation Extending PPM tolerance using a tracking data recovery algorithm in a data recovery circuit
US7102839B2 (en) * 2003-10-31 2006-09-05 International Business Machines Corporation Magnetic recording channel utilizing control fields for timing recovery, equalization, amplitude and amplitude asymmetry
US11159304B2 (en) * 2019-05-10 2021-10-26 Nvidia Corporation Clock data recovery mechanism

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1592556A (en) * 1976-10-28 1981-07-08 Rixon Quadrature-amplitude-modulation data transmission systems and transmitters
US4472813A (en) * 1981-03-30 1984-09-18 Nippon Electric Co., Ltd. Transmission system for intentionally violating a class IV partial response code to distinguish subsidiary signals from an error
US4644564A (en) * 1983-08-05 1987-02-17 International Business Machines Corporation Decoding the output signal of a partial-response class-IV communication or recording device channel
US4571734A (en) * 1983-08-05 1986-02-18 International Business Machines Corporation Method and apparatus for decoding the output signal of a partial-response class-IV communication or recording-device channel
US4609907A (en) * 1984-10-31 1986-09-02 International Business Machines Corporation Dual channel partial response system

Also Published As

Publication number Publication date
JPH0578223B2 (en) 1993-10-28
JPH01143447A (en) 1989-06-06
US4890299A (en) 1989-12-26
EP0316459A1 (en) 1989-05-24
EP0316459B1 (en) 1992-04-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee