DE3774818D1 - Binaerer addierer mit festem operand und paralleler/serieller multiplikator mit solchen addierern. - Google Patents
Binaerer addierer mit festem operand und paralleler/serieller multiplikator mit solchen addierern.Info
- Publication number
- DE3774818D1 DE3774818D1 DE8787402069T DE3774818T DE3774818D1 DE 3774818 D1 DE3774818 D1 DE 3774818D1 DE 8787402069 T DE8787402069 T DE 8787402069T DE 3774818 T DE3774818 T DE 3774818T DE 3774818 D1 DE3774818 D1 DE 3774818D1
- Authority
- DE
- Germany
- Prior art keywords
- multiplicator
- adders
- serial
- parallel
- binary adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3876—Alternation of true and inverted stages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Optimization (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8613222A FR2604270B1 (fr) | 1986-09-22 | 1986-09-22 | Additionneur binaire comportant un operande fixe, et multiplieur binaire parallele-serie comprenant un tel additionneur |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3774818D1 true DE3774818D1 (de) | 1992-01-09 |
Family
ID=9339160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8787402069T Expired - Lifetime DE3774818D1 (de) | 1986-09-22 | 1987-09-16 | Binaerer addierer mit festem operand und paralleler/serieller multiplikator mit solchen addierern. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4853887A (de) |
EP (1) | EP0262032B1 (de) |
JP (1) | JPS6389929A (de) |
DE (1) | DE3774818D1 (de) |
FR (1) | FR2604270B1 (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3880409T2 (de) * | 1987-09-23 | 1993-11-25 | France Telecom | Binäre Additions- und Multiplikationsvorrichtung. |
FR2656124A1 (fr) * | 1989-12-15 | 1991-06-21 | Philips Laboratoires Electro | Multiplieur serie programmable. |
US5128890A (en) * | 1991-05-06 | 1992-07-07 | Motorola, Inc. | Apparatus for performing multiplications with reduced power and a method therefor |
US5452466A (en) * | 1993-05-11 | 1995-09-19 | Teknekron Communications Systems, Inc. | Method and apparatus for preforming DCT and IDCT transforms on data signals with a preprocessor, a post-processor, and a controllable shuffle-exchange unit connected between the pre-processor and post-processor |
US5619441A (en) * | 1994-10-14 | 1997-04-08 | International Business Machines Corporation | High speed dynamic binary incrementer |
US5602767A (en) * | 1995-08-29 | 1997-02-11 | Tcsi Corporation | Galois field polynomial multiply/divide circuit and a digital signal processor incorporating same |
US5748071A (en) * | 1996-11-12 | 1998-05-05 | Motorola, Inc. | High speed comparator with programmable reference |
US5958000A (en) * | 1996-11-15 | 1999-09-28 | Samsung Electronics, Co. Ltd. | Two-bit booth multiplier with reduced data path width |
US6539411B1 (en) * | 1998-10-29 | 2003-03-25 | Lucent Technologies Inc. | Direct digital synthesizer |
US6807556B1 (en) * | 2000-10-27 | 2004-10-19 | Synplicity, Inc. | Method and apparatus for parallel carry chains |
US7428278B2 (en) * | 2002-05-09 | 2008-09-23 | Interdigital Technology Corporation | Method and apparatus for parallel midamble cancellation |
US8150902B2 (en) | 2009-06-19 | 2012-04-03 | Singular Computing Llc | Processing with compact arithmetic processing element |
CN102184090B (zh) * | 2011-05-27 | 2013-12-04 | 清华大学 | 一种动态可重构处理器及其固定数的调用方法 |
CN111708512A (zh) * | 2020-07-22 | 2020-09-25 | 深圳比特微电子科技有限公司 | 加法器、运算电路、芯片和计算装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL234515A (de) * | 1957-12-24 | |||
US4153939A (en) * | 1976-01-24 | 1979-05-08 | Nippon Electric Co., Ltd. | Incrementer circuit |
US4417315A (en) * | 1981-07-14 | 1983-11-22 | Rockwell International Corporation | Method and apparatus for incrementing a digital word |
US4417316A (en) * | 1981-07-14 | 1983-11-22 | Rockwell International Corporation | Digital binary increment circuit apparatus |
US4584660A (en) * | 1983-06-22 | 1986-04-22 | Harris Corporation | Reduction of series propagation delay and impedance |
US4700325A (en) * | 1984-02-08 | 1987-10-13 | Hewlett-Packard Company | Binary tree calculations on monolithic integrated circuits |
US4623982A (en) * | 1985-06-10 | 1986-11-18 | Hewlett-Packard Company | Conditional carry techniques for digital processors |
-
1986
- 1986-09-22 FR FR8613222A patent/FR2604270B1/fr not_active Expired - Lifetime
-
1987
- 1987-09-11 US US07/095,214 patent/US4853887A/en not_active Expired - Fee Related
- 1987-09-16 EP EP87402069A patent/EP0262032B1/de not_active Expired - Lifetime
- 1987-09-16 DE DE8787402069T patent/DE3774818D1/de not_active Expired - Lifetime
- 1987-09-21 JP JP62237080A patent/JPS6389929A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
FR2604270B1 (fr) | 1991-10-18 |
FR2604270A1 (fr) | 1988-03-25 |
EP0262032A1 (de) | 1988-03-30 |
EP0262032B1 (de) | 1991-11-27 |
US4853887A (en) | 1989-08-01 |
JPS6389929A (ja) | 1988-04-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |