DE3674981D1 - Testschaltung fuer einen differential-kaskaden-spannungsschalter. - Google Patents

Testschaltung fuer einen differential-kaskaden-spannungsschalter.

Info

Publication number
DE3674981D1
DE3674981D1 DE8686108504T DE3674981T DE3674981D1 DE 3674981 D1 DE3674981 D1 DE 3674981D1 DE 8686108504 T DE8686108504 T DE 8686108504T DE 3674981 T DE3674981 T DE 3674981T DE 3674981 D1 DE3674981 D1 DE 3674981D1
Authority
DE
Germany
Prior art keywords
test circuit
voltage switch
cascade voltage
differential cascade
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686108504T
Other languages
English (en)
Inventor
Edward Scott Kirkpatrick
Eric Paul Kronstadt
Robert Kevin Montoye
Winfried Wolfgang Wilcke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3674981D1 publication Critical patent/DE3674981D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Electronic Switches (AREA)
DE8686108504T 1985-07-29 1986-06-21 Testschaltung fuer einen differential-kaskaden-spannungsschalter. Expired - Fee Related DE3674981D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/759,804 US4656417A (en) 1985-07-29 1985-07-29 Test circuit for differential cascode voltage switch

Publications (1)

Publication Number Publication Date
DE3674981D1 true DE3674981D1 (de) 1990-11-22

Family

ID=25057017

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686108504T Expired - Fee Related DE3674981D1 (de) 1985-07-29 1986-06-21 Testschaltung fuer einen differential-kaskaden-spannungsschalter.

Country Status (5)

Country Link
US (1) US4656417A (de)
EP (1) EP0218794B1 (de)
JP (1) JPS6228679A (de)
CA (1) CA1229384A (de)
DE (1) DE3674981D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4967151A (en) * 1988-08-17 1990-10-30 International Business Machines Corporation Method and apparatus for detecting faults in differential current switching logic circuits
US4935646A (en) * 1989-02-22 1990-06-19 International Business Machines Corporation Fully static CMOS cascode voltage switch logic systems
US5299136A (en) * 1991-06-05 1994-03-29 International Business Machines Corp. Fully testable DCVS circuits with single-track global wiring
US5448164A (en) * 1992-12-24 1995-09-05 Delco Electronics Corp. Electrical test apparatus and method of checking the apparatus
US5389836A (en) * 1993-06-04 1995-02-14 International Business Machines Corporation Branch isolation circuit for cascode voltage switch logic
US5910730A (en) * 1996-12-13 1999-06-08 International Business Machines Corporation Digital circuit noise margin improvement
US5995010A (en) * 1997-01-02 1999-11-30 Texas Instruments Incorporated Output buffer providing testability
US6104213A (en) * 1998-03-02 2000-08-15 International Business Machines Corporation Domino logic circuit having a clocked precharge
US6097207A (en) * 1998-08-21 2000-08-01 International Business Machines Corporation Robust domino circuit design for high stress conditions
US6181155B1 (en) 1999-04-28 2001-01-30 International Business Machines Corporation Method and apparatus for testing dynamic logic using an improved reset pulse
JP3980560B2 (ja) * 2002-04-02 2007-09-26 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ テスト可能なカスコード回路およびそれをテストする方法
CN109522640B (zh) * 2018-11-14 2020-11-27 北京航空航天大学 基于电流再分配的电路系统级联失效传播路径确定方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4183460A (en) * 1977-12-23 1980-01-15 Burroughs Corporation In-situ test and diagnostic circuitry and method for CML chips
DE2905271A1 (de) * 1979-02-12 1980-08-21 Philips Patentverwaltung Integrierte schaltungsanordnung in mos-technik mit feldeffekttransistoren
JPS57107637A (en) * 1980-12-25 1982-07-05 Fujitsu Ltd Ecl integrated circuit

Also Published As

Publication number Publication date
JPS6228679A (ja) 1987-02-06
EP0218794B1 (de) 1990-10-17
CA1229384A (en) 1987-11-17
EP0218794A1 (de) 1987-04-22
US4656417A (en) 1987-04-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee