DE3650413T2 - Verfahren und Vorrichtung zur Annulierung eines Befehls. - Google Patents

Verfahren und Vorrichtung zur Annulierung eines Befehls.

Info

Publication number
DE3650413T2
DE3650413T2 DE19863650413 DE3650413T DE3650413T2 DE 3650413 T2 DE3650413 T2 DE 3650413T2 DE 19863650413 DE19863650413 DE 19863650413 DE 3650413 T DE3650413 T DE 3650413T DE 3650413 T2 DE3650413 T2 DE 3650413T2
Authority
DE
Germany
Prior art keywords
canceling
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE19863650413
Other languages
English (en)
Other versions
DE3650413D1 (de
Inventor
Ruby Bei-Loh Lee
Allen J Baum
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE3650413D1 publication Critical patent/DE3650413D1/de
Publication of DE3650413T2 publication Critical patent/DE3650413T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30069—Instruction skipping instructions, e.g. SKIP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
DE19863650413 1985-06-28 1986-06-12 Verfahren und Vorrichtung zur Annulierung eines Befehls. Expired - Lifetime DE3650413T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/750,625 US4755966A (en) 1985-06-28 1985-06-28 Bidirectional branch prediction and optimization

Publications (2)

Publication Number Publication Date
DE3650413D1 DE3650413D1 (de) 1995-11-09
DE3650413T2 true DE3650413T2 (de) 1996-03-07

Family

ID=25018608

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19863650413 Expired - Lifetime DE3650413T2 (de) 1985-06-28 1986-06-12 Verfahren und Vorrichtung zur Annulierung eines Befehls.
DE8686304500T Expired - Lifetime DE3680722D1 (de) 1985-06-28 1986-06-12 Bidirektionale vorhersage und optimierung von verzweigungen.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE8686304500T Expired - Lifetime DE3680722D1 (de) 1985-06-28 1986-06-12 Bidirektionale vorhersage und optimierung von verzweigungen.

Country Status (8)

Country Link
US (2) US4755966A (de)
EP (2) EP0207665B1 (de)
JP (1) JP2518616B2 (de)
KR (1) KR940005817B1 (de)
CN (1) CN1010618B (de)
AU (2) AU589977B2 (de)
CA (1) CA1270573A1 (de)
DE (2) DE3650413T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10101949C1 (de) * 2001-01-17 2002-08-08 Infineon Technologies Ag Datenverarbeitungsverfahren

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440704A (en) * 1986-08-26 1995-08-08 Mitsubishi Denki Kabushiki Kaisha Data processor having branch predicting function
US5341482A (en) * 1987-03-20 1994-08-23 Digital Equipment Corporation Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions
US5247627A (en) * 1987-06-05 1993-09-21 Mitsubishi Denki Kabushiki Kaisha Digital signal processor with conditional branch decision unit and storage of conditional branch decision results
US5134561A (en) * 1987-07-20 1992-07-28 International Business Machines Corporation Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries
JPS6488844A (en) * 1987-09-30 1989-04-03 Takeshi Sakamura Data processor
US5155818A (en) * 1988-09-28 1992-10-13 Data General Corporation Unconditional wide branch instruction acceleration
EP0365187A3 (de) * 1988-10-18 1992-04-29 Apollo Computer Inc. Vorrichtung zur selektiven Ausführung von einem Verzweigungsbefehl folgenden Befehlen
EP0378415A3 (de) * 1989-01-13 1991-09-25 International Business Machines Corporation Verteilungsmechanismus für mehrere Befehle
US5093908A (en) * 1989-04-17 1992-03-03 International Business Machines Corporation Method and apparatus for executing instructions in a single sequential instruction stream in a main processor and a coprocessor
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
EP0442116A3 (en) * 1990-02-13 1993-03-03 Hewlett-Packard Company Pipeline method and apparatus
US5303377A (en) * 1990-03-27 1994-04-12 North American Philips Corporation Method for compiling computer instructions for increasing instruction cache efficiency
EP0825529A3 (de) * 1990-05-04 1998-04-29 International Business Machines Corporation Gerät, um Befehle für einen Prozessor mit Parallelbefehlen vorzubereiten und Gerät mit einem Verfahren, um mitten in einem Verbundbefehl zu verzweigen
US5303356A (en) * 1990-05-04 1994-04-12 International Business Machines Corporation System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag
JPH0679273B2 (ja) * 1990-05-04 1994-10-05 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン データ処理装置
JP2845578B2 (ja) * 1990-06-19 1999-01-13 甲府日本電気 株式会社 命令制御方式
CA2045790A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Branch prediction in high-performance processor
US5283873A (en) * 1990-06-29 1994-02-01 Digital Equipment Corporation Next line prediction apparatus for a pipelined computed system
JP2834292B2 (ja) * 1990-08-15 1998-12-09 株式会社日立製作所 データ・プロセッサ
JP2508907B2 (ja) * 1990-09-18 1996-06-19 日本電気株式会社 遅延分岐命令の制御方式
JP2534392B2 (ja) * 1990-09-21 1996-09-11 三田工業株式会社 画像形成装置のための自己診断および自己修復システム
US5303355A (en) * 1991-03-27 1994-04-12 Motorola, Inc. Pipelined data processor which conditionally executes a predetermined looping instruction in hardware
US5450585A (en) * 1991-05-15 1995-09-12 International Business Machines Corporation Compiler with delayed conditional branching
JP2875909B2 (ja) * 1991-07-12 1999-03-31 三菱電機株式会社 並列演算処理装置
EP0855647A1 (de) * 1992-01-06 1998-07-29 Hitachi, Ltd. Rechner zur parallelen Durchführung von Datenabholung und Datenvorgriff
US5434986A (en) * 1992-01-09 1995-07-18 Unisys Corporation Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction
JPH06259262A (ja) * 1993-03-08 1994-09-16 Fujitsu Ltd 分岐確率を設定するコンパイラの処理方法および処理装置
US5426600A (en) * 1993-09-27 1995-06-20 Hitachi America, Ltd. Double precision division circuit and method for digital signal processor
JP3452655B2 (ja) * 1993-09-27 2003-09-29 株式会社日立製作所 ディジタル信号処理プロセッサおよびそれを用いて命令を実行する方法
US5815695A (en) * 1993-10-28 1998-09-29 Apple Computer, Inc. Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor
TW261676B (de) * 1993-11-02 1995-11-01 Motorola Inc
US5539888A (en) * 1993-12-23 1996-07-23 Unisys Corporation System and method for processing external conditional branch instructions
US5799180A (en) * 1995-10-31 1998-08-25 Texas Instruments Incorporated Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken
US5905881A (en) * 1995-11-30 1999-05-18 Unisys Corporation Delayed state writes for an instruction processor
US5774709A (en) * 1995-12-06 1998-06-30 Lsi Logic Corporation Enhanced branch delay slot handling with single exception program counter
US5799167A (en) * 1996-05-15 1998-08-25 Hewlett-Packard Company Instruction nullification system and method for a processor that executes instructions out of order
US5796997A (en) * 1996-05-15 1998-08-18 Hewlett-Packard Company Fast nullify system and method for transforming a nullify function into a select function
US5867699A (en) * 1996-07-25 1999-02-02 Unisys Corporation Instruction flow control for an instruction processor
US5974538A (en) * 1997-02-21 1999-10-26 Wilmot, Ii; Richard Byron Method and apparatus for annotating operands in a computer system with source instruction identifiers
US6401196B1 (en) * 1998-06-19 2002-06-04 Motorola, Inc. Data processor system having branch control and method thereof
US6192515B1 (en) * 1998-07-17 2001-02-20 Intel Corporation Method for software pipelining nested loops
US6862563B1 (en) 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
US20060168431A1 (en) * 1998-10-14 2006-07-27 Peter Warnes Method and apparatus for jump delay slot control in a pipelined processor
JP3470948B2 (ja) * 1999-01-28 2003-11-25 インターナショナル・ビジネス・マシーンズ・コーポレーション 動的コンパイル時期決定方法、バイトコード実行モード選択方法、及びコンピュータ
US6571385B1 (en) * 1999-03-22 2003-05-27 Intel Corporation Early exit transformations for software pipelining
WO2001016702A1 (en) 1999-09-01 2001-03-08 Intel Corporation Register set used in multithreaded parallel processor architecture
AU7099000A (en) 1999-09-01 2001-03-26 Intel Corporation Branch instruction for processor
US6662360B1 (en) * 1999-09-27 2003-12-09 International Business Machines Corporation Method and system for software control of hardware branch prediction mechanism in a data processor
US6446197B1 (en) * 1999-10-01 2002-09-03 Hitachi, Ltd. Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions
AU2001243463A1 (en) 2000-03-10 2001-09-24 Arc International Plc Memory interface and method of interfacing between functional entities
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
JP4141112B2 (ja) * 2001-04-12 2008-08-27 株式会社日立製作所 プロセッサおよびプロセッサシステム
US6785804B2 (en) * 2001-05-17 2004-08-31 Broadcom Corporation Use of tags to cancel a conditional branch delay slot instruction
US7437724B2 (en) 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
US7668622B2 (en) * 2004-03-30 2010-02-23 Honeywell International Inc. Efficient blending based on blending component availablity for a partial blend duration
JP2006011723A (ja) * 2004-06-24 2006-01-12 Matsushita Electric Ind Co Ltd 分岐制御方法、および情報処理装置
US8127113B1 (en) 2006-12-01 2012-02-28 Synopsys, Inc. Generating hardware accelerators and processor offloads
US8689200B1 (en) * 2011-01-12 2014-04-01 Google Inc. Method and system for optimizing an executable program by generating special operations for identical program entities
US8683455B1 (en) 2011-01-12 2014-03-25 Google Inc. Method and system for optimizing an executable program by selectively merging identical program entities
US20170277539A1 (en) * 2016-03-24 2017-09-28 Imagination Technologies Limited Exception handling in processor using branch delay slot instruction set architecture
US10970073B2 (en) 2018-10-02 2021-04-06 International Business Machines Corporation Branch optimization during loading

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE789583A (fr) * 1971-10-01 1973-02-01 Sanders Associates Inc Appareil de controle de programme pour machine de traitement del'information
GB1448866A (en) * 1973-04-13 1976-09-08 Int Computers Ltd Microprogrammed data processing systems
JPS52120735A (en) * 1976-04-05 1977-10-11 Agency Of Ind Science & Technol Microporogram control unit
US4378589A (en) * 1976-12-27 1983-03-29 International Business Machines Corporation Undirectional looped bus microcomputer architecture
US4210960A (en) * 1977-09-02 1980-07-01 Sperry Corporation Digital computer with overlapped operation utilizing conditional control to minimize time losses
US4325120A (en) * 1978-12-21 1982-04-13 Intel Corporation Data processing system
US4539635A (en) * 1980-02-11 1985-09-03 At&T Bell Laboratories Pipelined digital processor arranged for conditional operation
SE456051B (sv) * 1980-02-11 1988-08-29 Western Electric Co Digital processoranordning anordnad for pipeline-databehandlingsoperationer
US4390946A (en) * 1980-10-20 1983-06-28 Control Data Corporation Lookahead addressing in a pipeline computer control store with separate memory segments for single and multiple microcode instruction sequences
US4514804A (en) * 1981-11-25 1985-04-30 Nippon Electric Co., Ltd. Information handling apparatus having a high speed instruction-executing function
WO1985000453A1 (en) * 1983-07-11 1985-01-31 Prime Computer, Inc. Data processing system
US4742454A (en) * 1983-08-30 1988-05-03 Amdahl Corporation Apparatus for buffer control bypass
JPH0754461B2 (ja) * 1985-02-08 1995-06-07 株式会社日立製作所 情報処理装置
CA1254661A (en) * 1985-06-28 1989-05-23 Allen J. Baum Method and means for instruction combination for code compression
JPS6393038A (ja) * 1986-10-07 1988-04-23 Mitsubishi Electric Corp 計算機

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10101949C1 (de) * 2001-01-17 2002-08-08 Infineon Technologies Ag Datenverarbeitungsverfahren

Also Published As

Publication number Publication date
CN1010618B (zh) 1990-11-28
AU627828B2 (en) 1992-09-03
AU4867090A (en) 1990-05-10
DE3650413D1 (de) 1995-11-09
US4755966A (en) 1988-07-05
EP0423906B1 (de) 1995-10-04
KR870000643A (ko) 1987-02-19
CA1270573A1 (en) 1990-06-19
CA1272296C (de) 1990-07-31
EP0207665A1 (de) 1987-01-07
DE3680722D1 (de) 1991-09-12
CN86103708A (zh) 1986-12-24
EP0423906A2 (de) 1991-04-24
AU5917186A (en) 1987-01-08
EP0207665B1 (de) 1991-08-07
KR940005817B1 (ko) 1994-06-23
US5051896A (en) 1991-09-24
JPS623340A (ja) 1987-01-09
EP0423906A3 (en) 1991-08-28
AU589977B2 (en) 1989-10-26
JP2518616B2 (ja) 1996-07-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE