DE3640874A1 - Circuit arrangement for combining binary signals, divided into two part-signals having in each case half the bit rate at the transmitting end, in the correct bit sequence at the receiving end - Google Patents

Abstract

In a digital transmission system, a source-encoded colour television signal of 68.736 Mbit/s is divided into two part-signals of in each case 34.368 Mbit/s at the transmitting end and transmitted on adjacent channels. To compensate for delay differences between the two part-channels, they are read into a 3k-bit shift register, on the one hand, and into a 2k-bit aligner with k = 8 and 2k-bit buffer, on the other hand, before they are recombined in the multiplexer at the receiving end. An alignment word detection circuit operated at twice the input clock 2.T1 and connected to the multiplexer output allows the count of a following 2k-bit counter to increment by 1 bit each every one to two frame lengths until the alignment word arrives, stops the counter, reads out the aligner with a delay of at least 2k-bits and thus compensates for a mutual displacement of the part signals D1 and D2, respectively, by +/- 8 bits = 466 ns (Figure 3). <IMAGE>

Description

The invention relates to a circuit arrangement for on the receiving side, bit sequence correct assembly of a on the transmission side in two partial signals, each with half the bit rate split broadband and transmitted over adjacent channels binary signal.

field of use

Such a circuit arrangement is particularly on the Reception side of a transmission system necessary if one a color television signal digitized on the transmission side in two Split bit streams by half the bit rate.

In a digital transmission network, television and Audio broadcast programs, video telephony and telephony signals as well as data signals via a common multiplex bit stream be transmitted.

State of the art

For digital television signals there is a transmission bit rate not yet finalized.

The digital hierarchy levels for the future digital However, transmission systems are widely defined. To  Transmission of digital color television signals is initially suitable only the fourth hierarchical level at 139.264 Mbit / s. The next In principle, the lower level at 34.368 Mbit / s is also suitable, but currently the elaborate facilities such a transmission for source coding is not appear economical. There are also several Suggestions for coding moving picture signals with approx. 70 Mbit, for which the effort for source coding is essential is lower.

It is also known that two inputs of a digital signal multiplexers DSMX 34/140 occupied and the bits of this digital signals alternately transmitted over the two occupied channels will. A corresponding proposal was made in the CCITT document COM XVIII No. 200-E made in July 1983.

The basic structure of such a digital system can be seen in FIG. 1. The transmission side is shown above, starting with the transmission-side demultiplexer which effects the division of the binary input signal D and the input clock T with the two data outputs D 1 and D 2 and the two clock outputs T 1 and T 2 . Downstream are code converters from NRZ to HDB3 code. With their partial signals, the two code converters occupy two inputs of the 140 Mbit / s multiplexer on the transmission side and from there reach the actual transmitter LES and the transmission link.

The lower part of Fig. 1 shows the receiving part, starting with the receiver LEE and the downstream Mbit / s demultiplexer, in which the partial signals D 1 and D 2 are recovered and switched to the code converter from the HDB3 to the NRZ code . The two sub signals D 1 and D 2 engage with the supplied clocks impaired T 1 and T 2 on the receiving side multiplexer, the recombined total signal D is at its output connected to the associated clock T available.

Criticism of the state of the art

The from the block diagram described above in the The basic principle of transmission methods can be found at However, the implementation in terms of circuitry is somewhat difficult keiten. In particular, the problem is different possibly changing transit times of the signals in the multiplexing device at the receiving end is not resolved.

task

It is therefore the object of the invention to provide a circuit order for the reception-side, bit sequence correct merging tion of a transmission side into two partial signals, each with the half bit rate split and over adjacent channels transmitted broadband binary signal.

solution

This object is achieved according to the invention in that the two partial signals are read into a 3k-bit shift register and into a 2k-bit aligner with an upstream 2k-bit buffer before being reunited in the multiplexer at the receiving end. A synchronous word recognition circuit operated with the double input clock and connected to the multiplexer output causes the counter of a downstream 2k bit counter to grow by one bit every one to two frame lengths until the synchronous word arrives, the counter stops, the aligner with one reads the entire delay of the highest 4 k-bit and thus compensates for a shift in the sub-signals D 1 or D 2 of kbit among one another.

Advantageously, the two partial signals each have a bit rate of 34.368 Mbit / s and are created by splitting a source-coded color television signal of 68.736 Mbit / s. In this case, k with 8 bits is selected.

Embodiment

The following is the circuit arrangement according to the invention explained in more detail using block diagrams. It shows

Fig. 1 shows the block diagram already described in the prior art basic additional,

Fig. 2 shows the configuration of the transmission-side demultiplexer,

Fig. 3 shows the inventive design of the receiving-side multiplexer.

After the basic block diagram of FIG. 1 has already been described in the prior art, for the sake of completeness the circuit arrangement of the transmitter-side demultiplexer according to FIG. 2 is discussed below.

According to FIG. 2, the 68.736 Mbit / s signals D present at ECL level are converted into TTL level, since the HDB3 interfaces are constructed with TTL circuits. After halving the clock T and converting the ECL level into the TTL level, the D flip-flop FF 1 is driven with the positive clock edge of T / 2. The D flip-flop FF 2 is then driven with the positive clock edge of the inverted clock T / 2. The signal D is already at both inputs of the two D flip-flops. The data bits are thus divided up alternately between the two partial signals D 1 and D 2 . The two partial signals D 1 and D 2 and the associated clock signals T 1 and T 2 are supplied to two HDB3 interfaces. The output signals of the HDB3 interfaces are at two inputs of the multiplexer of the fourth hierarchy level according to FIG. 1 above.

On the reception side, the two 34.368 Mbit / s signals must be combined in the correct order. The circuit arrangement according to the invention according to FIG. 3 serves this purpose . If one or the other signal D 1 or D 2 is delayed over 15 ns on the transmission link, the transit time of the signals must be compensated. The signal D 1 is constantly delayed by T 1 in a 24-bit shift register SR by 24 bits. 24 bits are necessary because the 16 bit aligner has an upstream 16 bit buffer. The signal D 2 is written with T 2 in a 16-bit buffer. The reading out of the subsequent 16-bit aligner must now be controlled in order to ensure that the multiplexer (Mux) is assembled in the correct phase.

The synchronous word recognition circuit and counter 1 are used for this. . . 16. As long as the sync word of the 68.736 Mbit / s digital signal has not been recognized, the counter runs and increments its counter reading by 1 bit every 1 to 2 frame lengths. The readout pulse, which is derived from the clock T 1 , is thus also delayed by 1 bit in each case. As soon as the sync word of the 68.736 Mbit / s digital signal is recognized, the counter stops and the aligner is read out with the set delay. A shift in the two data signals D 1 and D 2 by +/- 8 bits = 466 ns can thus be compensated for. Clock T 1 is brought to the output frequency in a doubler circuit. At the output of the circuit, the signal D and clock T are brought into the required form by TTL-ECL converters.

Achievable advantages

With the circuit arrangement described above can a digital signal with 68.736 Mbit / s with little effort, the Z. B. be a digital color television signal of high quality includes, via Muldem (multiplexer / demultiplexer) systems  the fourth hierarchy level with the greatest possible utilization of the Transmission capacity can be transferred. The functional parts require relatively little circuitry. The 34,368 Mbit / s interfaces and the Muldem are standardized Assemblies. Simple clock synchronization is possible because the exact double bit rate was chosen. With the help of Aligners according to the invention can use phase-shifted signals correctly assembled up to a runtime of +/- 8 bits will. If the term is greater than this amount, it should the aligner can be expanded. Because a transfer of the two 34.368 Mbit / s signals on two completely different transmissions distance would result in a very large transit time difference, is the aligner to the use of neighboring transmissions channels limited. So the effort is reasonable Limits kept. But it is acceptable, with a maximum Runtime of +/- 8 bits to be expected, which in the supply lines and in Caching can occur.

Claims (3)

1. Circuit arrangement for the reception-side, bit-sequence-correct assembly of a broadband binary signals, in particular a digitized color television signal, divided into two partial signals each with half the bit rate and transmitted via adjacent channels, characterized in that the two partial signals prior to their reunification in the receiving-side multiplexer (Mux) once in a 3k bit shift register (24 bit SR) and on the other hand in a 2k bit aligner (16 bit aligner) with an upstream 2k bit buffer that one with the doubled input clock 2 × T 1 operated, connected to the multiplexer output synchronous word identification circuit, the counter reading of a downstream 2k-bit counter increases by one bit every one to two frame lengths until the synchronous word arrives, the counter stops, the aligner with a delay of at least 2k-bit reads and thus a shift of the part signals D 1 or D 2 is equal to each other from 8 bits = 466 ns ( Fig. 3). 2. Circuit arrangement according to claim 1, characterized in that the two partial signals each have a bit rate of 34.368 Mbit / s and arise by splitting a source-coded color television signal with 68.736 Mbit / s ( Fig. 1). 3. Circuit arrangement according to claims 1 and 2, characterized in that k = 8 is selected ( Fig. 3).