DE3622205A1 - Integrated digital circuit for logarithmic signal processing - Google Patents

Abstract

An integrated circuit for logarithmic signal processing has a logarithmic converter and a logarithmic computer, each with a comparator array logic (CAL circuit). The CAL circuit has a large number of comparators, which are connected to each other, and are arranged in an array. A digital value is stored in each of the comparators. The CAL circuit stores all digital values in monotonically ascending or descending sequence. Each of the comparators receives the input data signal and compares it with the digital values which are stored in the comparator. A comparison signal which depends on the comparison is generated. The comparison signal of every comparator is received by an end cell, which also receives the comparison signal of the immediately adjacent comparator. The end cell generates an output signal. An end cell is assigned to each comparator. The large number of output signals from the end cells gives the position of the comparator of which the stored digital value is next to the value of the input data signal. <IMAGE>

Description

An integrated circuit for logarithmic signal processing has a logarithmic converter and a logarithmic calculator, each of which has a lo assigned comparison array circuit (CAL circuit) is not. There are a large number of comparators in the CAL circuit arranged in an array. Each of the comparators saves a digital value. The CAL circuit stores them all digital values in monotonously increasing or falling fol ge. Each of the comparators receives the input data signal nal and compares the same with those saved in the comparator digital values.

Systems for converting integer data to logarithmi cal data, for operating on this logarithmic data and to convert back to whole numbers are generally knows, see e.g. B. IEEE Transactions On Computers, Vol. C-32, No. 6, June 1983, pp. 531-534, in which a loga rithmic arithmetic processing unit is disclosed. Attention is also drawn to Electron. Lett. 7: 56-58 (1971), SS. 215-217, the article entitled "Digital Filter ing Using Logarithmic Arithmetic "; IEEE Transactions On Computers, Vol. 24, No. 8, August 1975, pp. 761-765 Article titled "Multiplication Using Logarithms Implemented With Read-Only Memory "by Brubaker et al .; IEEE Transactions On Acoustics, Speech And Signal Proces sing, vol. ASSP-31, No. 1, February 1983, pp. 232-234; IEEE Transactions On Computers, December 1975, pp. 1238- 1242; IEEE Transactions On Computers, Vol. C-32, No. 6, June 1983, pp. 526-530; and also "The Implementation Of Logarithmic Arithmetic "by Bechtolsheim et al., Stan Ford University, March 7, 1981; and IEEE Transactions On Acoustics, Speech And Signal Processing, Vol. ASSP-28, No. 6, December 1980, the article entitled "Error  Analysis of Recursive Digital Filters Implemented With Logarithmic Number Systems "by Kurokawa et al.

With all known systems are either by soft goods or hardware implementation integers in loga rithmic numbers have been converted on which then operated and which were then converted back into whole numbers. In the Software implementation is the difficulty mainly in that a number of machines cycles is necessary to complete the task. In one Chen use cases, for example in digital Signal processing or Fourier analysis is Geschwin a necessary element. For this reason, the Conversion using software is impractical.

When implementing a logarithmic hardware Computing unit or a logarithmic processor be is the biggest obstacle in the cost of hardware. Because the lookup table for converting and operating on the logarithms generally have a large memory demands, the costs are disadvantageous.

Digital memory circuits such as ROMs (read-only memories) and RAMs (random access memories) are generally known knows. These memory circuits receive a digital one Input signal, which is the space of the memory cell specifies to which data should have access. It is common that to designate the digital input signal as an address signal. Depending on the address signal, the Memory content at the address in either the Memory circuit entered or retrieved from it. Sol che memory circuits are deterministic, since there is a unique memory for each address signal space from which the associated data either relate to the the memory cell is retrieved or entered into it.  

Digital comparators are also well known. A digital comparator receives a digital input signal and compares it with a stored digital len signal. Then depending on this comparison generates an output signal.

Finally, shock (flash) analog Digital converter (A / D converter) known. A shock A / D converter is a high speed A / D converter, in which analog data is entered into a linear array will. A variety of analog comparators in the array compares the analog signal and generates a variety of Digital signals. Every analog comparator is a reference voltage comparator or an A / D converter.

With the present invention, a digital scarf tion revealed. This digital circuit gets an on output data signal, which represents an input value. To a large number of comparators belongs to the circuit save one digital value each. The one in the lot number of digital values stored by comparators stored in monotonically increasing or decreasing order. Each comparator receives the input data signal and compares the input value it represents with that in Comparator stored digital value. Then he the comparator testifies as a function of this comparison a comparison signal. There will be a variety of comparative signals generated and fed to a device that responds to it producing an output signal, which represents the location of the comparator whose stored digital value to the value of the input value adjacent.

The invention also discloses a digital computing device. This device has a device for the simultaneous recording of four operands ( a, b, c, d ). A first multiplier / divider unit calculates a × b or a ÷ b and supplies an output signal U. A second multiplier / divider unit calculates c × d or c ÷ d and delivers an output signal V. An adding / subtracting unit receives U and V and calculates U + V and U - V. A control unit controls the operation of the first and second multiplying / dividing units to select either multiplication or division.

A digital device for converting a digital binary integer with a large number of bits in one logarithmic representation and reversed is also disclosed. To convert or convert the digital, bi shows its integer in a logarithmic representation the device has a device which the bit posi leading bit non-zero integer detected. A device also belongs to the device by means of which the whole numbers are shifted or be offset that the leading bit is not zero is the leftmost bit. A tables facility receives the digit and integer returns a number which is the mantissa part of the logarith mus represents the staggered number. Heard further to the device a coding device that a com input value and the number of the shift receives position shifted binary position and the exponent part of the logarithm of the integer testifies. Thus, the mantissa and exponent parts form the logarithmic representation of the integer.

The digital device for converting the logarithmic Representation of an integer in a binary integer has a table facility that the mantissa part of the logarithmic representation and receives a first Number delivers. A decoder receives the expo part of the logarithmic representation and a com masetzausgabewert and delivers a shift signal. A Slider receives the job transfer or Shift signal and the first number and shifts  the first number using the shift signal to move the gan generate ze number.

In addition, a digital processor with an address senbus and a data bus for communication with it disclosed. A data register belongs to the processor Direction for communication with the data bus and for emp capture and store data from the same. Heard further to the processor a data conversion device that for communication to the data register device is closable to data in a form, for example integer data from the data register device in Da another form, e.g. B. move log data convert so the data in the data register facility can be saved. To the data conversion direction also includes a device for relocating of data in one form and for storing that data in the data register facility. Furthermore, the process sor a computing device that also for communication cation can be connected to the data register device. The computing device receives data in another Form of the data register device, leads to this Through calculations and stores calculation results in the Data register facility.

A control device also belongs to the processor for communication with the address bus and the Data bus. The control device has a fast one Buffer memory or cache memory for storing Pro gram commands, a device for decoding Pro gram commands and a device for generating internal Program commands. The control device also belongs an internal bus device that the control device for communication with the data register device, Data conversion device and the computing device ver binds to communicate internal program commands adorn. The operation of the control device controls the Operation of the processor via the internal program commands.  

The invention is advantageous in the following Details with the aid of schematically represented execution examples explained in more detail. In the drawings:

Fig. 1 is a block diagram of a digital processor having a control device, a logarithmic order conversion means, means a logarithmic arithmetic and a data storage device;

FIG. 1a is a schematic block diagram of the Befehlsde coding portion of the processor of FIG. 1;

FIG. 1b shows a schematic block diagram of the Adressenregi sterspeicherteils of the processor of FIG. 1;

FIG. 1c and 1d are schematic block diagrams of the Indexein integral part of the processor of FIG. 1;

Fig. 2 is a block diagram of the logarithmic conversion device;

. Fig. 2a and 2b show the two modes of operation of loga rithmischen conversion device according to Fig 2, the conversion that is integer data in logarithmic mix data and the conversion logarithmic da ta into integer data;

FIG. 3 shows a block diagram of the data register memory according to FIG. 1;

FIG. 4 is a block diagram of the logarithmic computing device according to FIG. 1;

FIG. 4a shows the graphs of x and log ₂ (1 ± 2 ^{- x);}

Fig. 4b is a schematic of part of the logarithmic Re computing device according to Fig. 4;

Fig. 5 is a schematic of a logic comparator array circuit (CAL circuit);

Fig. 6 is a schematic of a further embodiment of a circuit CAL;

Fig. 6a is a circuit diagram of a bit comparator which forms part of the CAL circuit shown in Fig. 6;

Programmed 6b are circuit diagrams of the bit comparator according to Fig. 6a.

Comparators 6c, 6d and 6e show further embodiments of bits.

FIG. 7 shows a logic circuit diagram of an end cell used in the CAL circuit according to FIG. 6;

8 shows a further bit comparator usable in the circuit CAL, wherein the stored value is variable.

Fig. 8a shows a further embodiment of a Bitver gleichers, wherein the stored value is Variegated bar;

Fig. 9 logical equations and truth tables for the CAL circuit.

Fig. 1 is a block diagram of a processor 10 for digital signals, which has an address bus 12 and a data bus 14 , each sixteen bits wide and connected to connect with other digital devices such as memories and other microprocessors can.

The digital processor 10 includes a controller 16, a logarithmic converter 18 , a data register memory 20 and a logarithmic computer 22 . The controller 16 is connected via an internal command bus 24 to the logarithmic converter 18 , the data register memory 20 and the local computer 22 and communicates with them. The processor 10 also has a control unit 36 which receives or generates external control signals for the data bus 14 and addresses bus 12 . Such a control unit 36 is known.

The controller 16 also includes a cache memory 26 for programs with a program counter 28 , a command decoder (I decoder) 30 , an address register memory 32 and an index unit 34 .

The data bus is connected to sixteen status registers 13 , the content of all units, e.g. B. Converter 22 and computer 18 , the processor 10 is updated and to which the external processor 10 can access. These status registers 13 also perform jump checks depending on the status registers 13 . The data bus 14 is also connected to the program cache 26 and the data register 20 of the processor 10 for communication therewith. The address bus 12 is connected for communication with the address register memory 32 , the index unit 34 and the program counter 28 . The internal command bus 24 connects the decoder 30 for program commands to the address register memory 32 , the index unit 34 , the program counter 28 , the logarithmic converter 18 , the data register memory 20 and the logarithmic computer 22 .

As is usual with all von Neumann machines, programs and data are stored in memories (not shown here) outside the processor 10 , to which the address bus 12 and the data bus 14 have access. When a program instruction is retrieved, it is provided on the data bus 14 and loaded into the program cache 26 . When data is retrieved, it is provided on the data bus 14 and given to the data register memory 20 . The address for the memory space, which contains either the program or the data, is made available on the address bus 12 .

The program cache memory 26 and the program counter 28 are conventional hardware elements that are generally known. The cache memory 26 is a common high-speed buffer memory with thirty-two registers, thirty-two bits each. Because data bus 14 is only sixteen bits wide, two memory loads from data bus 14 are required to fill each register of program cache 26 .

The instruction decoder 30 decodes each internal instruction of the processor 10 and formulates the instructions which control the program counter 28 , the address register memory 32 , the index unit 34 , the logarithmic converter 18 , the data register memory 20 and the logarithmic computer 22 .

The address register memory 32 is a RAM with four connections (ports) and consists of sixteen registers of sixteen bits each. The index unit 34 performs address indexing based on four address inputs from the address register memory 32 .

When the digital signal processor 10 is operating, integer data is provided from the data bus 14 to the data register memory 20 , which is a multi-port memory with eight 16-bit registers. The logarithmic converter 18 communicates with the data register memory 20 and receives the integer data therefrom. The logarithmic converter 18 converts the integer number into a logarithmic number and stores it in the data register memory 20 .

The logarithmic computer 22 also communicates with the data register memory 20 . It receives the logarithmic numbers stored in the data register memory 20 and operates on them. The operations he performs include addition, subtraction, multiplication, division, multiplication with accumulation, special FFT and complex arithmetic. After the operation, the logarithmic calculator 22 returns the resulting logarithmic number and stores it in the data register memory 20 .

The logarithmic converter 18 then receives the logarithmic number from the data register memory 20 and converts it into integer data, which are then stored in the data register memory 20 . The integer number is then passed to the data bus 14 for output to other digital devices located outside of the processor 10 .

Processor 10 has been described herein as being useful for converting and operating on data in conjunction with logarithms; but it is obvious that it can also be used to convert and operate on data in other fields, such as floating point. In this case, converter 22 converts integer data into floating point data and vice versa. Similarly, the calculator 18 would then be a floating point calculator.

In addition, processor 10 has been described here in connection with a program cache memory 26 , which receives program commands externally from processor 10 via the data bus 14 lying down. It is obvious that the program cache 26 can also be a ROM, so that all program instructions are contained within the processor 10 itself.

 Instruction decoder

Instruction decoder 30 is shown in more detail in Fig. 1a. Instruction decoder 30 receives each 32-bit instruction from program cache 26 and stores it in an instruction register 38 .

Fifteen selected bits of the thirty-two bits are decoded from the instruction register 38 as instructions for register jumps which are fed to the index unit 34 and the program counter 28 . The instruction can be decoded as an immediate jump and is used by the index unit 34 in this case. If the instruction is a jump destination, then it is used by the program counter 28 . Another combination of selected sixteen bits of the thirty-two bits is inputted to the address register file 32, in order to address the or each special register within this memory address register 32nd Another combination of selected four bits of the thirty-two bits is entered into index unit 34 as commands for address functions. Finally, a selected combination of six bits of the thirty-two bits is passed to the status registers 13 as a command for jump conditions.

A selected combination of seven bits of the thirty-two bits goes to an instruction ROM 40 which has 128 ROM locations per twenty bits. The selected seven bit combination from instruction register 38 is used to address a particular ROM location within instruction ROM 40 . The combination of two of 2 ⁷ is 128. Thus, the seven bits can be used to address any of the 128 locations within the command ROM 40 . The output of instruction ROM 40 is twenty bits wide, eighteen of which are used to address the particular register (s) in data register memory 20 . The other two bits from the command ROM 40 are used to control the logarithmic mechanism 18 and the logarithmic converter 22 , one bit determining the use of one or the other element and the other bit determining the operation of the mechanism 18 , namely multiplication or division.

Another selected combination of nine bits, four of which are the same as the four bits for the address function, is provided to an instruction PLA (programmable logic array) 42 . The command PLA 42 also receives a control bit from the control unit 36 . If the control bit is high or "1", then the nine bits provided to command PLA 42 determine who should have access to command bus 24 . If the control bit of the control unit 36 is low or "0", the command PLA 42 is blocked so that no one has access to the command bus 24 . The command PLA is a 10 x 10 x 18 programmable logic array, which means that there are ten inputs, ten outputs and eighteen product terms.

The ten output bits determine the format of the micro programming. One of the ten bits is for the operation of logarithmic mechanism 18 and logarithmic converter 22 . If this bit is on, mechanism 18 or converter 22 is prepared. Two of the ten bits are address jumps and are fed to the program counter 28 and the control unit 36 . Five of the ten bits control the data bus 14 and are used in part for reading in and reading out from the data register memory 20 into the data bus 14 . The remaining two bits are memory control bits that also go to control unit 36 . The programming of the command PLA 42 to select the respective outputs from the special inputs is known to the person skilled in the art.

Finally, four bits, which are the address function bits, are also applied to a logic decoder 44 which determines that in the event that these four address function bits are in the "0000" bit pattern, the 1-bit output will operate the controller 16 stops.

All of the above-mentioned output signals of the command decoder 30 are delivered in parallel and continuously delivered to their destination.

 Address register memory and index unit

Address register memory 32 and index unit 34 are shown in more detail in Figures 1b, 1c and 1d. As already mentioned, the address register memory 32 is a RAM memory with four connections (ports), which has sixteen registers of sixteen bits each. The four connections are labeled A ₀ , A ₁ , A ₂ and A ₃ in FIG. 1c. Each port is a read port and is sixteen bits wide and contains the contents of one of the registers of the address register memory 32 . As is apparent from Fig. 1, 1b and 1c, the address register file 32 has also a write terminal labeled W _0. The write terminal W ₀ is also sixteen bits wide and is used by the address bus 12 or by the index unit 34 to write to the address register memory 32 . However, the write connection W ₀ is shared with the read connection A ₀ or is multiplexed with it. Therefore, the address register memory 32 has only four ports.

Since sixteen registers are contained in the address register memory 32 , four bits would be needed to address a particular register. Since there are also four connections, sixteen address register addresses are required to select the contents of four registers and to bring them to the four connections. Furthermore, one of the sixteen registers in the address register memory 32 is a read-only register which contains only zeros.

The addresses for the address register memory 32 are fed to an address decoder 31 , which has sixteen identical decoding sections, each of which is connected to a register in the register array 33 by means of a number of word lines. Six word lines are available for the fifteen read / write registers: four to select the read ports, one to select the write port and hold to control the latch that holds the data. For the read-only register, only four word lines establish the connection between the address decoder 31 and the register array 33 . These four lines are used to select the read connection or read connections.

The four word lines for selecting the one or more read connections are connected to a read connection crosspoint matrix 35 which connects the latch 37 holding the data to one or more of the read connections A ₀ , A ₁ , A ₂ or A ₃ .

The only word line for selecting the write connection is connected to a write switch 39 , which connects the latch 37 to the write connection W ₀ .

The output of the register array 33 is applied to an I / O buffer 41 .

The four bits that determine the address function from instruction decoder 30 are provided to an address function decoder 46 which decodes the four bits of the address function and sets the corresponding bit flags. Some of the instructions that the address function decoder 46 can decode are as follows: The address function decoder 46 for decoding the above bit pattern is known to those skilled in the art.

The various bits of the conditions that represent the particular address function code are provided to an address condition code tester 48 , which is shown in detail in FIG. 1c. For example, if the bit pattern "1011" is decoded, the bit line for IFNE is set high.

The index unit 34 also includes a subtractor 50 , which generates the term A ₀ - A ₂ . The output of the subtractor 50 is fed to the code tester 48 for the address condition. The index unit 34 also includes a multiplexer 52 which receives the address of A ₀ and A ₂ . Depending on the address function decoder 46 , the multiplexer 52 is thus activated. The multiplexer 52 applies the output signal to an adder 54 , which also receives the address of A ₁ . Depending on the state of the multiplexer 52 , the output of the adder 54 is therefore either A ₁ + A ₀ or A ₁ + A ₂ . Depending on the test conditions of the address function, the output of the index unit 34 is then supplied to the address bus 12 and from there via the write connection W ₀ to the address register memory 32 .

A special function of the address register memory 32 with the index unit 34 is the ability to automatically increment or decrement by a discrete amount, carry out a comparison with a test address and reload a reload address into the address register memory 32 , all in one single clock cycle.

The address from port A ₀ can contain, for example, the address of the storage space on the current operation. The address at connection A ₁ can contain the increment value. The address at connection A ₂ can contain the test address. The address at port A ₃ can contain the reload address. The advantage of auto-incrementing or decrementing by a certain amount, checking and reloading the address in a single command is evident from vector operations. If e.g. B. an array is multiplied by a vector of the following form: then the addressing would be done in the following way:

Addresses

If the address from the connection

A ₀

the address

X _n

reached and the condition to be checked is that

A ₀

≠≠

A _2nd

(Command IFNE), d. that is, if this condition of

A ₀

≠≠

A _2nd

is wrong or

A ₀

=

A _2nd

, the address becomes visible from the connection

A _3rd

the connection

A ₀

assigned. That means in other words, if the address from the connection

A ₀

the Test address from the connection

A _2nd

reached, the address will be from Connection

A _3rd

in the terminal

A ₀

loaded. Because the connection

W ₀

the connection with

A ₀

shared, the address is from Connection

A ₀

in the address register memory

32

written back. So the vector multiplication operation after reaching

X _n

at

X ₀

continue, taking only one only clock cycle is required.

This is erläuert with reference to FIG. 1c and 1d. If the condition to be checked is "IFNE", the bit line IFNE is raised or set to "1". In the n + 1 operation when A ₀ = A ₂ , the difference from subtractor 50 is zero. Then the input of the NOR gate 47 consists only of zeros and the output becomes "1". After inversion, this leads to "0" at NAND gate 49 , which results in an output of "1". The output for "true" is "0" behind the inverters.

The output of the NOR gate 51 is "1", which gates a tristate 53 . A ₃ is thus loaded onto the address bus 12 , which in turn forwards it to W ₀ .

It should be pointed out here that in the case of an address register memory 32 with a special register which is only "000 ..." contains, the register memory 32 can be programmed together with the index unit 34 to increment or decrement by "0 ... 0", causing the same current address to be used repeatedly.

 Logarithmic converter

The logarithmic converter 18 is shown in detail in FIG. 2. The converter 18 has sixteen input lines and sixteen output lines. The sixteen input lines are used to apply data to the converter 18 in either logarithmic or integer form. The output lines are used to receive the converted integer or logarithmic data from the converter 18 . The integer data supplied to processor 10 is in two's complement form. In the two's complement form, if the leftmost bit is "0", then the number is positive. If the leftmost bit is "1", the number is negative.

The logarithmic data in processor 10 have the following format:
S b e e e e e m m m m m m m m m
where S is the sign of the logarithmic data ("0" for positive and "1" for negative) with an exponent oe " , which again has a sign (bias sign) " b " , and with a mantissa " m " . If the If the data supplied to the converter 18 are in logarithmic form, the left-most bit is received by a sign operator 60. The remaining fifteen input lines for data in logarithmic form go to a first multiplexer 62 , which has a further fifteen lines from an exception identifier 64 Multiplexer control is set by L. When L is high, the fifteen lines of L's closest adjacent signal are chosen, so when logarithmic data is supplied to converter 18 , L is set low.

The six input lines, which represent the exponent part of a logarithmic number (sign b and five bits of the exponent value e ), are then applied to a decoder 66 . The remaining nine lines of the fifteen input lines, which form the Matisse part of the logarithmic number, go to a delogarithmic or antilog ROM 68 . A 6-bit comma set output value is supplied by a PSO register, which is contained in the status registers 13 . The PSO value is applied to decoder 66 , the output of which is connected to exception identifier 64 and a second multiplexer 70 . The fifteen output bits of the Antilog ROM 68 are supplied to a third multiplexer 72 .

Since L is low, the outputs of the second and third multiplexers 70 and 72 are fed to a barrel shifter 76 which receives and processes the fifteen bits of the integer output from the antilog ROM 68 via the third multiplexer 72 it shifts by the number of digits that decoder 66 supplies via second multiplexer 70 .

The fifteen output bits are passed to exception identifier 64 , which determines whether an underflow or overflow condition has occurred. In this case, the exception identifier 64 sets the status bit and generates the smallest or largest integer that is supplied to the sign operator 60 .

The sign operator 60 performs a two's complement operation and the number is passed to a fourth multiplexer 84 . If L is low, the number from the sign operator 60 becomes the output of the converter 18 .

If the input number is in integer form, L is set high and all sixteen bits are provided to the sign operator 60 , which generates the sign S of the logarithmic representation and also does a two's complement to convert the integer to a non-complementary representation .

Fifteen data lines go from the sign generator 60 to an MS finder 74 and also to the third multiplexer 72 . The output from the MSucher 74 goes to the second multiplexer 70 . The outputs of the second and third multiplexers 70 and 72 go to the drum shifter 72 . The output of the MS seeker 74 is also available to an encoder 78 . Encoder 78 also receives six input lines that form the comma set input from a PSI register contained in status registers 13 .

Since L is high, the output of the sign operator 60 and that of the MS seeker 74 are directed to the drum shifter 76 , the output of which is applied to a logarithmic CAL circuit 80 . The output of the CAL circuit 80 is the mantissa part of the logarithm of the integer input data. The new output lines are then concatenated to the six output lines of encoder 78 to form fifteen output lines which are fed to a zero detector 82 . The fifteen output lines from the sign operator 60 are also fed to the zero detector 82 . The fifteen output lines of the zero detector 82 are fed to a fourth multiplexer 84 . The sign bit of the sign operator 60 is connected to the fifteen output bits from the zero detector 82 . The output of the fourth multiplexer 84 represents the sixteen output bits of the logarithmic converter 18 .

The sign operator 60 , exception identifier 64 , MSucher 74 and drum shifter 76 are conventional hardware elements used in floating point operations. Decoder 76 and encoder 78 are modifications of known circuits to accommodate PSO and PSI values. In one embodiment, encoder 78 may be a conventional, well-known encoder, the output of which is added to the PSI value to produce the exponent value. An embodiment of decoder 66 may be a subtractor that subtracts the PSO value from the exponent value, and the result is provided to a known decoder. The Antilog-ROM 68 is only a read-only memory which has 512 addressable locations with fifteen bits in each location. The logarithmic CAL circuit 80 is a comparator array logic, which will be explained in more detail.

The mode of operation of the converter 18 is explained with reference to FIGS . 2a and 2b, which represent the conversion of integers into logarithms or of logarithms into integers.

FIG. 2a shows that part of the logarithmic converter 18 which fulfills the function of converting integer data into logarithmic data. The absolute value determiner 60 , which is part of the sign operator 60 , complements the integer input data in order to obtain the non-complementary representation of the integer data and supplies the left-most sign bit as an S bit to the output. The remaining fifteen bits, representing the absolute value of the integer entered, are passed to MSucher 74 .

The fifteen bits of the input data are also fed to a zero detector 81 . If the integer input data is zero, then a special number ("0... 0") is generated, which the processor 10 interprets as a logarithm of zero. A special number must be generated because mathematically log zero is undefined.

MSucher 74 searches for the leading non-zero bit position. Its output is a number that indicates the number of bits that the drum shifter 76 must shift the input data to the left in order for the leading non-zero bit to go to the left most position. Once the number of bits is shifted, the fifteen output lines of drum shifter 76 are applied to CAL circuit 80 . The CAL circuit 80 is a look-up table that has 512 15-bit memory cells that determine what the mantissa part of the logarithmic number is based on the input GH data. The output of CAL circuit 80 thus consists of nine bits of mantissa.

The CAL circuit 80 stores the values of the logarithmic equation: y = log ₂ x , where x is the input and y is the output, and where 1 x ≦ ωτ 2. The output y is 0 y ≦ ωτ 1, i.e. around the mantissa the input number x .

Because the drum shifter 76 is the integer of 1 _{- - - - - - - - - - - - - -}
shifts, with the comma immediately to the right of "1", the CAL circuit accepts 80 x , namely the number entered, as x = 1, _{- - -} and generates the corresponding mantissa. The exponent, ie the extent of the shift, is determined by the encoder 78 .

The output of the MS seeker 74 is also passed to the encoder 78 . Encoder 78 also receives the 6-bit comma input value or PSI value. Starting from the output of the MS seeker 74 and the PSI value, the encoder 78 generates a 6-bit number which represents the exponent part of the logarithm of the input number.

The 6-bit output from encoder 78 is then concatenated to the 9-bit output of CAL circuit 80 to form the 15-bit logarithmic number. The fifteen log number lines are fed to the zero detector 82 . When the zero detector 81 determines that the input data is zero, the zero detector 82 generates the aforementioned special number. Otherwise, the 15-bit logarithmic number supplied to the zero detector 82 is provided as an output. The fifteen lines are combined by the zero detector 82 with the one sign bit of the absolute value 60 to form the sixteen of the output bit of the logarithmic number.

In Fig. 2b, the conversion logarithmic data is shown in integer data. The sixteen input bits represent the logarithmic data. The left-most bit of the sixteen input lines is supplied to the sign operator 60 . The remaining fifteen input bits are divided according to the exponent part (six bits) and the mantissa part (nine bits).

The six bits forming the exponent part reach decoder 66 . Decoder 66 also accepts six lines which represent the six bits for the PSO value. The output of decoder 66 is applied to drum shifter 76 and commands it by how many places and in which direction it has to make a shift. The nine bits of the mantissa part of the entered logarithmic data reach the Antilog ROM 68 .

The Antilog-ROM 68 is, as already said, a conventional 512x15 bit ROM lookup table. The Antilog-ROM 68 stores the values of the logarithmic equation x = 2 ^y , where y represents the input, 0 y ≦ ωτ 1, and x the output, with 1 x ≦ ωτ 2.

The output of the Antilog-ROM 68 is an integer with fifteen bits. This data is fed to drum shifter 76 , which shifts the integer data by the number of bits from decoder 66 . The output of the drum shifter 76 is then passed to the exception identifier 64 to determine whether there was an overflow or underflow condition. If decoder 66 commands drum shifter 76 to shift the comma too many places to the right or left, an underflow or overflow condition at the output of drum shifter 76 could result. The exception identifier 64 generates the smallest or largest integer if there is an underflow or overflow and generates a signal on the status lines, the underflow or overflow condition.

If the exception identifier 64 determines that the data generated by the drum shifter 76 is neither overflow nor underflow, then the integer data is passed by the drum shifter 76 to the sign operator 60 , from which the sign bit, namely the leftmost bit, is concatenated; the sixteen bits of integer data are then output from converter 18 .

The comma set output (PSO) and the comma set input (PSI) have the task of providing flexibility and a dynamic range for the number shown at the input or output of the converter 18 . PSO and PSI enable the user to fit the wide dynamic part of a logarithmic number into a usable range of a linear number system. Even if the data is an integer, PSO and PSI indicate where the decimal place of the entered or output integer data should be. Although data bus 14 is only sixteen bits wide, a number with a range of 64 bits can be specified based on the 6-bit PSI and PSO values. A 6-bit PSO or PSI value gives 64 bits for the range of the integer. Where precision is required, integer data can therefore be stored with the desired accuracy, the decimal place being determined by PSO or PSI. On the other hand, if a dynamic range is desired, that is, flexibility in the determination range of the input and output integer data, the integer can simply be stored as an integer with PSI and PSO set to zero or a low number.

 Data register memory

Fig. 3 shows the data register memory 20 in more detail. The data register memory 20 has eight 16-bit registers, two of which are read-only registers, one of which contains only zeros and the other of which contains only ones. Since there are a total of eight registers, 3-bit lines are required to address each register.

The data register memory 20 has eight connections, namely five read connections and three write connections. Six connections (four for reading and two for writing) are connected to the computer 22 . The four read ports are labeled A, B, C, D and the two write ports are labeled P and M. Since six ports are used for the computer function and 3-bit lines are required to address each register for each port, eighteen address lines are needed to address data register memory 20 for computer 22 operation. These eighteen lines come from the IROM 40 .

Since only the converter 22 or the computer 18 is switched on, the connections to the converter 22 are shared or multiplexed with the connections to the computer 18 . Thus, the eighteen address lines from IROM 40 are also used to deliver data from data register memory 20 to converter 22 (a read port) and from converter 22 to data register memory 20 (a write port).

The other two connections of the data register memory 20 are a read connection to and a write connection from the data bus 14 . Since the read and write operations cannot occur simultaneously from the data bus 14 , only three address lines are required for this function. Thus, three of the five bus control lines from the PLA 42 are used as addresses, while another bus line is used for reading or writing.

The addresses for the data register memory 20 are supplied to an address encoder 90 , which has eight identical decoding areas, each of which is connected to a register in a data register array 92 by means of a plurality of word lines. Nine word lines are provided for the read / write registers, namely five to select the read connection or read connections, three to select the write connection and one to control the latch that holds the data. For the two read-only registers, only five word lines connect decoder 90 to data register array 92 . The five word lines select the read connection or the read connections. The five word lines to select the read port (s) are connected to a read port crosspoint matrix 100 which connects the latch 102 holding the data to one or more of the read ports.

The three word lines for selecting the write port are connected to a write port cross point matrix 104 which connects one of the write ports to the latch 102 .

The output of the data register array 92 is fed to an I / O buffer 94 .

The read-only ones containing all zeros or ones Registers can be made in different ways to be used. First of all, the content of this register be used where these numbers are in arithmetic  Operations are desired. Second, one Operation performed and the result in a read-only Registers are "registered". That way an update of the status can be done without the information output will be changed.

Logarithmic calculator

As already mentioned, the logarithmic computer 22 receives logarithmic data from the data register memory 20 , carries out these operations, and returns the resulting logarithmic data to the data register memory 20 for storage.

In FIG. 4, the logarithmic calculator 22 is shown in more detail. The logarithmic calculator 22 performs the tasks of calculating multiplication, division, addition and subtraction on four logarithmic data. The four input operands in the logarithmic computer 22 are labeled A, B, C and D , respectively. The logarithmic computer 22 has a first multiplier / divider unit 122 , a second multiplier / divider unit 124 and an add / subtract unit 126 .

The first multiplier / divider unit 122 receives data at ports A and B with which it carries out the operations A × B or A ÷ B.

The second multiplier / divider 124 works with the operands C and D and forms the result of C (× / ÷) D. The output of the first multiplier / divider 122 is the result U and the output of the second multiplier / divider 124 is the result V. The multiplication or division selection is controlled by one of the bit lines from the IROM 40 . The single bit line can control both the first and second multiplier / divider units 122 and 124 . However, a separate control line is also possible for each of the two units.

The results U and V of the first and second multiplying / dividing units 122 and 124 are applied to the adding / subtracting unit 126 , which produces the outputs U + V and U - V , respectively. These are then fed back to the data register memory 20 via the connections P or M.

Since the logarithmic computer 22 receives four operands and can carry out multiplication, division, subtraction and addition several times, the following functions can be carried out with the computer 22 in a single operation: The "1" and "0" at the input are provided by the read-only registers of the data register memory 20 .

In one embodiment, logarithmic calculator 22 requires two clock cycles to handle the four input operands to produce the two output results. To maximize efficiency, computer 22 is designed for pipeline processing, ie after a single clock cycle, computer 22 can pick up four new operands and begin processing them. Pipeline processing is well known. One way of pipeline processing is to store the results U and V in buffers at the output of the first and second multiplier / divider units 122 and 124, respectively. According to an alternative, the results U and V can also be stored at the input of the adding / subtracting unit 126 .

For the case of multiplication and division of two numbers A and B , which have been converted into a logarithmic representation, with a = log ₂ A and b = log ₂ B , the following results for the calculations: similar if U = A / B , log ₂ U = a - b .

In the logarithm area, the multiplication and division of integer data is carried out by adding or subtracting the corresponding logarithmic data. To carry out the multiplication or division of integer representations of the data, the first and second multiplier / divider units 122 and 124 only have an add / subtract unit to add or subtract the logarithmic representation of this integer data, with correction of the exponent sign (bias), limit (saturation) and status.

To perform addition and subtraction of integers in logarithmic representation, the following equation is given: This equation can be written as: where x = u - v , max ( u, v ) is the maximum value of u or v . If u _s and v _{s are} the signs of u and v , then where σ = u _s ⊕ v _s (⊕ is exclusive or). The equation of log ₂ (1 + σ 2 ^{- x} ) is shown graphically in FIG. 4a.

The add / subtract unit126 is in detail inFig. 4b shown. The two logarithmic numbers with which addition and subtraction should be carried out are by the lettersu andv reproduced. A first one Add / subtract unit128 determines the arithmetic productu -vwhile a second adding / subtracting unit 130 the arithmetic productv -u certainly. The outputs of the two add / subtract units 128 and130 are connected to a fifth multiplexer 132 created. The carry output bit of the second add / Subtraction unit130 is going to the fifth multiplexer132  and a sixth multiplexer134, a seventh multiplexer 136 and an eighth multiplexer138 created. The Inputs for the sixth, seventh and eighth multiplexers 134,136, respectively.138 are (u, v), (u _s ,v _s ) respectively. (u _s , _s ). The carry output bit of the second add / subtract unit130  determines whetherv ≦ λτu oru ≦ λτv. If the carry bit is "high" is, d. H.v ≦ λτu, then the content of the add / subtract unit 130 to an index register140 passed on. If the carry bit is "low", then the output of the Add / subtract unit128 in the index register140 saved. In any case, the index register saves140  the value:x =u -v .

The carry output bit of the add / subtract unit 130 also determines the output of the sixth, seventh and eighth multiplexers 134 , 136 and 138 , respectively. The output of the sixth multiplexer 134 is max ( u, v ). The output of the seventh multiplexer 136 is the sign S , which is supplied to the output term ( u + v ). The output of the eighth multiplexer 138 is the sign S , which is supplied to the output term ( u - v ).

The fifteen bits output by the fifth multiplexer 132 are fed to the index register 140 , which is then applied to a zero detector 142 . The index register 140 has the task of temporarily storing the data.

The thirteen output lines of index register 140 are fed to a second and third CAL circuit 144 and 146, respectively.

These two CAL circuits 144 and 146 are 512 × 13 bits each. The second CAL circuit 144 receives the output of the index register 140 and generates a 9-bit number which is the result of log ₂ (1 + 2 ^{- x} ). The third CAL circuit 146 receives the output of the index register 140 and produces the result of log ₂ (1-2 ^{- x} ). The output of the second CAL circuit 144 is then passed to a ninth multiplexer 148 , which is then applied to an adder 150 . The nine output bits of the third CAL circuit 146 are concatenated to six higher order zero bits from "0" to form fifteen bits which are fed to a tenth multiplexer 152 and from there to a subtractor 154 .

Index register 140 also applies nine bit lines to a read-only memory ROM 160 with thirteen output lines. The thirteen output lines are appended to two higher order bits to form fifteen bits which are fed to the tenth multiplexer 152 . The fifteen output lines from seventh multiplexer 134 contain the maximum of u or v and are fed to subtractor 154 and adder 150 . The output of adder 150 and subtractor 154 forms the result of log ₂ ( U + V ) and log ₂ ( U - V ), respectively.

The working theory of the logarithmic computer 22 will be explained below. As already said, the first and second add / subtract units 128 and 130 determine whether v is greater than u or not or whether u is greater than v . The absolute value of the size ( u - v ) is stored in the index register 140 . This is the value of x . If x is zero, this is detected by zero detector 142 . It should also be mentioned that x is still logarithmic and has the following form: The thirteen bits of x , which comprise the nine bits of mantissa and the first four bits of the exponent part (bits 0-3 of e), are supplied to the second CAL circuit 144 . As already mentioned, the output of the second CAL circuit is the result log ₂ (1 + 2 ^{- x} ). From Fig. 4a, it is apparent that the output of the second CAL circuit 144 is always a number that is between zero and plus one. Therefore, the nine output bits of the second CAL circuit 144 are all mantissa parts.

The two most significant bits of the exponent part of x , ie bits 4-5 of e are then passed to a test unit 149 which determines whether these two bits are zero. If the result of the test unit 149 is such that both bits are zero, then the test unit 149 selects the multiplexer 148 so that the output comes from the second CAL circuit 144 . On the other hand, if the result of the test unit 149 with respect to these two bits looks like they are not zero, then the output of the multiplexer 148 gets all zeros.

If the two most significant bits of the exponent part of x show that they are non-zero, it means that x is a very large number. From Fig. 4a it can be seen that the value of log ₂ (1 + 2 ^{- x} ) approaches asymptotically zero for very large numbers. The output of multiplexer 148 is therefore zero. On the other hand, if checking the two most significant bits of the exponent part of x shows that both are zero, then the value of x is not a number so large as to justify an output of all zeros. As a result, the output of the second CAL circuit 144 is passed through the multiplexer 148 .

The adder 150 receives the output from the multiplexer 148 and adds to it the value of the output of the multiplexer 144 which, as already said, supplies the maximum of u or v . So the output of the adder 150 is the term max ( u, v ) + log ₂ (1 + 2 ^{- x} ), that is log ₂ ( U + V ).

From index register 140 , the thirteen bits of the value of x , namely the nine bits of mantissa and the four least significant bits of the exponent, ie bits 0-3 of e , are also applied to the third CAL circuit 146 . The output of the third CAL circuit 146 is the expression log ₂ (1 + 2 ^{- x} ). The nine output bits of the third CAL circuit 146 are the mantissa part of the expression log ₂ (1 - 2 ^{- x} ). If x is greater than or equal to one, the expression log ₂ (1 - 2 ^{- x} ) is a number between zero and minus one. The nine bits of mantissa are appended to six zero bits to provide the fifteen output bits that are passed to multiplexer 152 .

If x is between zero and one, then the output of log ₂ (1-2 - ^x ), as shown in Fig. 4a, is a number between minus one and minus infinity. Since this is a mapping from a few numbers to a large number of numbers, a ROM 160 is used. The nine bits of the mantissa portion of x are applied to ROM 160 , with the result that thirteen bits of output are provided. These thirteen are supplemented by two further bits, which represent the direction sign of the exponent part (if the direction was negative, this would be "0") and the higher-order bit for the exponent, which would be "1". These fifteen bits are passed to multiplexer 152 . The four low-order bits of the exponent part of x , ie bits 0-3 of e, are checked in a second test unit 151 . The results of the first test unit 149 and the second test unit 151 are fed to a logic decoder 153 which controls the operation of the multiplexer 152 .

The operation of the multiplexer 152 is to be understood as follows: if all six bits of the exponent e are zero and the zero detector 142 is not zero, then the output of the ROM 160 is selected. If the zero detector 142 is zero, then the output of multiplexer 134 , ie max ( u, v ), is the output of multiplexer 152 . If the output of test unit 149 is not zero, the output of multiplexer 152 is all zeros. Finally, if the output of the test unit 151 is not zero and the output of the test unit 149 is zero, then the output of the third CAL circuit 146 is selected. The output of multiplexer 152 is subtracted from the maximum of u or v by subtractor 154 .

The multiplexer 152 is selected on the following basis. If the exponent part of x is all zeros and the zero detector 142 does not determine that x is zero, then it is clear that x is a number between zero and one, and consequently the output from ROM 160 is chosen. If x is zero, then log ₂ (1-1) is an undefined number and, as previously mentioned, processor 10 generates a special number. Max ( u, v ) is selected by multiplexer 152 and subtracted from itself in subtractor 154 . Thus the output of the subtractor 154 is the special number "0.. .0". If the output of the test unit 149 is not zero, then x is a large number and in this case log ₂ (1-2 ^{- x} ) is a number that approaches zero asymptotically. As a result, the multiplexer 152 selects a number consisting only of zeros. If the output of the test unit 149 is zero, ie if x is not a large number and the output of the test unit 151 is not zero, ie x is greater than +1, then the output of the third CAL circuit 146 is selected.

Since the number log ₂ (1 - 2 ^{- x} ) is always a negative number (see FIG. 4a), it is consequently subtracted from max ( u, v ) with the subtractor 154 in order to obtain the desired output max ( u, v ) + log ₂ (1 - 2 ^{- x} ), i.e. log ₂ (U - V).

 Comparator array logic, d. H. CAL circuit

FIG. 5 shows a CAL circuit 210 which has a multiplicity of comparators 212 . In the exemplary embodiment of the CAL circuit 210 shown in FIG. 5, N such comparison circuits are provided. A digital value is stored in each comparator 212 . The digital values stored in the N comparators are stored in monotonically increasing or decreasing order. Monotonically increasing or decreasing is to be understood to mean that the digital values stored in the N comparators 212 are all stored in ascending or descending order.

Each of the comparators 212 receives an input data signal that represents an input value. Each of the comparators 212 compares the digital value stored in it with the received data and generates a comparison signal as a function of this comparison. The comparison signal determines whether or not the value stored in each comparator 212 is strictly greater, which means that the stored value is less than or equal to the input data value. Each of the comparison signals is provided along one of the output lines 214 , all of which lead to an encoder 216 . Encoder 216 generates an output signal that represents the location of comparator 212 , the stored digital value of which is adjacent to the value of the input data. The output of encoder 216 may be the location of comparator 212 , the value of which is adjacent to the digital input data in that it is immediately larger than or equal to the input digital data. Conversely, the output of encoder 216 may be the location of comparator 212 , whose stored value is adjacent to the value of the input data in such a way that it is immediately smaller than the input data.

Since data is typically stored in a two-dimensional array so that fewer access lines are required than in a one-dimensional array, the CAL circuit 210 can similarly be arranged in a two-dimensional array form, which saves considerable wiring and makes the CAL circuit 210 more compact. In addition, encoder 216 could then be more compact and practical. For example, a linear arrangement of 512 comparators 212 required an encoder 216 with 512 inputs. A two-dimensional encoder, on the other hand, only requires 48 inputs in an arrangement of 16 × 32 (512 = 16 × 32).

FIG. 6 shows a further CAL circuit 310 , which is a two-dimensional array with a number of rows and a number of columns. There are many interconnected comparators 312 within each row of CAL circuit 310 . There are also a plurality of interconnected comparators 312 within each column. A digital value is stored in each comparator 312 . The array of a plurality of comparators 312 is arranged such that the values stored in the comparators 312 are stored in a monotonically increasing or decreasing sequence. Each comparator 312 is labeled C _ÿ , where i is the row number and j is the column number. The digital values can be stored in the CAL circuit 310 such that C ₀₀ ≦ ωτ C ₀₁ ≦ ωτ C ₀₂ ≦ ωτ C ₀₃ ≦ ωτ C ₁₀ . . . ≦ ωτ C _33. Hence C _ÿ ≦ ωτ C _{i ( j +1)} within each row and C _ÿ ≦ ωτ C _{( i + i ) j} within each column. Furthermore, in an M × N CAL circuit 310 , where 0 ≦ i ≦ M - 1 and 0 ≦ j ≦ N - 1, when the last column of a row i is reached, ie when C _{i , N -1} , the next value C _{i +1.0} , where C _{i, N -1} ≦ ωτ C _{i +1.0} .

Each comparator 312 includes a data input device 314 for receiving the input data signal. The input data signal at 314 represents an input value received by each comparator 312 and compared with the digital value stored therein. Each comparator 312 generates a comparison signal 316 depending on the comparison of the input data value with the stored digital value. An end cell EC _ÿ 320 is assigned to each comparator C _ÿ 312 in each row. Each end cell EC _ÿ 320 receives the comparison signal 316 from the comparator C _ÿ 312 and the comparison signal 316 from an immediately adjacent comparator C _{i ( j -1)} 312 . Each end cell EC _ÿ 320 generates an output signal 322 , which is fed to the gate of a pull-down transistor 324 . Pull-down transistor 324 has a source that is at ground potential and a drain that is connected to each column bit line.

Similarly, between each adjacent row of comparators 312 in the last column there is an end cell EC _{i, N -1} 321 , which contains the comparison signal 316 from the comparator C _{i, N -1} 312 and the comparison signal 316 from the immediately adjacent comparator C _{( i +1), N -1} 312 in the same column. The end cell 321 generates an output signal 323 which is applied to the gate of a column pull-down transistor 325 . This pull-down transistor 325 has a source at ground potential and a drain connected to each row bit line.

Each end cell EC _{ÿ of} the row or column type 320 is shown as logic in FIG. 7 and is identical. Each end cell 320 has an AND gate with two inputs, of which one the Vergelichssignal receives 316 from the comparator 312 associated with 320 of the end cell, and the other the comparison signal 316 is obtained from the immediately adjacent comparator 312 after a in Inverter was inverted. Logically, this is the same as a NOR gate with an inverted input.

As already mentioned, a digital value is stored in the comparator 312 . The digital value is represented in binary form. As a result, the comparator 312 has a plurality of interconnected bit comparators 326 . Such a bit comparator 326 is shown in FIG. 6a. Each of the bit comparators 326 is connected to the adjacent bit comparator 326 . A single bit value is stored in each of the bit comparators 326 and each bit comparator compares a single bit of the input data signal 314 with the stored bit. Each of the bit comparators 326 has an input, shown as C _IN , at which it receives the output of the comparison from the immediately adjacent bit comparator 326 . The signal at C _IN is supplied to the source of a first transistor 328 . The first transistor 328 has a gate that receives a single bit of the input data signal. The first transistor 328 also has a drain connected to the drain of a second transistor 330 . The second transistor 330 has a source that is either connected to V _DD or grounded, depending on whether the stored value is binary 1 (in this case it is grounded) or binary 0 (in this case the source is at V _DD) connected). The second transistor 330 has a gate which also receives a single bit of the input data signal. The drain of the second transistor 330 is connected to the drain of the first transistor 328 and they form the output of the bit comparator 326 , which is shown as C _OUT .

So for bit _k , which is programmed to "1", the source of the second transistor330 grounded.   lies at the gate of the second transistor330 andD at the gate of the first Transisitor328 at. If reverse bit _k  programmed like this is that it is "0" then the source of the second Transistor330 atV _DD  connected.D is going to the Gate of the second transistor330 and  to the gate of the first Transistor328 delivered. As a result, this works in addition that a maximum of 2 transistors per bit is required will.

In Fig. 6b, the bit comparator 326 in Fig. 6a 05685 00070 552 001000280000000200012000285910557400040 0002003622205 00004 05566 shown separately which is programmed so that it is "1" or "0". The embodiment of the bit comparator 326 shown in FIGS . 6a and 6b is the preferred embodiment.

A modification of the bit comparator 326 is shown in FIG. 6c. In this embodiment, the comparator 326 has a double bit comparator. Each of the four circuits shown in Figure 6c belongs to comparator 326 and is programmed to store the values "00" or "01" or "10" or "11". Inputs D ₃ , D ₂ , D ₁ and D ₀ are decodings of two-bit input signals, and all four must be high when precharging. If speed is desired, this is the preferred embodiment because of the rapid propagation.

FIG. 6d shows a further modification of the bit comparator 326th In this embodiment, each of the cells of bit comparators is self-driving.

InFig. Finally, 6e is yet another embodiment a bit comparator326 shown. This bit comparator 326 is a dynamic carry chain where KE goes deep during the evaluation and  =  = high during the Subpoena. This embodiment probably needs less semiconductor area than the exemplary embodiment with self-boosting or the preferred embodiment.

The logical equations of the comparator 312 assigned to each end cell 320 are shown in FIG. 7. It is assumed that for the least significant bit, ie the rightmost bit of the bit comparator 326 , C _{IN is set} to logic 0, which means that C _{IN is} tied to ground potential. The calculation of C _OUT depends on variables B and D , of which B is the value of the stored bit within each bit comparator 326 and D is the value of the binary data in the input data signal.

Fig. 8 shows another embodiment of a bit comparator 426th A plurality of the bit comparators 426 connected to one another form the comparator 312 . Bit comparator 426 differs from bit comparator 326 in that it has a bit value that is changeable. The variability of the bit stored in binary comparator 426 occurs as follows. A separate latch or memory location 425 stores the value of the bit in the comparator 426 . Changes in the bit value of the memory cell 425 change the bit comparator 426 . Storage space 425 may be a latch, flip-flop, static RAM, ROM, or any other storage device.

Another programmable bit comparator 426 is shown in FIG. 8a. Each of the transistors in bit comparator 426 has a floating gate 428 . The programmability can be achieved by removing the floating gate 428 during the masking step and causing the transistor to always be on or off or to be switchable by means of the gate signal. Of course, floating gate 428 can also be programmed in the field using known E ² technology.

The CAL circuits 210 or 310 can be used in many ways. A special application is in the case of lookup functions, where there is a monotonous function in which there are I bits input versus 0 bits output, I being greater than 0. The CAL circuit can be used for functions that increase and also decrease monotonously. Some of the use cases that meet these criteria are log conversion, spell checking, database operations and token passing identification in high-speed networks.

A conventional memory such as a read-only memory ROM or a random access memory RAM can be used for this lookup function; but then the number of memory cells required would be orders of magnitude higher. For example, a ROM lookup table with I inputs and 0 outputs requires 2 ^I times 0 bits, where I is greater than 0. On the other hand, the CAL circuit only requires 2 ⁰ times I bits. If I = 15 and 0 = 9, a ROM 2 would require ¹⁵ × 9 or 294 912 memory cells. A CAL circuit, on the other hand, would require 2 ⁹ × 15 or 7680 memory cells. Although a CAL circuit requires that at least two transistors be used for each bit comparison (as shown for bit comparator 326 in the embodiment of FIG. 6a), this means that a total of 15,360 transistors would be required in the embodiment described above. With a ROM implementation and assuming only one transistor per bit, the same circuit would need 294 912 transistors. This results in a significant saving in transistors.

Claims (27)

1. Digital circuit, characterized by
means for receiving a digital input data signal representing an input value;
a multiplicity of comparators which store a multiplicity of digital values in a monotonically increasing or decreasing sequence;
- wherein each comparator has a device for receiving the digital input data signal, a device for comparing the same with the stored digital value and a device for generating a comparison signal as a function of the comparison; and
- A coding device which responds to the plurality of comparison signals to produce an output signal, the output signal representing the location of the comparator whose stored digital value is adjacent to the value of the input value. 2. Comparator array logic circuit, characterized by
means for receiving a digital input data signal representing an input value;
- A large number of interconnected comparators, which are arranged in an array and store a large number of digital values in monotonically increasing or decreasing sequence; and
- wherein each comparator means for receiving the digital input data signal, means for comparing the same with the stored digital value, means for generating a comparison signal in dependence on the comparison, means for receiving the comparison signal from a directly adjacent comparator and one Means responsive to the comparison signal from each comparator and the comparison signal from the adjacent comparator to produce an output signal;
- So that the plurality of output signals indicates the location of the comparator whose stored digital value is adjacent to the value of the input value. 3. Circuit according to claim 2, characterized in that the digital Input data signal is in binary form. 4. Circuit according to claim 3, characterized in that each comparison cher also a plurality of interconnected bits has comparators, in each of which a bit value is stored chert is, the bit comparator is a bit of the digital Input data signal compared with the stored bit. 5. Circuit according to claim 4, characterized in that the comparators are arranged in a two-dimensional array, which a variety of rows and a variety of columns having. 6. Circuit according to claim 5, characterized in that each bit ver same also a device for changing the food bits. 7. Circuit according to claim 5, characterized in that each one Value of "1" storing the first bit comparator Has transistor with source, gate and drain, the supplied data to the gate and the input from the immediately adjacent bit comparator to the source is supplied, and a second transistor with source, Has gate and drain, the inversion of the supplied led data supplied to the gate, the source grounded and the drain is connected to the drain of the first transistor is closed, the output of the comparator is the drain of the second transistor.   8. Circuit according to claim 5, characterized in that each one Bit comparator storing value "0" a first transi stor with souce, gate and drain, in which the inversion of the data supplied to it is delivered to the gate and the on from the immediately adjacent bit comparator to the Source is supplied, and with a second transistor Has source, gate and drain, at which the supplied to him Data sent to the gate, the source to a span Power source connected and the drain with the drain of the first transistor is connected, the output of the Comparator is the drain of the second transistor. 9. Digital computing device, characterized by
a device for the simultaneous reception of four operands (hereinafter " a , b , c , d ");
a first multiplier / divider unit for performing the calculation of a × b or a ÷ b and for supplying an output u ;
a second multiplier / divider unit for performing the calculation c × d or c ÷ d and for supplying an output v ;
- a device for performing the calculation u + v and u - v ; and
- Means for controlling the first and second multiplier / divider for performing the calculation of the multiplication or division. 10. The device according to claim 9, characterized in that the operands Numbers are in logarithmic representation. 11. The device according to claim 10, characterized in that the first and second multiplier / divider one add / Has subtraction unit.   12. The apparatus according to claim 11, characterized in that the Einrich device for performing the function u + v and u - v further comprises the following:
means for determining the absolute value (hereinafter " x ") of the difference between U and V ;
- A first CAL circuit for receiving x and for generating a digital value output in a logarithmic representation of log ₂ (1 + 2 ^{- x} ); - a second CAL circuit for receiving x and for generating a digital value output in a logarithmic representation of log ₂ (1 - 2 ^{- x} ); - wherein the first and second CAL circuits each have a large number of interconnected comparators which are arranged in an array and store a large number of digital values in monotonically increasing or decreasing sequence, each comparator devices for comparing x with the digital value stored in the comparator, means for generating a comparison signal as a function of the comparison, means for receiving the comparison signal from an immediately adjacent comparator; a device responsive to the comparison signal from each comparator and the comparison signal from the adjacent comparator to produce an output signal; comprises means for receiving the plurality of output signals and for generating the digital value output;
a device for determining the larger of the two numbers u and v (hereinafter max ( u , v ); and
- A device for summing max ( u, v ) with the digital value output;
- so that max ( u, v ) + log ₂ (1 + 2 ^{- x} ) the term u + v in lo githmic representation and max ( u, v ) + log ₂ (1 - 2 ^{- x} ) the term u - v is in logarithmic representation. 13. The apparatus according to claim 12, characterized by
a ROM table device for receiving x and for generating a digital value output, in logarithmic representation, log ₂ (1 - 2 ^{- x} ); - means for receiving the output from the ROM and the second CAL circuit and for generating a digital value output;
a device for supplying the digital value output of the receiving device to the summing device;
a device that determines whether x ≦ ωτ 1.0; and
means for controlling the receiving means based on the output of the determining means; so that the output of the ROM is selected when x ≦ ωτ 1.0, is selected from the output of the second CAL circuit when x ≧ 1.0. 14. The apparatus according to claim 13, characterized by
a device which determines when x is zero and which provides an output to the device for controlling the receiving device,
- In the event that x = 0, the output max ( u, v ) is also supplied to the receiving device and the control device for selecting max ( u, v ). 15. Digital computing device for simultaneous calculation of the sum and the difference of a first number, U and a second number, V , each of which is present in a logarithmic representation of U or V , characterized by
a device which determines the absolute value (hereinafter " x ") of the difference between U and V ;
- A first CAL circuit for receiving x and for generating a digital value output, in logarithmic representation, of log ₂ (1 + 2 ^{- x} );
- A second CAL circuit for receiving x and for generating a digital value output, in logarithmic representation, of log ₂ (1 - 2 ^{- x} );
- Wherein the first and second CAL circuit each have a plurality of interconnected comparators, which are arranged in an array and store a lot of digital values in monotonically increasing or falling as a result, each comparator means for x means for comparing x with the digital value stored in the comparator, a device for generating a comparison signal as a function of the comparison, a device for receiving the comparison signal from an immediately adjacent comparator, one on the comparison signal from each comparator and the comparison signal from the adjacent comparator under generation a device responsive to an output signal, means for receiving the plurality of output signals and for generating the digital value output,
means for determining the larger of the two numbers u and v (hereinafter max ( u, v )); and
- A device for summing max ( u, v ) with the digital value output; so that max ( u, v ) + log ₂ (1 + 2 ^{- x} ) the term u + v in lo-graphical representation and max ( u, v ) + log ₂ (1 - 2 ^{- x} ) the term u - v in logarithmic representation. 16. The apparatus according to claim 15, characterized by
a ROM table device for receiving x and for generating a digital value output, in logarithmic representation, log ₂ (1 - 2 ^{- x} ); - means for receiving the output of the ROM and the second CAL circuit and for generating a digital value output;
- A device that supplies the digital value output of the receiving device to the summing device;
a device that determines whether x ≦ ωτ 1.0; and
means for controlling the receiving means based on the output of the determining means;
- So that the output of the ROM is selected if x ≦ ωτ 1.0 and the output of the second CAL circuit is selected if x ≧ 1.0. 17. The apparatus according to claim 16, characterized by
means for determining when x is zero and providing an output to the means for controlling the receiving means;
- In the event that x = 0, the output max ( u, v ) is also supplied to the receiving device and the control device for selecting max ( u, v ). 18. A digital device for converting a digital binary integer containing a plurality of bits into a logarithmic representation characterized by
means for determining the leading non-zero bit position of the integer;
means that shifts the integer so that the leading non-zero bit is the left-most bit;
a table device which receives the digitized integer and delivers a number which represents the mantis part of the logarithm of the digited digit, and
an encoder which receives a comma input value and the number of binary positions shifted by the shifter and generates the exponent part of the logarithm of the integer, the comma input value being the scale factor for the integer, so that the mantissa part and the exponent part are the logarithmic Form representation of the integer. 19. The apparatus according to claim 18, characterized in that the tables setting up a CAL circuit with a variety of below having interconnected comparators in one Arrays are arranged and a variety of digital values save in a monotonically increasing or decreasing sequence, each comparator means for receiving the digitized integer, a device for ver same with the one stored in the comparator Digital value, a device for generating a comparison signals depending on the comparison; a facility device for receiving the comparison signal from an immediate bar neighboring comparator, one on the comparative sig nal from each comparator and the comparison signal from the be neighboring comparators generating an output sig as an attractive facility; a facility for reception the large number of output signals and for generating the Number that has the mantissa part of the logarithm of the represents a staggered number. 20. Digital device for converting the digital, logarithmic, exponent part and a mantissa part representation of an integer into a binary integer, characterized by
a table device which receives the mantissa part of the local representation and supplies a first number;
a decoder which receives the exponent part of the logarithmic representation and a comma set value and delivers a shift signal, the comma set output value being the scale factor for the integer; and
- A shifter that receives the shift signal and the first number and shifts the first number by means of the Ver shift signal to generate the integer. 21. Digital processor with an address bus and a data bus for communication, characterized by
data register means for communicating with and receiving and storing data from the data bus, the data being in one form;
- A data conversion device which can be connected for communication with the data registration device, in order to convert the data in one form from the data register device into data of another form and to receive data in the other form from the data register device and into data of the one Convert form and to store the converted data in the data register device;
- A computing device which can be connected for communication with the data register device, in order to receive data in the form thereof, to perform calculations on these and to store the results of the calculations in the data register device;
a control device for communication with the address bus and the data bus, which has a program cache memory which stores program commands from the data bus, a device for decoding the program commands and a device for generating internal commands; and
an internal bus device that connects the control device for communication with the data register device of the data conversion device and the computing device for communication of the internal commands,
- So that the control device controls the operation of the processor via the internal commands. 22. The processor according to claim 21, characterized in that the in the a form of existing data is integer data. 23. The processor according to claim 22,  characterized in that the in the whose form existing data are logarithmic data. 24. The processor according to claim 23, characterized in that the computing device is a logarithmic calculator. 25. Processor according to claim 24, characterized in that in the other Form data is floating point data. 26. Processor according to claim 25, characterized in that the arithmetic direction is a floating point calculator. 27. Digital processor with an address bus and a data bus for communication and with a control device for generating program instructions for controlling the processor, which has an address register memory for storing addresses from the address bus, characterized by
- An index unit that can be connected for communication with the address register memory;
- This unit has a device for receiving a current address from the memory;
means for receiving a test address from the memory;
means for receiving a change address from the memory;
- A device for receiving a reload address from the memory;
the unit further comprising means for changing the current address by the change address to generate a result address, means for comparing the result address with the check address, and means for storing the reload address as the current address in the address register memory based on the comparison between the result address and the test address.