DE3614428A1 - DIGITAL PHASE / FREQUENCY DETECTOR CIRCUIT - Google Patents

Description

LIECK & BEDS

• - Patent attorneys Dipl.-Ing. H.-Peter Lieck

European Fatent Attcreys Dipl.-Ing. Jürgen Betten

3 6 I 4 4 2 O Maximiliansplatz

D-8000 Munich 3> «089-291119

Telex 5 216 741 list d Fax 089-2915 Technolaw® Telegram Electropat

Description Digital phase / frequency detector circuit.

The invention relates to circuit arrangements for comparing the phase / frequency difference between two digital input signals and relates in particular to a method and a circuit arrangement for Extending the linear phase modulation range of a digital phase / frequency detector in a phase locked loop (PLL).

Circuit arrangements for detecting the phase and frequency difference between two digital input

Signals are generally used in signal evaluation

used and are of particular importance in digital transmission technology and in digital Frequency synthesis. For example, in a digital phase-locked loop, an input signal is used to are supplied to a phase detector with a reference signal. One of the momentary Phase / frequency difference between the input signals dependent error signal is filtered and used to control a voltage controlled oscillator (VCO) uses. The output of the VCO, which is the output of the p ^U: »Senstarren loop forms, is fed to the phase detector as the ßzugssignal and causes the phase / frequency of the VCO with the phase / frequency of the

Input signal locks into place. In some applications, phase-locked loops are used for signal demodulation. See Chapter 9 in Gardner, Floyd M., Phase Lock Techniques , 2nd Edition 1979, John Wiley & Sons. In other applications, phase-locked loops are used for signal modulation (Chapter 9 in Gardner, as above) or in frequency synthesis, as described in US Pat. No. 4,360,788.

In either case, a conventional digital phase / frequency detector comprises a pair of flip-flops or other bistable switching elements that connect with each other and with are connected to a logic element in a feedback circuit. The logic states of the two flip-flops are determined by the two digital input signals, their frequency / phase difference is to be, and the logic element of the feedback circuit certainly. The flip-flops are initially in a reset state; it is up to theirs Data connections to a logical "1", and their clock connections each receive one of the two digital input signals. The output of each flip-flop is set to a logical "1" is set as soon as a positive transition of its input signal is detected. So has that input signal fed to the first flip-flop causes the first positive transition, the first flip-flop opens a logical "1" is set, and then the second Flip-flop set to a logical "1". Immediately after the second flip-flop is set, however both flip-flops reset by the logic element, which responds to the outputs of the two flip-flops, and both remain in the reset state, until one of them detects a positive signal transition again at its input.

The output signals of the two flip-flops are thus Square waves, whose duty cycle is the phase / frequency difference between the two input signals. When the first signal is opposite to the second Signal leads, only the first flip-flop generates a square wave, where the duty cycle is the amount of Phase / frequency advance of the first compared to the second input signal. The second input signal rushes before, only the second flip-flop generates a square wave, and in this case the duty cycle is the same the amount of phase lead of the second compared to the first input signal. The two square waves are combined in a differential circuit, and the resulting signal is integrated to obtain a sawtooth voltage centered on zero, that is, when the first input signal leads has one polarity and the opposite polarity when the second input signal is advanced. The amplitude the sawtooth voltage corresponds to the phase / frequency difference between the two digital input signals, and the period is fixed and amounts to 360 °. If the phase / frequency difference between the two input signals increases monotonically, the output of the detector is a sawtooth pulse train with a number Sawtooth periods, which is the number of full periods of the phase / frequency difference between the two digital ones Corresponds to input signals.

The invention is based on the object of providing a method and a circuit arrangement for expanding the response or to create the working area of a digital phase / frequency detector.

This task is with a method and a circuit arrangement solved, which are characterized with their respective configurations in the claims.

According to the invention, the maximum output becomes mean of a digital phase / frequency detector is enlarged in that the detector output is at a peak value is set when the phase / frequency difference between the input and the reference signal a Has a predetermined value that then internal circuit parts are reset, and that the additional phase / frequency difference is added to the detector output. A circuit arrangement is used which is based on responds to the maximum range of the detector and emits an output signal that corresponds to the detector output signal is added.

In the following the invention with its advantages and its further advantageous refinements is based on a preferred, schematically illustrated embodiment explained in more detail. In the drawings show: Fig. 1 is a block diagram of a conventional one digital phase-locked loop of the type in which the phase / frequency detector according to the Er

finding can be used,

Fig. 2 is a circuit diagram of a conventional digital Phase / frequency detector, over which the invention represents an improvement, Fig. 3 waveforms for explaining the operation

of the detector according to FIG. 2,

Fig. 4 shows the output characteristic of the same detector, Fig. 5 the desired characteristic of the invention the enhanced digital phase / frequency Detek ^tors>

Fig. 6 various resulting from the invention

Time domain waveforms, and 7 shows a circuit diagram of the detector according to the invention.

The detector according to the invention is designed so that is the linear phase modulation range of a digital phase locked loop of the type disclosed in U.S. Pat 4,360,788 and US patent application 629,555 and in frequency synthesizers manufactured by the applicant is built in, is expanded.

The conventional phase locked loop (PLL) 10 shown in Figure 1 comprises a phase detector 12 of the type to which the invention is directed, a filter 14 and a voltage controlled oscillator (VCO) 16 connected together in a feed forward loop. The phase detector 12 receives an input signal F- at one input and a reference signal F _r at a second input and generates a signal which corresponds to the phase and frequency difference between the two input signals F. and F. The detector signal is filtered or smoothed by the filter 14 and fed to the control input of the VCO 16. Its output is fed back to the phase detector 12 _{as the reference signal F r} via a programmable frequency divider 18. As described in detail in US Pat. No. 4,360,788, the signal f generated by the VCO 16 is regulated to a frequency which, depending on the programming of the frequency divider 18, is a harmonic or a subharmonic of the input signal F .., and to a phase position that is shown in has a certain relationship to the phase position of the input signal, which is dependent on an offset bias voltage built into the detector.

Although a phase-locked loop like the one in Fig.

1, is a particularly important application of the phase detector according to the invention numerous other applications in the fields of signal processing and signal measurement.

The relatively low maximum mean value of the output signal from the conventional phase / frequency detector, over which the invention is an improvement, must be fully understood in order for the meaning of the invention to be understood. Referring to Fig. 2, a conventional detector has a pair of flip-flops 20, 22, which are shown as D-type flip-flops for clarity of explanation. In the case of a D-type flip-flop, a logic level or switching value applied to the D terminal is transferred to the Q output terminal when a rising clock pulse edge occurs at the clock terminal. Each of the flip-flops 20 and 22 also has an output ^{terminal Q 1} , which generates the logical complement to the output terminal Q, and a reset terminal R, which is dependent on a logic "0" or a signal with the switching value 0 or with a "low" level resets the output terminal Q to a logic "0". For a better explanation, it is assumed in the case of flip-flops 20 and 22 that the Η assignment applies to them, ie

that a logic "1" corresponds to a "high" voltage and a logic "0" corresponds to a "low" voltage.

An associated input of a NAND element 24 is connected to each of the Q outputs of the flip-flops 20 and 22, and its output is connected to the reset connections R of the two flip-flops 20 and 22. The D input of each of the flip-flops 20 and 22 carries a logic "1", and a first variable signal or input signal V or a second fixed signal or reference signal R is present at the two clock connections. The input signal V can F .. and the input signal R can correspond to the signal F _p in FIG. 1; however, this assignment is not mandatory. Furthermore, although both signals V and R are generally digital signals or square waves with variable and different frequencies and phases, the signal R can be a reference

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signal with fixed frequency and fixed phase.

The Q outputs 26 and 28 of the flip-flops 20 and 22 are each connected to a filter 30 provided if required and 32, respectively. The output signals U and L of them are fed to a summing circuit 34, whose Output in an integrating circuit 36 is averaged or smoothed in the usual way. When using the detector circuit 12 in a phase-locked loop, the output signal integration becomes that of that in phase-locked Loops of conventional filters, e.g. 14 in Fig. 1, are carried out.

Basically, the detector 12 becomes the Q output each flip-flop 20 or 22 is set to logic "1" if at its clock input due to the input signal V or R a positive transition occurs. However, if both flip-flops 20 and 22 are set, the NAND gate is 24 at its output a low or "0" level to the reset terminal R of both flip-flops 20 and 22, which causes both Q outputs to be reset to switching value 0. So either the flip-flop 20 or the flip-flop 22 set, depending on which of the input signals V and R a positive transition occurs first. Both flip-flops 20 and 22 are reset when the second of the both input signals V and R a positive transition or a positive edge occurs. The two flip-flops 20 and 22 thus generate square waves with key Ratios that of the phase and frequency difference between the two input signals V and R correspond. If the input signal V leads the input signal R, dominates flip-flop 20 and generates a square wave, while flip-flop 22 does not. If the input signal R rushes before, the flip-flop 22 dominates and generates a square wave, while the flip-flop 20 does not.

The operation of detector 12 and how it relates to the improved detector of the present invention are detailed with reference to Fig. 3, which shows common waveforms generated in the phase detector 12, and Fig. 4, in which the output waveform is shown is.

FIGS. 3 (a) and 3 (b) show input signals V and R, respectively, which are connected to the clock connections of the flip-flop 20 or 22 are supplied. These two input signals have different frequencies and can be different Have duty cycles, albeit duty cycles are not important because each flip-flop 20 and 22 is responsive to the leading edge. In Figs. 3 (c) and 3 (d) are the waveforms of the output signals on lines 26 and 28 are shown.

It is assumed that both flip-flops 20 and 22 are initially triggered by the first positive transition 38 'of the input signal V are reset, whereby the Q outputs of both flip-flops 20 and 22 have the switching value 0 lead (see at 40 'and 42' in Fig. 3 (c) and 3 (d)). Of the next positive transition 44 'of the input signal R (s. Fig. 3 (b)) has the effect that the Q output of the flip-flop is set to the switching value 1 (see at 46 'in Fig. 3 (d)). When the next positive transition 48 'of the input signal V (see FIG. 3 (a)) occurs, the The Q output of the flip-flop 20 is set to the switching value 1, and the NAND gate 24 speaks almost immediately and resets both flip-flops 20 and 22, the Q output of flip-flop 22 being set to the switching value 0 is reset (see at 50 'in Fig. 3 (d)).

This cycle of events is repeated when the positive transition 52 'of the input signal occurs R and the positive transition 54 'of the input signal V,

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and is repeated again when the positive transitions 56 'and 58' of the input signals R and V occur During this period of time, the flip-flop 22 generates a square wave with a duty cycle due to its "dominance" the smaller as the phase / frequency difference between the two input signals R and V decreases will; the output of the other flip-flop 20 remains at the switching value 0.

After the occurrence of the positive transition 60 'of the input signal However, V is the pulse frequency applied to the clock terminal of flip-flop 20 such that two pulses with positive transition are present, namely one with the positive transition at 58 'and the next Pulse with the positive transition 60 'before the next pulse with a positive in the input signal R Transition 62 'occurs. The effect of the second consecutive pulse at 60 'is to to set the output of the flip-flop 20 now to the switching value 1, because both flip-flops 20 and 22 before the positive pulse transition 60 'were reset. Then the positive transition 62 'of the input signal R resets the Q output of the flip-flop 20, and the sequence continues with enabled flip-flop 20 and disabled flip-flop 22 (see Fig. 3 (c) and 3 (d)). The sequence eventually runs again when the phase and frequency difference between the input signals V and R changes, one of the flip-flops 20 and 22 is continuously enabled and a square wave with a duty cycle equal to that of the Phase / frequency difference is generated, and the other flip-flop is blocked. Which of the two flip-flops 20 and 22 is released at a given point in time depends on which of the input signals V and R is leading.

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As already mentioned, the output lines 26 and 28 of the flip-flops 20 and 22 are provided as required Low-pass filters 30 and 32 to a differential circuit 34 out, the output of which by an integrating circuit 36 is averaged or smoothed.

The difference signal smoothed by the integrating circuit 36 is a sawtooth voltage (see Fig. 3 (e)) which passes through zero when, as for that in Figs. 3 (a) through 3 (d), the "dominance" between flip-flops 20 and 22 alternates, and which with the duration of a complete phase / frequency period (2 ^) (see Fig. 4) repeated. When there are two input signals V and R are in a positive or negative single period in which they synchronize with each other or locked, the detector identifier is located in the so-called active area (see Fig. 4). Are the two input signals V and R outside the active area, the phase detector 12 generates a sawtooth signal with a maximum mean value (dashed Lines in Fig. 4), the size of which corresponds to half the peak value of the sawtooth and its polarity depends on which of the two signals is leading.

Fig. 5 shows the desired typical course of the output in the digital phase / frequency detector according to the invention in contrast to the output of a conventional detector shown in FIG. In Fig. 5, the zero current level is defined by the zero axis 100. Point 102 on the zero axis represents the point in which the input signal V coincides in phase with the reference signal R. From point 102 to the right going the input signal V leads the reference signal R, conversely, going to the left, the input signal leads V according to the reference signal R.

As the phase difference between the input signal V and the reference signal R increases, the current increases in accordance with the slope 104 and reaches the normal output level 106. At the point 2 V of the normal output level 106 there is a slight discontinuity, which is described in more detail below; thereafter the current increases up to point 4 & to the peak output value 108, which is approximately twice the normal output level 106. As the phase difference increases beyond 4 it , a discontinuity results, which means that the current falls from the peak output level 108 to the normal output level 106. As the phase difference increases further, the current begins to increase again towards the peak output level 108.

This repeats itself indefinitely every 2 /? .

The discontinuities at the zero axis 100 are due to different time delays in the flip-flops 20 and 22 return. The discontinuity at the normal output level 106 is due to the difficulty of the current level of a flip-flop 124 to match that of the flip-flop 20.

In the opposite case, if the input signal V lags the reference signal R, the digital phase / Frequency detector in a conventional manner, as the current increases in the negative direction until the negative peak output level 110 is reached at which with As the phase difference increases, a discontinuity occurs, which means that the current returns to the zero level 100 drops.

Because the electronic components in the detector do not work in an ideal way, certain discontinuities arise and disturbances occurring at the normal output level 106 and at the zero level 100. To an ar-

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To avoid working on one or the other of these two points, it is desirable to use the operating point of the detector away from these two points. In the preferred embodiment, the operating point is H2 chosen to be midway between the positive peak output level 108 and the negative Peak output level 110 is.

With the one chosen in the preferred embodiment The maximum possible operating point is obtained for both a leading and a lagging phase position Working range of the phase / frequency detector. Another The advantage is that by defining the operating point as far away as possible from the discontinuities, in this case in the middle between them, the percentage distortion in proportion to a pretty large phase deviation becomes small.

The flip-flops 20 and 22 shown in Fig. 7 are usually part of a conventional phase / frequency detector. The input signal V is also fed to the clock input of the D-type flip-flop 124, its reset input with the preset1 input of the flip-flop 20 is connected. (It has not been mentioned before that D-type flip-flops are commonly are equipped with preset inputs P.) The input signal V is also a flip-flop 126 of the D-type fed to the preset input at its Q 'output of flip-flop 20 and the reset input of flip-flop 124 is connected.

The Q output of the flip-flop 124 is connected to the D input of the flip-flop 126 and the clock input of a monostable Multivibrators 128 connected. The Q 'output of the flip-flop 124 arrives at an OR gate 130 negative input, the output of which is connected to a pulse

voltage circuit 132 is connected, which consists of a Resistor 134, which is connected to the D input of the flip-flop, and a resistor 134 to ground 138 connecting capacitor 136 is composed.

The Q output of the flip-flop 20 is connected to an AND gate 140, the output signal of which is the input a NOR gate 142 is supplied. The Q output of the flip-flop is connected to the other input of the AND gate 140 22 connected. The NOR gate 142 is at its second input to the Q output of the multivibrator 128 and sends its output signal to the reset inputs the flip-flops 20 and 22 off. The Q output of flip-flop 20 is also connected to summing circuit 34 and connected via this to the integrator 36. The summing circuit 34 also sums signals from the Q outputs of flip-flops 22 and 124.

The flip-flop 126 is connected at its Q output to a reset threshold circuit 144, which consists of a capacitor 146, which is connected to the reset input of the flip-flop 126 and via a resistor 148 the Q output of the flip-flop 22 is connected.

With reference to FIGS. 6 and 7, the mode of operation of the detector according to the invention is explained on the basis of a time domain representation. Since the detector operates almost the same as that of the conventional detector when the input frequency V leads the reference frequency R by less than 2 ^, the following description will focus on the area in which the phase difference approaches 2 It .

As the difference approaches the amount 2 » , the pulse duty factor of the pulse 114 approaches

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The illustrated Q output of the flip-flop 120 has the value 100% (full width), whereas the Q 'output approaches the value 0% (width zero). This has the effect that the output of the OR gate 130 via the pulse stretching circuit 132 holds the D input of the flip-flop 124 at the level or the switching value 1 until the next leading edge of the input signal V causes the state of the flip-flop 124 to change. When the flip-flop 124 changes its state, the Q output assumes the switching value 1. At the same time, the Q 'output of the flip-flop 124 assumes the switching value 0, which causes the OR gate 130 to maintain the switching value 1 and the D input of the flip-flop 124 to the switching value 1.

Thus, at point Iff, the Q output of the flip-flop is fed to the summing circuit 34 and is summed in it with the Q output of the flip-flop 20.

At the same time, the Q output of flip-flop 124 is fed to the clock input of multivibrator 128. Of the The tilting process of the flip-flop 124 causes the change in state of the multivibrator 128 by an output pulse to generate, which resets the flip-flops 20 and 22 by means of the NOR gate 142.

When the flip-flop 20 is reset, the Q output assumes the switching value 0; it therefore sends no usable signal to the summing circuit 34. As the phase difference increases above 2 ff , the pulse width of the Q output from flip-flop 20 increases and is added to the normal output from the Q output of flip-flop 124.

When the phase difference increases from 2 ff to 4 fi * and above, the output of the flip-flop 124 remains at the switching value 1, with the result that the flip-flop 20 of the

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Effect of the detector according to the invention that of a conventional detector clearly superimposed.

In the above, the relationships have been described when the input signal V with respect to the reference signal R increases continuously. On the other hand, when the phase difference decreases, whereby the input signal V approaches the reference signal R more closely, the operation is somewhat different. If the phase difference changes from an amount greater than ItY to an amount less than 2 ff (see Fig. 5), the duty cycle of the pulses from the Q output of the flip-flop 20 goes back to zero percent and the duty cycle of the pulses from the Q. -Output of flip-flop 22 increases. When a predetermined pulse width (duty cycle) determined by the capacitor 146 is reached, the reset signal to the flip-flop 126 is so largely eliminated that the input signal V at the clock input of the flip-flop 126 can cause the Q output of the flip-flop 126 to assume the switching value 1.

When the Q output of flip-flop 126 has the switching value 1 leads, the Q 'output assumes the switching value 0, which causes the flip-flop 124 to reset and the flip-flop 20 is preset. By resetting the flip-flop 124, its Q output assumes the switching value 0, and the Q output of flip-flop 20 assumes the switching value 1. Meanwhile, after the rc time constant of the reset threshold circuit 144 has expired, the flip-flop 126 changes its state again, whereby the Q output assumes the switching value 0. Thereafter, the phase / frequency detector 12 operates in the same way like the conventional detector.

The above description is only of the preferred embodiment. However, there is the possibility

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add more flip-flops in cascade to by duplicating the characteristic existing above zero level 100 in the same way in the negative Direction to achieve a range expansion. One further enlargement of the area can be achieved by following the procedure described above similar procedure, additional stages can be added if necessary.

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Claims (1)

LIECK & BEDS Patent attorneys Dipl.-Irg. H.-Pe * er 1 ieok European Patent Attornays Dip '.- Ing. Jürgen Betien Maximiliansplatz Q C 1 / / OQ D-8000 Munich «089-291119 Telex 5 216 741 list d Fax 089-2915 ■ ν * · _ Technolaw 'Telegram Electropat Expectations 1. Digital phase / frequency detector circuit for detection of phase and frequency differences between an input and a reference signal; characterized by the following features: there is an input device for receiving the input (V) and the reference signal (R); a generator device generates square waves with a duty cycle that can be reset The phase and frequency difference between the input (V) and reference signal (R) corresponds and changes with each Period of phase and frequency difference repeated; a threshold device speaks to a certain, predetermined duty cycle and generates a corresponding output signal that the device for Generating square waves resets. 2. Detector circuit according to Claim 1, characterized by the following features: An integrating circuit generated by integrating the Square waves a sawtooth signal, the steepness of which corresponds to the Duty cycle corresponds to the square waves; an adding circuit adds an output of the threshold device to the maximum value of the sawtooth signal before resetting the generator device. 36H428 Detector circuit according to Claim 1, characterized by the following features: A further threshold device responding to a further specific predetermined pulse duty factor is generated a further, corresponding output signal and also resets the generator device; a further adding circuit adds an output of the further threshold device to the maximum value of another Sawtooth signal before resetting the generator device. 4th Detector circuit according to Claim 2 or 3, characterized by the following features: The integrating circuit comprises a device for Generating a positive sawtooth when the input signal (V) leads the reference signal (R), and one negative sawtooth when the input signal (V) dem Reference signal (R) lags; the threshold means comprises means for Addition of output signals that are constant for leading and lagging signals.