DE3586791T2 - INTEGRATED SEMICONDUCTOR CIRCUIT ARRANGEMENT. - Google Patents

Description

This invention relates generally to a semiconductor integrated circuit (IC) device. More particularly, the present invention relates to a semiconductor circuit technique that is effective when applied to, for example, a semiconductor memory device including a substrate bias generating stage, such as a dynamic RAM (random access memory).

For semiconductor memory devices constituted by MOSFETs (junction field effect transistors), it is known in the art to generate a substrate bias (reverse bias) by a built-in substrate bias generating stage in order to reduce the parasitic capacitance between circuit elements such as MOSFETs and a semiconductor substrate (see, for example, "Nikkei Electronics", May 14, 1979, pp. 77-79, published by Nikkei McGraw Hill Co.). When such a substrate bias generating stage is built in, a power supply voltage to be supplied to a semiconductor memory device can be uniformly a voltage of 5 V, and the number of external terminals can therefore be reduced.

However, as a result of investigations, the inventors of the present invention have found that when a circuit for rectifying the pulses continuously generated by an oscillator circuit is used in this case, the following problem occurs. A current flowing to the substrate changes greatly between the access state in which all the circuits start to operate simultaneously and the non-access state in which no internal circuit operates. Therefore, when the substrate bias by rectifying these oscillator pulses generated in no relation to the circuit operation, the power supply capability is essentially set for a "worst case" condition. This requires relatively large capacitor and rectifier elements and a drive circuit, so that the integration density of the semiconductor integrated circuit is reduced. In addition, more current is drawn. (For details of the substrate bias generating stage, see, for example, Japanese Patent Laid-Open No. 13566/1980.)

GB-A-2 111 336 and EP-A-0 118 108, the latter being cited under Article 54(3) EPC, disclose a semiconductor integrated circuit having the features set out in the first part of claim 1. In the known circuits, the substrate bias voltage is controlled in synchronism with the operation of the circuit elements included in the integrated circuit to which the substrate bias voltage is applied.

IBM Technical Disclosure Bulletin (Vol. 22, No. 7, December 1979, pp. 2765-2767) discloses a level detection circuit (threshold detector) for detecting the level of a reverse bias voltage (substrate bias voltage), in which the output signal (VOUT) of the level detection circuit controls the substrate bias voltage generator to increase the substrate bias voltage if it turns out that the substrate bias voltage level is insufficient.

It is an object of the present invention to provide a semiconductor integrated circuit in which the substrate bias voltage generating stage is additionally used to prevent an increase in leakage current due to temperature changes.

This object is achieved by the device characterized in claim 1. Invention solved.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a circuit diagram showing an embodiment of the present invention;

Fig. 2 is a circuit diagram showing an example of the substrate reverse bias generating stage of the embodiment shown in Fig. 1;

Fig. 3 is a timing chart useful for explaining the operation of the substrate reverse bias generating stage ;

Fig. 4 is a circuit diagram showing another embodiment of the present invention; and

Figs. 5 and 6 are circuit diagrams each showing another embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Example 1]

Fig. 1 is a circuit diagram showing a dynamic RAM according to an embodiment of the present invention. Each circuit element or circuit block shown in the circuit diagram is formed on a semiconductor substrate such as a single crystal silicon substrate by a previously known semiconductor integrated circuit manufacturing technique, although there is no particular limitation to this configuration. Various MOSFETs formed on the semiconductor substrate are of the enhancement type (this also applies to the other embodiments of the invention, which are described later).

A memory array MARY has a plurality of memory cells arranged in a matrix, a plurality of data lines DL, DL and a plurality of word lines. Although there is no particular limitation to this configuration, the memory array MARY has a folded bit line (data line) structure.

Each of the memory cells MC has a data storage capacitor Cs having one electrode connected to a reference point potential such as a voltage terminal of the circuit, and an address selection MOSFET Qm arranged between this capacitor Cs and the data line. Logical values "1" and "0" stored in the memory cells depend on whether a charge is stored in the capacitor.

During data readout operation, each data line DL, DL of the memory array MARY is first precharged by a precharge stage PC to a level that is essentially close to the supply voltage Vcc of the circuit. The precharge stage PC has, for example, precharge MOSFETs Qt1 and Qc2 that are connected between the data lines DL and DL, respectively, and the voltage terminal Vcc. The conduction state of these precharge MOSFETs Qc1 and Qc2 is controlled by a precharge pulse φpc. The precharge circuit PC can contain, in addition to the precharge MOSFETs Qc1 and Qc2, an equalization MOSFET that is connected between the pair of data lines DL, DL and is controlled by the precharge pulse φpc.

One of the multiple word lines WL of the memory array MARY is selected after each data line is precharged. When a particular word line is selected, the MOSFET Qm of the memory cell corresponding to the selected word line is turned on, and the capacitor Cs is connected to the data line DL or DL. Accordingly, the potential of the data line DL or DL to which the memory cell is connected changes. The potential of the data line DL or DL in this case changes depending on the amount of charge stored in the capacitor Cs. This change in potential of the data line is detected by a sense amplifier SA.

In a large-capacity memory array, each memory cell is made smaller and smaller, and a large number of memory cells are connected to the respective data lines DL, DL. Therefore, the ratio Cs/C�0 of the capacitor Cs to the stray capacitance C�0 (not shown) on the common data line DL is extremely small. This means that the signal supplied to the data line DL or DL according to the charge stored in the capacitor Cs, i.e., the signal, is extremely weak.

Although there is no particular limitation on the configuration of the embodiment, it includes a dummy cell DC for each data line in the same manner as a known dynamic RAM to detect such a weak signal. The dummy cell DC is manufactured under the same manufacturing conditions and with the same design constants as the memory cell MC, except that the capacitance of the capacitor CD of the memory cell DC is half that of the capacitor Cs of the memory cell MC. Before addressing, the capacitor CD is charged to ground potential by a MOSFET Qd which receives a timing signal φd. Since the capacitance of the capacitor CD is half that of the capacitor Cs, the capacitor CD applies a reference voltage which is substantially half that of the readout signal from the memory cell MC to the corresponding data line.

In the circuit diagram, symbol SA represents a sense amplifier which amplifies the difference of such potential changes caused by addressing within a reading period determined by timing signals (sense amplifier control signals) φpa1, φpa2. (The function of the sense amplifier will be described below). The input and output nodes of the sense amplifier are connected to a pair of complementary data lines DL and DL arranged in parallel to each other. The numbers of memory cells connected to these complementary data lines DL and DL, respectively, are made equal to each other to improve the data detection accuracy at the time of the data readout operation.

When the memory cells MC connected to one of the complementary data lines DL, are selected during addressing, a pair of dummy word lines DWL, DWL are selected so that the dummy cells connected to the other data lines are selected accordingly.

The sense amplifier SA comprises a pair of MOSFETs Q₁, Q₂ whose gates and drains are mutually connected, and amplifies a weak signal appearing on the complementary data lines DL, DL through these MOSFETs. The amplification operation is divided into two stages by a MOSFET Q₇ having a relatively small conductance and a MOSFET Q₈ having a relatively large conductance. When the MOSFET Q₇ is made conductive by a relatively fast timing signal φpa1, the amplification operation of the first stage is then initiated, and the amplification of the second stage is started at the time when the potential difference between the complementary data lines DL, DL reaches a certain value and a timing signal φpa2 is generated. In other words, when the MOSFET Q₇ is made conductive by a relatively fast timing signal φpa1, the amplification operation of the first stage is initiated, and the amplification of the second stage is started at the time when the potential difference between the complementary data lines DL, DL reaches a certain value and a timing signal φpa2 is generated. is made conductive by the timing signal φpa2, the amplification operation of the second stage is then started. The two-stage operation of the sense amplifier SA makes it possible to perform amplification free from any error concerning the potential difference between the complementary data lines DL, DL to achieve amplification at a higher operating speed. As a result of the amplification operation by the sense amplifier SA, one of the data lines of the pair of data lines is set at a potential slightly lower than the power supply voltage Vcc, while the other is set at a low potential substantially equal to the ground potential (0 V) of the circuit.

The stored data of the data cell, which is almost destroyed when the cell is addressed, is restored when the high or low level potential obtained by this reading operation is supplied as such to the memory cell MC. In other words, a stored data which has been temporarily read out is once again written into the memory cell.

An active restore circuit AR is arranged between the complementary data lines DL and DL to raise the high-level potential written in the memory cell MC to a level substantially equal to the power supply voltage Vcc of the circuit. This active restore circuit AR has the function of selectively raising only the high-level signal to the power supply voltage Vcc and does not affect the low-level signal in any way. A detailed explanation of the exact circuit structure of this active restore circuit AR is omitted here since it is not directly relevant to the essence of the present invention.

A column switch CW with MOSFETs Q₃ and Q₄ is connected between the pair of data lines DL, DL and the pair of common, complementary data lines CDL, CDL. Similarly, another column switch CW with similar MOSFETs Q₅ and Q₆ is inserted between the other pair of data lines and the pair of common, complementary data lines CDL, CDL. The input terminals of a data output buffer DOB with an output amplifier and the output terminal of a data input buffer DIB are connected to the pair of common, complementary data lines CDL, CDL.

A row decoder R-DCR and a column decoder C-DCR receive internal complementary address signals generated from address buffers R-ADB and C-ADB, and generate a select signal for selecting a word line and a dummy word line, as well as a column switch select signal to be applied to the column switches. In this way, addressing of the memory cells and the dummy cells is effected.

The operations of the address buffers R-ADB and C-ADB are controlled by timing signals Φar and Φac, respectively, and the operations of the row decoder R-DCR and the column decoder C-DCR are controlled by timing signals Φx and Φy, respectively. In other words, external address signals AX0-AXi are written into the row address buffer R-ADB in synchronism with the timing signal Φar formed based on a row address strobe signal RAS, and the internal address signals generated by the address buffer R-ADB are transmitted to the row decoder R-DCR. The address decoder R-DCR decodes the internal address signal supplied from the row address buffer ADB and sets a word line and a dummy word line to a selection level depending on a word line access timing signal φx.

External address signals AYo-AYl are read into the column address buffer G-ADB in synchronism with the timing signal Φac formed based on the column address strobe signal CAAS and are transferred to the column decoder C-DCR. The column decoder C-DCR generates a column selection signal for selecting a predetermined data line at a timing dependent on a data line selection timing signal Φy.

A timing control circuit TC receives the row address strobe signal RAS, the column address strobe signal CAS and a write enable signal WE supplied from external terminals, and generates various timing control signals required for the memory operation in addition to the timing control signals described above as typical examples.

The address buffer, address decoder and data output buffer DOB of the column system comprise static CMOS (complementary MOS) circuits, although there is no particular limitation to this configuration, in order to provide lower power consumption of the device and to perform continuous readout operation by bringing the word lines into the access state and switching the column address signals.

A substrate bias generating circuit Vbb-G is operated by a positive supply voltage of, for example, 5 V, applied between the power terminal Vcc as one of the external terminals of the integrated circuit and a reference potential terminal (or ground terminal) GND, and generates a negative bias voltage.

The bias voltage generated by the substrate bias voltage generating circuit Vbb-G is applied to semiconductor regions that act as a common substrate gate of a MOSFET Qm in the memory area and MOSFETs that form the circuit blocks shown in the drawing.

The CMOS integrated circuit of this embodiment is formed on a semiconductor substrate made of p-type single crystal silicon, but there is no particular limitation to this configuration.

Although there is no particular limitation to the following configuration, an n-channel MOSFET such as the MOSFET Qm in the memory array MARY has an n-source region and an n-drain region both formed on the surface of the semiconductor substrate, and a gate electrode formed on the surface of the semiconductor substrate between the source region and the drain region via a thin gate insulating film, and contains polysilicon. A p-MOSFET is formed in an n-well region formed on the surface of the semiconductor substrate. Thus, the semiconductor substrate forms a common substrate gate for a plurality of n-channel MOSFETs formed therein. The n-well region forms the substrate gate of the p-channel MOSFET formed therein. The substrate gate of the p-channel MOSFET, i.e., the n-well region is connected to the voltage terminal Vcc of Fig. 1.

On the main surface of the semiconductor substrate, the surface areas other than those serving as active areas, that is, the surface areas other than those where MOSFETs, MOS capacitors and semiconductor wiring areas are to be formed are covered with a relatively thick field insulating film, although the film is not shown in the drawing. The required wiring layer extends on the field insulating film or extends to the active areas via an insulating film.

With the In the structure described above, the reverse bias voltage -Vbb generated by the substrate bias voltage generating circuit Vbb-G is supplied to the common substrate gate of the n-channel MOSFETs formed on the surface of the semiconductor substrate.

The reverse bias reduces the junction capacitance formed by the pn junction between the source-drain regions of the n-channel MOSFETs and the semiconductor substrate and by the pn junction between the semiconductor wiring regions and the semiconductor substrate. Since this reduces the parasitic capacitance that limits the operating speed, the integrated circuit can operate at a higher speed.

MOSFETs such as the address select MOSFETs Qm sometimes generate a tail current or leakage current even when they are turned off. The threshold voltage of the MOSFET is appropriately increased by the substrate bias effect when the reverse bias voltage -Vbb is applied, so that the leakage current decreases. Since the leakage current of the address select MOSFET Qm is reduced, the standing time of the charge stored in the data storage capacitor Cs is relatively prolonged.

An integrated circuit structure consisting of a field insulating film and a wiring layer such as a signal wiring layer extending on the field insulating film can be considered to form part of the parasitic MOSFET structure. The reverse bias voltage -Vbb increases the threshold voltage of the parasitic MOSFET and prevents the operation of the parasitic MOSFET.

As is well known in the art, the extent of the increase in the threshold voltage of the MOSFET due to of the substrate bias effect decreases with higher substrate bias. Therefore, the threshold voltage of each n-channel MOSFET remains within a relatively narrow range when the reverse bias voltage -Vbb is generated, regardless of variations in the characteristics of the MOSFETs resulting from variations arising during the fabrication of the integrated circuit.

As will become clearer from the later description, the substrate bias generating circuit Vbb-G periodically generates the bias due to a charge pumping operation using the capacitor. The reverse bias is smoothed by the parasitic capacitance and the stray capacitance existing between the semiconductor substrate to which it is applied and the power source wiring layer, the semiconductor regions and the like.

The reverse bias voltage, which is essentially maintained by the capacitance, is lowered by a leakage current that occurs between the source-drain region of a MOSFET and the semiconductor substrate.

Here, the leakage current to the semiconductor substrate is not always constant, but is affected by the circuit operation. This leakage current is relatively small as long as the switching state of a MOSFET remains unchanged and is fixed or kept stationary. Conversely, when the switching state of a MOSFET changes, the leakage current is increased by this change. For details regarding the mechanism of occurrence of the leakage current to the substrate, refer to "Physics of Semiconductor Devices", pages 480-487 by S. M. Sze, published by John Wiley & Sons, 1981.

In the dynamic RAM shown in Fig. 1, the substrate leakage current increases when the timing control circuit TC, the Address buffers, decoders, sense amplifiers and the like operate based on the row address strobe signal RAS, the column address strobe signal CAS and the like.

According to this embodiment, the substrate bias generating circuit Vbb-G has a relatively large driving capacity so that it can maintain the substrate bias potential at an appropriate value even if the substrate bias current increases. The circuit Vbb-G is also designed to have lower power consumption characteristics.

Although not particularly limited to the following configuration, the substrate bias voltage generating circuit Vbb-G of this embodiment has a circuit portion exhibiting steady-state operation and a circuit portion exhibiting intermittent operation in terms of the driving capacity and the power consumption. The circuit portion exhibiting steady-state operation is provided with such a driving capacity that, when each circuit shown in Fig. 1 is substantially in the non-operating mode, it can maintain the reverse bias voltage -Vbb at a desired value.

The circuit part that implements the intermittent operation is provided with a relatively large driver capacitance so that the reverse bias voltage can be maintained at desired values even if the substrate leakage current increases.

A level detector circuit VLD, as shown in Fig. 1, is provided to control the operation of the circuit part exhibiting the intermittent operation. The level detector circuit VLD detects the reverse bias voltage Vbb and generates a signal for operating the circuit part with intermittent operation when the reverse bias voltage is lower than a desired level.

Although there is no particular limitation on the following configuration, the operation of the intermittent operation developing circuit part in the substrate bias generating circuit in this embodiment is also controlled by a relatively high-speed row system control signal RAS1 generated by the timing control circuit TC based on the external control signal RAS.

This structure makes it possible to obtain the following circuit operations.

When the access of the dynamic RAM in this embodiment is started by the row address strobe signal RAS, the circuits shown in the drawing start to operate in response, and therefore the substrate leakage current increases. The level of the reverse bias voltage -Vbb becomes smaller as the substrate leakage current increases. In this case, the reverse bias voltage is adjusted in such a way that it returns to the desired level through a feedback path consisting of the level detector circuit VLD and the circuit part exhibiting the intermittent operation, which is done even when the operation control of the substrate bias voltage generating circuit by the control signal RAS1 is not present. In this case, however, the time required until the reverse bias voltage returns to the desired level becomes somewhat long and depends on the speed change of the output signal of the circuit part exhibiting the intermittent operation.

Conversely, when the control signal RAS₁, ie a control signal which is under the conditions generated by the timing control circuit TC, Row system control signals having a faster timing is used in this embodiment, the operation of the circuit part having an intermittent operation can be started at a timing substantially coincident with the timing at which the substrate leakage current is drastically increased. As a result, a drastic level change of the reverse bias voltage can be prevented.

When the intermittent operation circuit part of the substrate bias voltage generating circuit Vbb-G is controlled by a control signal such as the control signal RAS1, the level detection circuit VLD may be omitted. However, in this case, the following must be taken into account.

It is preferable that the reverse bias voltage can change from 0 volts to the desired level within a relatively short period of time after the power source is turned on. In order to speed up the generation of the reverse bias voltage when the power source is turned on, it is necessary that the circuit part having the intermittent operation in the substrate bias voltage generating circuit Vbb-G is also operated. For this purpose, the row address strobe signal for carrying out the dummy operation cycle must be supplied to the external terminal RAS at the same time that the power is turned on.

When the detection output of the level detection circuit VLD is used, the circuit part exhibiting the intermittent operation is immediately operated by the detection output so that the reverse bias voltage is changed to the predetermined level within a relatively short period of time after the time of turning on the power source, regardless of whether a signal is supplied to the external terminal RAS.

If the output signal of the level detection circuit VLD is not used, the level of the reverse bias voltage may be undesirably reduced due to the increase in the substrate leakage current resulting from an increase in the operating temperature of the integrated circuit.

Fig. 2 is a circuit diagram showing an example of the substrate bias generating circuit Vbb-G together with that of the above-described level detecting circuit VLD. In this circuit diagram, those MOSFETs provided with straight lines between their sources and drains are of the p-channel type, while those MOSFETs shown with the usual symbols are of the n-channel type.

In this embodiment, there are two types of substrate reverse bias generating circuits, namely, a substrate bias generating circuit Vbb-G1 which forms the circuit part with steady-state operation, and a substrate bias generating circuit Vbb-G2 which forms the circuit part with intermittent operation. The stationary reverse bias generating circuit Vbb-G1 has an oscillator stage OSC2, CMOS inverter stages IV4, IV5 for signal shaping and for amplifying the output signal of the oscillator stage, and a rectifier stage.

The oscillator stage OSC2, for example, has a ring oscillator that is operated with the supply voltage Vcc and has several CMOS interstages that are connected to one another in a ring shape.

The rectifier stage comprises a charge pump capacitor C2 and MOSFETs Q₂�0, Q₂₁ whose gate electrodes are connected to their drain electrodes (which operate either as drain electrodes or as source electrodes, depending on the polarity of the voltage applied to them, but referred to herein as drain electrodes) so that the transistors operate as rectifying elements. Although there is no particular limitation to the following configuration, the capacitor C2 has a MOS capacitor structure similar to the structure of the n-channel MOSFET. In other words, one of the electrodes of the capacitor, which should correspond to the gate electrode of the MOSFET, is connected to the output terminal of the CMOS inverter stage IV₅ as an output buffer. The other of the electrodes of the capacitor C₂, that is, the electrode which should correspond to the source or drain electrode of the MOSFET, is connected to the common connection point between the MOSFETs Q₂₀ and Q₂₁.

The MOSFET Q₂�0 acting as a rectifying element is connected between the other electrode of the capacitor C₂�0 and the ground point GND of the circuit, and the MOSFET Q₂₁ is arranged between the other electrode of the capacitor C₂ and the semiconductor substrate.

A parasitic capacitance Csb (not shown), which essentially maintains the reverse bias, is present between the substrate and the ground point of the circuit.

The diode-connected MOSFET Q₂₀ is turned on when the oscillator generated by the inverter stage IV5 is at a high level in the pulse (essentially at the level of the supply voltage Vcc), and the capacitor C₂ is precharged by the output high level. Subsequently, when the output pulse is at a low level (essentially at the level of the ground potential of the circuit), the other electrode of the capacitor C₂ is at a negative potential with the value - (Vcc-Vth). Here, the symbol Vth represents the threshold voltage of the MOSFET Q₂₀. The MOSFET Q₂₁ in diode connection is turned on by this negative potential and transfers the negative potential to the above-described parasitic capacitance Csb. Therefore, the substrate bias voltage -Vbb is applied to the substrate. The substrate bias voltage generating circuit Vbb-G1 for stationary operation has a relatively small power supply capacity so that when the above-described RAM is in the non-chip select state, it can compensate for the leakage current flowing through the substrate.

The power supply capacity of the substrate bias voltage generating circuit Vbb-G1 for steady state operation is mainly determined by the capacitance of the capacitor C2 and the oscillation frequency of the oscillator stage OSC. In other words, the amount of charge injected into the semiconductor substrate upon one oscillation becomes larger as the capacitance of the capacitor C2 increases. The number of charge injections into the semiconductor substrate per unit time becomes larger as the oscillation frequency of the oscillator stage OSC2 increases.

According to this embodiment, the substrate bias voltage generating circuit for stationary operation is constructed in such a manner that it has the low power consumption characteristic while ensuring the capacity for the required supply of a relatively small current. The oscillation frequency of the oscillator stage OSC2 is set to a relatively low value, such as 1 or 2 MHz, by selecting an appropriate number of CMOS inverter stages constituting the oscillator circuit and setting their signal delay characteristics to appropriate values.

Here, the power consumed by the oscillator circuit OSC₂ is proportional to the oscillation frequency. The operating current or the current of each element forming the oscillator circuit OSC₂ is The current consumed by each CMOS inverter stage is proportional to a so-called "transition current" required for charging and discharging the load capacitance (consisting of wiring capacitance, input capacitance of inverter circuits of the post-stage, and the like) connected to the output of each inverter stage in the same manner as in the well-known CMOS inverter stage, and is substantially zero in the steady-state operation in which the output or input signal of each inverter is at a high or low level. Since the transient current of each CMOS inverter stage is proportional to the operating frequency, the power consumption of an oscillator circuit OSC₂ with a low oscillation frequency is low.

In this embodiment, the driving capacitance of the CMOS inverter stage IV₅ acting as an output buffer for driving the rectifier stage can be relatively small because the capacitor C₂ is relatively small. Therefore, the p- and n-channel MOSFETs (not shown) constituting this CMOS inverter stage IV₅ do not need to have a low on-resistance and can therefore be small. The p- and n-channel MOSFETs (not shown) constituting the CMOS inverter stage IV₄ as a signal shaping stage only need to drive a load with relatively small capacitance because the MOSFETs constituting the CMOS inverter stage IV₅ are small. Therefore, the MOSFETs constituting the CMOS inverter stage IV₄ can be small.

The substrate bias voltage generating circuit Vbb-G2 for intermittent operation comprises a controllable oscillator circuit, i.e., an oscillator circuit OSC₁ capable of performing intermittent operation, a CMOS inverter stage IV₂ as a signal shaping circuit, a CMOS inverter stage IV₃ as an output buffer, and a rectifier stage.

The oscillator stage OSC₁ has CMOS NAND gate stages G₂ to G₄. The output terminals of these gate stages G₂-G₄ are connected to one of the input terminals of a gate stage of the subsequent stage. The output terminal of the gate stage G₄ of the final stage is connected to one of the input terminals of the gate stage G₂ of the input stage. The other input terminal of each of the gate stages G₂-G₄ is considered to be a common operation control terminal and it is connected to the output terminal of the gate stage G₁.

Each of the gate stages G2-G4 constituting the oscillator circuit OSC1 operates substantially as an inverter when the control signal supplied to the operation control terminal is at a high level (logic "1") such as one substantially equal to the power source voltage Vcc. Therefore, the oscillator circuit OSC1 performs the oscillation operation as a ring oscillator. When the control signal is at a low level (logic "0") such as one substantially equal to the ground potential, the output signal of each of the gate stages G2-G4 is maintained at the high level substantially equal to the power source voltage Vcc.

The rectifier stage comprises a capacitor C₁ and MOSFETs Q₁₈, Q₁₉, as shown in the drawing.

When the oscillator circuit OSC₁ is activated by the high level at the control input, the rectifier stage comprising the capacitor C₁ and the MOSFETs Q₁₈, Q₁₉ is activated in response to the former, and the charge for applying a reverse bias is injected into the semiconductor substrate. The reverse bias in this case is determined by the substrate bias generating circuit Vbb-G1, which is in continuous operation together with the substrate bias generating circuit Vbb-G2.

When the oscillator circuit OSC₁ is disabled by the low level at the control input, the rectifier stage comprising the capacitor C₁ and the MOSFETs does not operate. In this case, the output signal of the CMOS inverter stage IV₃ is maintained at the high level, which is substantially equal to the supply voltage Vcc, by the high level output signal of the oscillator circuit OSC₁. The capacitor C₁ is maintained in the charged state by the high level output signal of the inverter IV₃. This structure makes it possible to inject charges into the substrate at an early stage when the oscillator circuit OSC₁ starts operating.

The CMOS NAND gates G2-G4 constituting the oscillator circuit OSC1 do not consume any current as long as they operate in the steady state mode, in the same way as the CMOS inverter stage. Therefore, the power supplied by the substrate bias voltage generating circuit Vbb-G2 for intermittent operation is substantially zero during the period in which the oscillator circuit OSC1 stops operating.

The intermittently operating substrate blocking voltage generating circuit Vbb-G2 is required to have a relatively large power supply capacity so that it can compensate for a relatively large leakage current flowing into the substrate when the RAM is in the operating state. Therefore, the capacitance of the capacitor C₁ is relatively large while the oscillation frequency of the oscillator circuit OSC₁ is relatively high, such as from 10 to 15 MHz.

The p- and n-channel MOSFETs (not shown) forming the CMOS inverter stage IV₃ are relatively large, since the rectifier stage forms a relatively large load. The p- and n-channel MOSFETs (not shown) forming the CMOS inverter stage IV₂ are relatively large, so that they form the CMOS inverter stage IV₃ can be driven sufficiently.

This embodiment includes a level detector circuit VLD with MOSFETs Q₁₀-Q₁₇ and CMOS inverter stages IV₀, IV₁ and a control circuit with the CMOS NAND gate stage G₁ to operate the substrate bias generating circuit Vbb-G2 only when its operation is required.

The level detection circuit VLD is provided to positively detect an excessive substrate reverse bias voltage -Vbb beyond a predetermined level, which is required for high-speed operation of the RAM. In the level detection circuit VLD, the ground potential of the circuit is always applied to the gate of the p-channel MOSFET Q₁₀ so that the transistor serves as a constant current load. In other words, the MOSFET Q₁₀ is always on. A p-channel MOSFET Q₁₁ for clamping the level is connected in series with this MOSFET Q₁₀. Since the ground potential of the circuit is always applied to the gate, this MOSFET Q₁₁ is always kept on. Therefore, the source potential of the MOSFET Q₁₁, i.e. the potential of the electrode connected to the drain of the MOSFET Q₁₀ is at a level at least higher than the ground potential of the circuit, and the drain potential is substantially equal to the ground potential of the circuit. MOSFETs Q₁₂-Q₁₄ in diode connection are connected in series between the drain of the MOSFET Q₁₁ and the substrate (-Vbb).

Therefore, the detection level of the level detector circuit VLD is substantially equal to the sum 3Vth of the threshold voltages Vth of the three series-connected MOSFETs Q₁₂ to Q₁₄. When the substrate reverse bias voltage -Vbb is at a level lower than the total threshold voltage 3Vth of the three transistors Q₁₂-Q₁₄ in diode connection, these transistors are turned off. In this case, the potential at the junction between the MOSFETs Q₁₁ and Q₁₀ is at a high level like that of the power supply voltage Vcc. When the substrate reverse bias voltage -Vbb is at a level higher than the total threshold voltage 3Vth of the MOSFETs Q₁₂-Q₁₄ in diode connection, these transistors Q₁₂-Q₁₄ are turned on. In this case, the potential at the junction between the MOSFETs Q₁₁ and Q₁₀ is at a low level higher than the ground potential of the circuit by the threshold voltage Vth of the MOSFET Q₁₁. In this case, the current flowing into the substrate from the power supply voltage terminal Vcc inevitably lowers the substrate reverse bias voltage -Vbb.

The conductance of the load MOSFET Q₁₀ is set to an extremely low value in order to minimize the current flowing through the level detector circuit into the substrate and to sufficiently reduce the low level appearing at the junction between the MOSFETs Q₁₀ and Q₁₁. In other words, the conductance is set to an extremely small value so that the MOSFET Q₁₀ allows only a small current to flow.

The high and low levels of the detector output as described above are judged by a CMOS inverter stage constituted by a p-channel MOSFET Q₁₅ and an n-channel MOSFET Q₁₆. The inverter stage comprising the MOSFETs Q₁₅ and Q₁₆ together with a MOSFET Q₁₇ and a CMOS inverter stage IVo constitutes a Schmidt circuit (hysteresis circuit) to achieve a high-speed change in the detection output and, in particular, to quickly operate the oscillation circuit OSC₁ when the reverse bias voltage is reduced; however, there is no particular limitation to this configuration. In other words, the output of the inverter stage comprising the MOSFETs Q₁₅ and Q₁₆ is applied to the input of the CMOS inverter stage IVo which has a similar structure. The output of this CMOS inverter stage IVo is applied to the gate of the p-channel MOSFET Q₁₇ connected between its input and the power supply voltage Vcc, thereby causing in-phase feedback. When the low-level detection output is formed, the detection signal generated by the inverter stage IVo is changed to the low level at high speed. The detection output generated by this inverter stage IVo is applied to one of the output terminals of the CMOS NAND gate stage G₁ through the CMOS inverter stage IV₁. The internal row address strobe signal RAS₁ formed by the timing control circuit TC shown in Fig. 1 is applied to the input of the CMOS inverter stage IVo. is fed to the other input terminal of this NAND gate stage G₁. The output signal of this NAND gate stage G₁ is fed together to the other input terminals of the NAND gate stages G₂-G₄ which form the ring oscillator OSC₁ described above.

Next, the operation of the circuit of this embodiment will be described with reference to the timing chart of Fig. 3.

When the RAM is in the chip unselected state or when the internal address strobe signal RAS₁ is at a high level, the output of the gate stage G₁ is responsive to the detection output of the level detector circuit VLD.

In this chip-unselected state, if the absolute value of the substrate reverse bias voltage -Vbb is smaller than the total threshold voltage 3Vth of the three MOSFETs Q₁₂ to Q₁₄ described above, the transistors are turned off, and accordingly, the detection output signal is at the high level. Therefore, the detection output signal supplied to the NAND gate stage G₁ is at the low level (logic "0"), and the output signal of the NAND gate stage G₁ is at the high level (logic "1"), whereby the oscillator circuit OSC₁ is in the oscillation state. The absolute value of the substrate reverse bias voltage is increased by the rectifier stage which receives the output pulses of the oscillator circuit. When the substrate reverse bias voltage -Vbb exceeds the total threshold voltage 3Vth, the MOSFETs Q₁₂-Q₁₄ are turned on so that the detection output signal is at the low level, whereupon the detection output signal supplied to the NAND gate stage G₁ is at the high level (logic "1"). Since the output of the NAND gate stage G₁ falls to the low level (logic "0") in response to the previous signal, the outputs of all the NAND gate stages G₁ - G₄ that form the oscillator circuit OSC rise to the high level (logic "1"). In other words, the oscillation ends.

Since the oscillation stops, the operation of the rectifier stage (C₁, Q₁₈, Q₁₉) also stops. Since the high-power consuming oscillator circuit and the rectifier stage stop operating, low power consumption can be achieved. Besides, since the substrate reverse bias voltage is at a low level or close to the ground potential immediately after the power is turned on, the operations of the two substrate reverse bias voltage generating circuits can quickly raise the absolute value of the substrate reverse bias voltage to the desired level.

When the row address strobe signal RAS falls to the low level, indicating a chip select, the internal signal RAS₁ is then lowered to the low level, so that the output of the NAND gate stage G₁ rises to the high level (logic "1") regardless of the detection output of the level detector circuit described above. When the RAM performs write/read operations and the like, the oscillator circuit OSC₁ is unconditionally operated. This is to prevent a drastic drop in the absolute value of the substrate reverse bias voltage -Vbb caused by a relatively large substrate leakage current, which occurs when RAM operations as described above are started. If the oscillator circuit OSC₁ is preliminarily operated before the RAM is operated, as in this embodiment, it becomes possible to prevent the drastic drop in the substrate reverse bias voltage -Vbb.

[Example 2]

Fig. 4 is a circuit diagram showing a dynamic RAM according to the second embodiment of the invention. The circuits not shown in Fig. 4 are substantially the same as those shown in Fig. 1.

The RAM in this embodiment includes a refresh control circuit REFC and a multiplexer MPX to perform automatic refresh of memory cells.

The refresh control circuit REFC includes a refresh timer and a refresh address counter, which are not shown.

The refresh timer is operated when the row address strobe signal RAS is raised to the high level and the refresh control signal REFH is lowered to the low level, that is, when refresh operation is performed in the non-selected state. chip and periodically generates refresh control signals Φref during its operation.

The refresh address counter receives the control signals generated by the refresh timer as advance pulses and forms refresh address signals axo to axi.

The operation of the multiplexer MPX is controlled by the control signal Φref. The multiplexer MPX selects the internal address signals axo to axi generated by the address buffer R-ADB when the control signal Φref is not generated, and selects the refresh address signals axo' to axi' when the control signal Φref is generated.

The timing control circuit TC generates various timing signals similar to those in the first embodiment in response to the row address strobe signal RAS, the column address strobe signal CAS and the like supplied from the external terminals in the same manner as in the first embodiment. However, this embodiment is slightly different from the first embodiment in that the internal circuit of the timing control circuit TC is constructed in such a manner as to respond to the refresh control signal φref. When the refresh control signal φref is generated, the timing control signal TC controls the operation of the row system circuits, i.e., the row address decoder R-DCR, the precharge circuit PC, the sense amplifier SA and the active restore circuit AR, as shown in Fig. 1, in response to the refresh control signal.

In this structure, refresh operation is effected whenever the refresh control signal φref is generated. In other words, when the refresh control signal φref is generated, the refresh address signals axo to axi of the refresh address counter to the row address decoder R-DEC of Fig. 1 via the multiplexer MPX in response to the refresh control signal Φref. The control signal Φref actuates the timing control circuit TC, and the row system timing signals generated by the timing control circuit TC in turn sequentially actuate the precharge circuit PC, the row address decoder R-DCR, the sense amplifier SA and the active restore circuit AR of Fig. 1. As a result, the word line corresponding to the refresh address is selected, and the data stored in the memory cell connected to the selected word line is refreshed.

The substrate bias voltage generating circuit Vbb-G and the level detecting circuit VLD of this embodiment are substantially the same as those of Fig. 2.

In this embodiment, a logic synthesis circuit comprising a CMOS gate stage G5 and CMOS inverter stages IV6 and IV7 is provided so that the operation of the substrate bias generating circuit Vbb-G is also controlled by the refresh control signal φref. The output of this logic synthesis circuit is set to a low level at the time of chip selection (period in which the row address strobe signal RAS is at a low level) and at the time of the refresh operation.

The intermittent operation circuit part within the substrate bias generating circuit Vbb-G is synchronously operated when the substrate leakage current is increased by executing the refresh operation, that is, when the timing control circuit TC and the row system circuits are operated by the refresh control signal φref.

If battery support of a dynamic RAM is required, a voltage source device PS for forming a predetermined DC voltage from, for example, a conventional AC power source, and a series circuit comprising a battery E and a diode D is connected between the external terminal Vcc and GND. When the power source device PS is turned off, the supply voltage required by the RAM to hold the information or data is supplied from the battery E.

In the dynamic RAM of this embodiment, in particular, the refresh operation at the time of battery backup is automatically carried out without requiring any external control signals. Therefore, the RAM does not require the operation of other external devices at the time of battery backup.

Since low power consumption can be achieved by the substrate bias voltage generating circuit Vbb-G, the power consumption of the dynamic RAM of this embodiment can be lowered as a whole. Therefore, the battery life can be extended in battery backup.

[Example 3]

Fig. 5 is a circuit diagram showing a level detector circuit VLD and a substrate bias generating circuit according to still another embodiment of the invention.

The level detector circuit VLD comprises a p-channel MOSFET Q₂₆, n-channel MOSFETs Q₂₇-Q₂₇, and a CMOS inverter stage IV₁₀, as shown in the drawing. The substrate gate of the MOSFET Q₂₆ is connected to the voltage terminal Vcc in the same manner as in the previous embodiments. The substrate gates of the MOSFETs Q₂₇-Q₂₉ are made of the p-type semiconductor substrate.

The detection output signal VD of the level detector circuit VLD is set to a high level substantially corresponding to the level Vcc or to a low level substantially corresponding to 0 V depending on the level of the reverse bias voltage -Vbb, which is carried out in the same manner as in the previous embodiments.

The CMOS NAND gate stage G6 receives the detection output signal VD of the level detector circuit VLD and the control signal VCN1. The control signal VCN1 is generated, for example, by an inverter stage IV7 shown in Fig. 4. The output signal of the gate stage G6 is supplied to the substrate bias voltage generating circuit Vbb-G.

The substrate bias voltage generating circuit Vbb-G comprises the common oscillator circuit OSC, a CMOS inverter stage IV8 acting as a signal shaping circuit, a CMOS NAND gate stage G7, a CMOS inverter stage IV11, CMOS inverter stages IV9 and IV12 as buffer amplifiers, and rectifier stages CPC1 and CPC2.

Since the output signal of the CMOS inverter stage IV�8 is fed directly to the input of the CMOS inverter stage IV�9, the latter generates stationary pulse signals. As a result, the rectifier stage CPC�1 is operated stationary.

The output signal of the CMOS inverter stage IV₈ is fed to the input of the CMOS inverter stage IV₁₂ via the gate stage G₇ and the CMOS inverter stage IV₁₁. Therefore, the output pulses of the CMOS inverter stage IV₁₂ are intermittent. The rectifier stage CPC₂ is therefore operated intermittently depending on the output signal of the inverter stage IV₁₂.

The power supply capacity of the rectifier stage CPC₁, which has steady-state operation for the semiconductor substrate can be small, as in the previous embodiments. Therefore, the charge pump capacitor C₃ can also be relatively small.

The charge pump capacitor in the rectifier stage CPC₂, which has the intermittent operation, is relatively large.

Although there is no particular limitation to the following configuration, the capacitors C3 and C4 are formed in an n-type region (not shown) formed on the surface of the p-type semiconductor substrate, and have a structure similar to that of the p-channel MOSFET. The n-well region in which these capacitors C3 and C4 are formed is maintained at the potential of the circuit power terminal Vcc, for example. This structure is somewhat advantageous for reducing the substrate leakage current.

In this embodiment, the oscillator circuit OSC is common to the rectifier stages CPC₁ and CPC₂. As already described, the bias current supplied to the semiconductor substrate is associated with the operating frequency of the rectifier stage. The oscillation frequency of the oscillator circuit OSC is determined by the power supply capacity provided by the rectifier stage CPC₁ for steady-state operation and by the power supply capacity provided by the rectifier stage CPC₂ for intermittent operation. Therefore, the lower limit of the oscillation frequency of the oscillator circuit OSC is somewhat limited in comparison with that of the oscillator circuit OSC₂ for steady-state operation as shown in Fig. 2.

However, this embodiment does not include an oscillator circuit that itself consumes power during operation, such as the oscillator circuit OSC1 shown in Fig. 2 for intermittent operation.

Therefore, the number of required circuit elements can be reduced. In addition, the average power consumption of the RAM as a whole can be sufficiently reduced even if the power consumed by the common oscillator circuit OSC is slightly larger than that of, for example, the oscillator circuit OSC2 shown in Fig. 2.

[Example 4]

Fig. 6 is a circuit diagram of a substrate bias voltage generating circuit Vbb-G according to still another embodiment of the present invention.

The substrate bias voltage generating circuit Vbb-G of this embodiment includes the oscillator circuit OSC, a CMOS inverter stage IV13 serving as a signal shaping circuit, a CMOS NAND gate stage G8, CMOS inverter stages IV14 and IV16, CMOS inverter stages IV15 and IV17 acting as buffer amplifiers, charge pump capacitors C5 and C6, and n-channel MOSFETs Q35 to Q38 as rectifying elements.

When the control signal VCN₂ generated in combination with the detection output of the level detector circuit and the control signal of the dynamic RAM as in the previous embodiment is at low level, the circuit operation is as follows.

The output signals of the gate stage G�8 and the inverter stage IV₁₇ are independent of the output signal of the oscillator circuit OSC is at high level. The capacitor is in the charging state by the high level output signal of the inverter IV₁₇.

The output of the inverter IV₁₅ is charged to a high or low level depending on the output of the oscillator circuit OSC. In this state, the rectifier stage comprising the capacitor C₅ and the MOSFETs Q₃₇ and Q₃₈ is operated and the reverse bias voltage -Vbb is then supplied to the semiconductor substrate. The MOSFET Q₃₅ is kept essentially in the off state because the maximum positive potential level appearing at the node N₁ is clamped by the MOSFET Q₃₇ as a rectifying element.

When the control signal VCN₂ is at high level, the circuit operation is as follows.

When the output of the inverter stage IV₁₃ is raised to a high level in response to the output of the oscillator circuit OSC, the output of the inverter stage IV₁₅ is then raised to a high level substantially corresponding to the power supply voltage Vcc, while the output of the inverter stage IV₁₇ is lowered to a low level substantially corresponding to 0 V. Since the capacitor C₆ is precharged, the node N₂ is set to a negative potential when the output of the inverter stage IV₁₇ is lowered to the low level. Since the node N₂ is accordingly at a negative potential, the MOSFET Q₃₅ acting as a rectifier element is turned on. As a result, the negative potential formed by the capacitor C₆ is applied to the node N₁ via the MOSFET Q₃₅. The capacitor C₅ is supplied by the high level formed by the inverter stage IV₁₅ and by the signal connected to the node N₁. is charged to such a high level that the supply voltage Vcc is exceeded. In other words, the capacitor C6 is essentially operated as a bootstrap capacitor and the charging voltage of the capacitor C5 is the gain level.

Subsequently, when the output of the inverter stage IV₁₃ is lowered to the low level, the output of the inverter stage IV₁₅ is then lowered to the low level, which is substantially equal to 0 V. Since the capacitor C₅ is precharged to the boost level, the node N₁ is set to a large negative potential upon the fall of the output of the inverter stage IV₁₅ to the low level. The potential of this node N₁ is supplied to the semiconductor substrate via the MOSFET Q₃₈. The output of the inverter stage IV₁₇ is raised to a high level, which is substantially equal to the supply voltage, in response to the low level output of the inverter stage IV₁₅. The MOSFET Q₃₆ is turned on by the positive potential supplied to the node N₂ via the capacitor C₆. As a result, the capacitor C₆ is recharged.

The operations described above are repeated depending on the change in the output signal of the inverter stage IV₁₃. As a result, a large bias current is supplied in the semiconductor substrate during a period in which the control signal VCN₂ is at a high level.

According to this embodiment, the two inverter stages IV₁₅ and IV₁₇ having relatively high driving capacity are operated to complement each other, so that the transient current flowing through the power supply wiring within the RAM can be reduced, thereby suppressing noise in the power supply wiring can be reduced.

[Effects]

(1) The operations of the oscillator circuit for forming the reverse bias voltage and the rectifier stage are selectively stopped by monitoring the level of the reverse bias voltage, so that the consumption of substantially wasted power can be restricted. As a result, lower power consumption of a semiconductor integrated circuit device having a built-in substrate reverse bias voltage generating circuit can be achieved.

(2) The present invention arranges a substrate reverse bias generating circuit having only a small power supply capacity which compensates for a leakage current in periods of non-selection and another substrate reverse bias generating circuit which is selectively operated by a level monitor output signal for the substrate reverse bias. Moreover, the invention invalidates the monitor output signal when the internal circuits are operated. With this arrangement, a substrate reverse bias of a substantially constant level can be formed with reduced power consumption.

(3) Thanks to the effects (1) and (2), the power consumption of the substrate bias voltage generating circuit can be reduced, so that the service life of a battery in battery backup operation can be extended.

(4) A level limiting operation by the p-channel MOSFETs whose gates are supplied with the ground potential of the circuit and by the n-channel MOSFETs in diode connection can limit the level of a negative voltage with respect to the Determine the ground potential as a reference value, whereby essentially the positive supply voltage Vcc alone is used, with a simple circuit design.

Although the invention has been clearly described in this way with reference to some preferred embodiments thereof, it is not particularly limited thereto, but can of course be modified or changed in various ways without departing from the essence thereof. For example, in such semiconductor devices having integrated circuits which are operated by chip select signals, such as RAMs, the substrate reverse bias monitor output signal can be invalidated by the chip select signal instead of the internal control signal RAS1 in the circuit of the embodiment shown in Fig. 2. The oscillator circuit which is operated in a stationary manner by switching on the supply voltage and its rectifier stage are essentially not required.

The circuit structure in which the substrate bias generating circuit is divided into the steady-state operation circuit part and the intermittent operation circuit part is desirable from the viewpoint of avoiding an undesirable increase in the sizes of circuit elements constituting the intermittent operation circuit part. However, if necessary, the small power supply capacity circuit and the large power supply capacity circuit may be selectively operated. A plurality of intermittent operation circuit parts may be arranged and individually controlled.

In the invention, the term "substrate" of the "substrate bias voltage generating circuit" means a semiconductor region such as the substrate gate of a field effect element, but it shall not mean only a semiconductor substrate. For example, when a memory cell is formed in a p-well region formed in the surface of an n-type semiconductor substrate in order to reduce the soft error (error due to foreign matter) of the memory resulting from α-rays, and when the reverse bias voltage is applied to the p-well region, the term "substrate" means the p-well region.

In addition to using the dummy cells, the reference voltage for reading out the memory cells constituting the dynamic RAM can be generated by short-circuiting the complementary data lines which are at high and low levels in the high impedance state without using dummy cells. The reference voltage in this case is at an intermediate level. Various other circuit configurations can also be used. For example, peripheral circuits such as the address buffers, the address decoders and the like can be formed by static CMOS circuits. The X and Y address signals can be supplied from mutually independent external terminals, and a detector circuit for detecting the change timing of the address signal is arranged to generate various timing signals as required for the operations of the internal circuits.

In addition to the above-described semiconductor memories such as dynamic RAMs and static RAMs, the present invention can be widely applied to semiconductor integrated circuit devices equipped with a built-in substrate bias generating circuit.

Claims (20)

1. Integrated semiconductor circuit arrangement comprising a first circuit with insulated gate field effect transistors (Qm) having a common substrate region to which a substrate bias voltage (-Vbb) is applied, the operation of the first circuit being controlled by a control signal (RAS1), and a circuit (Vbb-G) for generating the substrate bias voltage (-Vbb), the current output capacitance of the circuit (Vbb-G) generating this bias voltage being changed during the period in which the first circuit is in operation, based on the control signal (RAS1), characterized in that a level detector circuit (VLD) is provided for detecting the level of the substrate bias voltage (-Vbb), the current output capacitance also being changed based on the detection signal of the level detector circuit (VLD), and that the circuit generating the substrate bias voltage (Vbb-G) comprises a first rectifier stage which delivers this bias voltage and has a capacitor (C1) and several rectifier elements (Q18, Q19) as well as a control circuit (G1) for controlling pulse signals which are fed to the first rectifier stage as a function of the output signal of the level detector circuit (VLD) and the control signal (RAS1). 2. Arrangement according to claim 1, wherein the substrate bias generating circuit (Vbb-G) comprises a periodic pulse signal receiving second rectifier stage with a capacitor (C2) and several rectifier elements (Q20, Q21). 3. Arrangement according to claim 2, wherein the pulse signal to be supplied to the first rectifier stage is set to such a level that the capacitor (C1) of the first rectifier stage comes into a precharge state when the control signal (RAS1) is at such a level that the first circuit is not in operation. 4. Arrangement according to claim 2 or 3, wherein the substrate bias voltage generating circuit (Vbb-G) comprises a first oscillator circuit (OSC2) for generating pulse signals to be supplied to the second rectifier stage and a second oscillator circuit (OSC1) whose operation is controlled in dependence on a control signal generated by the control circuit (G1) and generates the pulse signals for supply to the first rectifier stage. 5. Arrangement according to claim 4, wherein the second oscillator circuit (OSC1) comprises a ring oscillator which forms a feedback loop based on the control signal (RAS1). 6. Arrangement according to claim 4 or 5, wherein the control circuit (G1) generates the operating control signal in order to set the second oscillator stage (OSC1) in operation as a result of this during the period in which the first circuit is in operation as well as during the period in which the detection signal is generated. 7. Arrangement according to claim 6, wherein the level detector circuit (VLD) comprises a level shift stage (Q10...Q14) which, upon receipt of the substrate bias voltage (-Vbb), generates an output voltage which is level-shifted with respect to the same, and a level discriminator stage (Q15...Q17, IVo) which receives the output signal of the level shift stage. 8. Arrangement according to claim 7, wherein the level shift stage comprises a plurality of level shift elements (Q12...Q14), each of which Insulated gate field effect transistor in diode connection, these transistors being in series, and a bias element (Q10, Q11). 9. Arrangement according to claim 7 or 8, wherein the level discriminator stage comprises a hysteresis circuit (Q15...Q17, IVo). 10. Arrangement according to one of claims 4 to 9, wherein the oscillator frequency of the first oscillator circuit (OSC2) is lower than that of the second oscillator circuit (OSC1). 11. Arrangement according to one of claims 1 to 4, wherein the first circuit comprises a memory (MARY) whose operation is controlled by the control signal (RAS1). 12. Arrangement according to claim 11, wherein the memory (MARY) comprises a dynamic random access memory and the control signal (RAS1) is a chip selection signal (RAS1). 13. Arrangement according to claim 12, wherein the dynamic random access memory (MARY) is put into operation at the time of chip selection determined by the chip selection signal (RAS1) and at the time of a refresh process determined by a refresh control signal (Φref), and wherein the control circuit (G1) generates the operating control signal which puts the second oscillator circuit (OS1) into operation on the basis of the chip selection signal (RAS1) and the refresh control signal (Φref) synchronously with the operating state of the dynamic random access memory. 14. The arrangement according to claim 13, wherein the control circuit (G1) generates the operation control signal to operate the second oscillator circuit (OSC1) during the period in which the dynamic random access memory (MARY) is in operation due to the chip selection signal (RAS1) and the refresh control signal (Φref), as well as during the period in which the detection signal from the level detector circuit (VLD) into operation. 15. Arrangement according to claim 2, wherein the substrate bias generating circuit (Vbb-G) comprises a common oscillator circuit (OSC) for generating pulse signals to be supplied to the first and second rectifier stages (CPC2, CPC1), the control circuit and the first and second rectifier stages, and wherein the control circuit has a gate circuit (G7) which inhibits the operation of the first rectifier stage (CPC2) when the first circuit is out of operation. 16. Arrangement according to claim 15, wherein the gate circuit (G7) is arranged between the output terminal of the oscillator circuit (OSC) and the input terminal of the first rectifier stage (CPC2) and its operation is controlled by the control signal. 17. Arrangement according to claim 15 or 16, wherein the gate circuit (G7) inhibits the operation of the first rectifier stage (CPC2) when the first circuit is out of operation and when the detection signal (GD) is not generated by the level detector circuit (VLD). 18. Arrangement according to claim 17, wherein the level detector circuit (VLD) has a level shift stage (Q26...Q29) which, upon receipt of the substrate bias voltage (-Vbb), generates an output voltage which is level-shifted with respect to the same, and a level discriminator stage (IV10) which receives the output signal of the level shift stage. 19. Arrangement according to claim 18, wherein the level shift stage comprises a plurality of level shift elements (Q27...Q29), each of which comprises an insulated gate field effect transistor, said transistors being connected in series, and a bias element (Q26) which supplies the level shift elements with a bias current. 20. Arrangement according to claim 2, wherein the substrate bias generating circuit (Vbb-G) comprises: a first rectifier stage (C6, Q35, Q36) with a first capacitor (C6) which increases the precharge level of a second capacitor (C5) when the first rectifier stage is put into operation due to the control signal (VCN2) supplied to a gate circuit (G8), and a second rectifier stage (C5, Q37, Q38) comprising the second capacitor (C5) which is precharged in response to a first level of a periodic pulse signal and supplies a bias potential to the common substrate region at a first node (N1) in response to a second level of this pulse signal, a first switching stage (Q37) connected to the first node (N1) and forming a precharge path for the second capacitor (C5), and a second switching stage (Q38) arranged between the first node (N1) and the common substrate region and operating substantially complementarily to the first switching stage (Q37).