DE3570167D1 - Device for the automatic synchronisation of a local clock with a data signal, and sampling circuit for its application - Google Patents

Device for the automatic synchronisation of a local clock with a data signal, and sampling circuit for its application

Info

Publication number
DE3570167D1
DE3570167D1 DE8585401449T DE3570167T DE3570167D1 DE 3570167 D1 DE3570167 D1 DE 3570167D1 DE 8585401449 T DE8585401449 T DE 8585401449T DE 3570167 T DE3570167 T DE 3570167T DE 3570167 D1 DE3570167 D1 DE 3570167D1
Authority
DE
Germany
Prior art keywords
application
data signal
sampling circuit
local clock
automatic synchronisation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8585401449T
Other languages
English (en)
Inventor
Michel Servel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Application granted granted Critical
Publication of DE3570167D1 publication Critical patent/DE3570167D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE8585401449T 1984-07-13 1985-07-15 Device for the automatic synchronisation of a local clock with a data signal, and sampling circuit for its application Expired DE3570167D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8411189A FR2567696B1 (fr) 1984-07-13 1984-07-13 Dispositif de cadrage automatique d'horloge locale par rapport a un signal de donnees et circuit d'echantillonnage en comportant application

Publications (1)

Publication Number Publication Date
DE3570167D1 true DE3570167D1 (en) 1989-06-15

Family

ID=9306126

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585401449T Expired DE3570167D1 (en) 1984-07-13 1985-07-15 Device for the automatic synchronisation of a local clock with a data signal, and sampling circuit for its application

Country Status (3)

Country Link
EP (1) EP0168330B1 (de)
DE (1) DE3570167D1 (de)
FR (1) FR2567696B1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2623675A1 (fr) * 1987-11-25 1989-05-26 Dassault Electronique Dispositif de synchronisation d'une horloge par rapport a un signal numerique incident, notamment a haut debit
EP0363513B1 (de) * 1988-10-13 1994-02-16 Siemens Aktiengesellschaft Verfahren und Schaltungsanordnung zum Empfang eines binären Digitalsignals
US5146478A (en) * 1989-05-29 1992-09-08 Siemens Aktiengesellschaft Method and apparatus for receiving a binary digital signal
US6150855A (en) * 1990-02-06 2000-11-21 Bull, S.A. Phase-locked loop and resulting frequency multiplier
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
EP0511836B1 (de) * 1991-05-01 1997-04-16 Motorola, Inc. Breitbandiger digitaler Phasenausrichter
FR2704376B1 (fr) * 1993-04-22 1995-06-30 Rainard Jean Luc Procédé de récupération d'horloge et de synchronisation pour la réception d'informations transmises par un réseau ATM et dispositif de mise en Óoeuvre du procédé.

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3908084A (en) * 1974-10-07 1975-09-23 Bell Telephone Labor Inc High frequency character receiver
US4320525A (en) * 1979-10-29 1982-03-16 Burroughs Corporation Self synchronizing clock derivation circuit for double frequency encoded digital data

Also Published As

Publication number Publication date
FR2567696B1 (fr) 1991-06-28
EP0168330B1 (de) 1989-05-10
EP0168330A1 (de) 1986-01-15
FR2567696A1 (fr) 1986-01-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition