DE3505989C2 - - Google Patents

Description

The invention relates to a method for calculating the weighted average of a plurality of neighboring, as stored digital signals of available pixels according to the preamble of claim 1 or one Circuit arrangement for performing this method.

EP 00 95 514 A1 describes a method and a method Circuit arrangement for calculating the weighted  Average of a multitude of neighboring ones than stored ones Digital signals of existing pixels through Multiply signals corresponding to the pixels with weighting coefficients, adding the weighted Signals and correcting the sum signal are known.

In the previously known method, the image signals present in digital form are passed through a first register and digitally multiplied by weighting coefficients passed through a second register. Digital image signals formed one after the other by the multiplication are added to one another, the weighted mean value thus formed is then corrected. This process is purely digital. The technical effort is considerable because of the provision of registers, digital multipliers and digital adders, and in particular the control unit. Another disadvantage is that the total of the weighting coefficients must be 2 n , since the correction is to be carried out by omitting the least significant bits.

A circuit arrangement for calculating a weighted Mean value surrounded by a certain pixel Image signals is further from EP 00 95 514 A1 known.

The invention has for its object a method or to create a circuit arrangement that at low technical effort, especially with avoidance a variety of digital building blocks, better ones Deliver results.

According to the invention, this task is characterized by  Part of claim 1 and claim 2 specified features solved.

Claims 3 and 4 give advantageous refinements the circuit arrangement proposed according to the invention at.

The invention is described below with reference to a drawing explained. It shows

Fig. 1 is a schematic representation of the present invention,

Fig. 2 shows the structure of a digital / analog converter and a multiplier in the details,

Fig. 3 shows the structure of a circuit for summing the products and to the multiplying by a mean coefficient

Fig. 4 shows a method for magnification conversion.

Fig. 1 shows a block diagram of the present invention.

Digital input signals I ₁ _n to I converted into corresponding analog signals in digital / analog converters 1₁ to 1 _s and then analog multipliers 2₁ to _2N zugeführt.Die analog multiplier 2₁ to 2 take further weighting coefficient signals α ₁ to A _n for signals α Output ₁ I ₁ to α _n I _n , which are then added up in an adder 3 to a weighting 4 as the sum of the products

to be abandoned.  

The weighting circle 4 also receives an average value coefficient K for an calculation

to execute, the calculation result is converted back into an appropriate digital signal in an analog / digital converter 5 . The relationship between the input signals I _i , the weighting coefficients α ₁ and the output signal O can be expressed by an equation:

If the mean coefficient K is set with:

the following process can be used to average of the sums of the products.

It is now assumed that the weighting coefficients α _i (α ₁ to α _n ) which are to be assigned to the input signals I _i (I ₁ to I _n ) are each set to α ₀ and that the value of the input signals I _i (I ₁ until I _n ) are all I ₀, there should be a corresponding mean coefficient K ₀:

K ₀ = 1 / n α ₀,

if a corresponding output signal is O ₀:

O ₀ = K ₀ · n · α ₀ · I ₀ = I ₀

according to equation (2). It follows that the average of the sum of the products of the input signals I _i and the weighting coefficients α _{i are} reliably obtained.

Assuming that the value of each of N signals from all input signals is I _i I _S , the N signals are each assigned a weighting coefficient α _S and the other signals each have a weighting coefficient 0, the corresponding mean coefficient K _S should be:

K _S = 1 / N α _S

if the corresponding output signal is O _S :

O _S = K _S · N · α _S · I _S = I _S.

As in the previous case, the mean value of the sum of the products of the input signals I _i and the weighting coefficients α _{i is also} obtained here.

Fig. 2 shows in detail the structure of the digital / analog converter 1 ₁ to 1 _n (these are referred to here as 100 ( 100 ₁ to 100 _n )) and the multipliers 2 ₁ to 2 _n (these are here as 200 ₁ to Designated 200 _n ). In this exemplary embodiment from FIG. 2, the input signals I _i and the signals of the weighting coefficients α _{i are} each calculated in 8 bits. The digital / analog converter 100 is not limited to the exemplary embodiment shown in FIG. 2, but it must be suitable for the given purpose.

In the embodiment of the digital / analog converter 100 ₁ ( 100 ₂... 100 _n ) with an input signal I ₁ a plurality of input resistors 101 to 108 are provided in a ladder-shaped arrangement via corresponding digital switches 111 to 118 between a connection to which a reference voltage V _{C is} applied and a negative terminal of an operational amplifier. The digital switch 118 , which is connected to the highest resistor 108 of the ladder-like resistors, is controlled by the least significant bit (2⁰) of the digital input signal I ₁, while the digital switch 111 , which is connected to the lowest resistor 101 , by the most significant bit (2⁸) of the same input signal is controlled. A feedback resistor 121 is connected between the negative input terminal and the output of the operational amplifier 131 , the positive input of the operational amplifier is grounded.

It should be noted that the correspondence between the digital switches (resistors) and the bits of the input signal between each set of a plurality of switches (resistors) arranged in a ladder pattern is provided as the input or feedback resistors of the operational amplifiers 231 ( 231 ₁ to 231 _n ), 331 ( 331 ₁ to 331 _n ) and 381 ( 381 ₁ to 381 _n ) and the bits of the input signals to the respective amplifiers. The negative input of the operational amplifier 131 is grounded via a switch 119 , which is closed when no input signal is present, in order to enable the operational amplifier to be zeroed.

In a digital / analog converter constructed in this way, the relationship between the input signal I _i and an output signal V ₁₁ of the operational amplifier 131 is to be expressed by an equation:

V ₁₁ = ( R ₂ / R _C ₁) · V _C
= - ( R ₂ / 1 / (I ₁ · (1/128 R ₁))) · V _C
= - I ₁ · (R ₂ / 128 R ₁) · V _C ,

where R _C ₁ is a certain resistance from the resistors 101 to 108 . The maximum value of the output signal of the operational amplifier 131 is preferably as close as possible to the reference voltage V _C. Since the output of the operational amplifier 131 reaches its maximum value when the digital input signal reaches its maximum (in this case 255), assuming that the resistance R ₂ is given by:

R ₂ = (128/255) · R ₁ (4),

the equation (3) can be further expressed as:

V ₁₁ = - I ₁ · V _C / 255 (5).

The output signals V ₁ _i thus obtained from the digital / analog converter 100 ₁ to 100 _n are fed to the subsequent multipliers 200 ₁ to 200 _n . The multiplier 200 ₁ to 200 _n basically have the same structure as the digital / analog converter 100 ₁ to 100 _n . The following description is based on the multiplier 200 ₁.

The output signal V ₁₁ of the digital / analog converter 100 ₁ is at the negative input of an operational amplifier 231 through resistors 201 to 208 and digital switches 211 to 218 , which are arranged like a ladder, with the digital switches 211 to 218 of the weighting coefficient α ₁ can be controlled. The relationship between the digital switches (the resistors) and the weighting coefficients x ₁ is as indicated above. A resistor 221 is used as a feedback resistor for the operational amplifier 231 . A switch 219 is used for zero adjustment and thus corresponds to the switch 119 described above.

With this structure, the relationship between an output signal V ₂₁ and the input signal V ₁₁ of the operational amplifier 231 is expressed as:

V ₂₁ = - α ₁ · (R₄ / 128 R ₃) · V ₁₁ (6).

To operate the output signal V ₂₁ of the operational amplifier 231 at its maximum value when the input value V ₁₁ is at its maximum (in other words, the input signal I ₁ has the value 255) and the weighting coefficient has reached its maximum (ie has a value of 255) ) and the weighting coefficient has its maximum (ie has the value 255), equation (6) can be assumed with the assumption that the resistance R ₄ is given with

R ₄ = (128/255) R ₃ (7)

are further expressed as:

V ₂₁ = α ₁ · V ₁₁ / 255 (8).

Equation (8) can be converted into

V ₂₁ = α ₁ · I ₁ · (1/255) · (1/255) · V _C (9)

when the value V ₁₁ is given as in equation (5), is expressed.

Equation (9) can be expressed in general terms as:

V _i = a _i · I _i (1/255) · (1/255) · V _C (9 ')

in relation to the other digital / analog converters 100 ₂ to 100 _n and the multipliers 200 ₂ to 200 _n .

The thus obtained output signals V ₂ _i corresponding to the products of the input signals I _i and the weighting coefficient α ₁ are supplied to a circuit for adding up each of the products and multiplying the sum value by the mean coefficient K , as shown in FIG. 3.

In Fig. 3, the output signal V ₂ _i (V ₂₁ to V ₂ _n ) of the multiplier 200 ( 200 ₁ to 200 _n ) each corresponding to the input signals I _i (I ₁ to I _n ) an operational amplifier 331 via input resistors 30 _{n of} similar resistors R ₅ entered. The operational amplifier 331 is provided with feedback resistors 311 to 318 , which are arranged in a ladder-like manner via digital switches 321 to 328 between its negative input and its output, the digital switches (the resistors) being controlled by the corresponding bits of an average coefficient K ₁. The relationship between the resistors connected in series with switches 321 to 328 and the bits of the average coefficient K ₁ is as indicated above. With this structure, the output signal V _{A of} the operational amplifier 331 can be expressed as:

where R _C ₂ is the resistance value of one of the determined resistors 311 to 318 . Assuming that the ratio between the resistors R ₆ and R ₅

R ₆ = (255/128 × n) · R ₅ (11)

is such that V _A is equal to V _C if α _i = 255, I _i = 255 and K ₁ = 255 (V ₂ _i = V _C if α ₁ = 255 and I _i = 255 from equation (9)) , the output signal V _{A of} the operational amplifier 331 can be expressed as:

The output signal V _{A of} the operational amplifier 331 is fed to the negative input of an operational amplifier 381 via input resistors 341 to 348 and digital switches 351 to 358 , which are arranged in a ladder-like manner, the digital switches 351 to 358 being controlled by corresponding bits of an average coefficient K ₂.

Feedback resistors 361 to 368 and digital switches 371 to 378 of an operational amplifier 381 are arranged like a ladder, the switches are controlled by the corresponding bits of an average coefficient K ₃. The ratio between the input resistors 341 to 348 and the bits of the average coefficient K ₂ and the ratio between the feedback resistors and the average coefficient K ₃ are as indicated above. It must be noted that in this embodiment the average coefficient K consists of the three units K ₁, K ₂ and K ₃.

With the above construction, the output signal V _{B of} the operational amplifier 381 can be expressed as:

V _B = R _C ₄ / R _C ₃
= - (1 / K ₃ · (1/128 R ₈)) / (1 / (K ₂ · (1/128 R ₇))
= - (K ₂ R ₈ / K ₃ R ₇) V _A (13),

where R _C ₃ is the resistance of a particular one of resistors 315 to 318 , while R _C ₄ is the resistance of resistors 371 to 378 . Assuming that the ratio between the resistors R ₇ and R ₈ is:

R ₈ = R ₇ (14),

and that V _{B is} equal to V _C when α _i , I _i , K ₁, K ₂ and K ₃ are at their respective maxima (in this case 255), the equation (13) can be expressed as

V _B = - (K ₂ / K ₃) · V _A (15).

Then the final analog output signal V _B with respect to the output signal V ₂ _{i of} the multipliers 200 ₁ to 200 _{n is expressed} according to equations (12) and (15) as:

From this representation, the final analog end signal V _B can be further expressed in relation to the input signal I _i (I ₁ to I _n ) and the corresponding weighting coefficients α _i ( a ₁ to α _n ) according to equations (9) and (16) are considered:

Assuming that in equation (17) α _i = I _i = 255, the final analog output signal V _B results as:

V _B = 255 · (K ₂ / K ₁ · K ₃) · V _C (18),

and is particularly expressed as:

V _B = V _C (19),

if K ₁ = K ₂ = K ₃ = 255. By setting the analog / digital converter 5 such that it outputs a maximum of an 8-bit signal (= 255) with respect to an input signal V _C , an output signal of a desired value can thus be obtained from the analog / digital converter 5 .

Two calculation examples are given below.

example 1

If n = 9, α ₁ to α ₉ = 255, I ₁ to I ₉ = 255 and K ₁ = K ₂ = K ₃ = 255, the output signal V ₁ _{i of} the operational amplifier 131 results from equation (5) with

V ₁ _i = - V _C (i : 1 to 9) (20),

the output signal V ₂ _{i of} the operational amplifier 231 according to equations (8) and (9) results in:

V ₂ _i = - V ₁ _i = V _C (i : 1 to 9) (21),

the output signal V _{A of} the operational amplifier 331 results from equation (12) with:

V _A = - (255 / K ₁ · 9) · 9 · V _C = - V _C (22),

while the output signal V _{B of} the operational amplifier 381 results from equation (15) as:

V _B = V _C (23).

It results from the above equations that the output signal of the operational amplifier 381 is either V _C or - V _C.

Example 2

If n = 4, α ₁ to α ₄ = 255, α ₅ to α ₉ = 0, I ₁ to I ₄ = 255 and I ₅ to I ₉ = 0, the output signal V ₁ _i results from equation (5) as follows:

V ₁ _i = - V _C (i : 1 to 4)
V ₁ _i = 0 (i : 5 to 9) (24)

the output signal V₂ _i results from equations (8) and (9) with:

V ₂ _i = - V _i = V _C (i : 1 to 4)
V ₂ _i = 0 (i : 5 to 9) (25)

the output signals V _A and V _B therefore result from equation (12) as:

V _A = - (255 / K ₁ · 9) · 4 · V _C (26),

and

V _B = (4 · 255/9) · (K ₂ / K ₁ · K ₃) · V _C (27).

Assuming that the mean coefficient K ₁ = 4 × 28 = 112, the following results for the output signal V _A from equation (26):

V _A = - (255/112 x 9) x 4 · V _C = V _C -1.00119047,

when the output signal V _{A is} approximately equal to the value - V _C. If it is further assumed from equation (27) that the mean coefficients K ₂ and K ₃ are given with K ₂ = 9 × 28 and K ₃ = 255, the final output signal V _{B is} approximately equal to the value V _C as the average of the sums of Products of the four input signals above.

Theoretically, the mean coefficients K ₁ and K ₂ can be 4 or 9, however, by setting the mean coefficients K ₁, K ₂ and K ₃ close to 255, the output signal of the analog operational amplifier becomes equal to or approximately equal to the reference value V _C.

Example 3

Assuming that n = 9, α ₁, α ₃ α ₇ and α ₉ = 32, α ₂, α ₄, a ₆ and α ₈ = 128, α ₅ = 255 and I ₁ to I ₉ = 255 the output signals V ₁ _i (i = 1 to 9) of the analog / digital converter 100 ₁ to 100 ₉ from equation (5) as follows:

V ₁ _i = - V _C (i = 1 to 9),

while the output signals V ₂ _{i of} the multipliers 200 ₁ to 200 ₉ result from equation (9) n as:

V ₂ _i (i : 1, 3, 7, 9) = 32 · 255 · (1/255) · (1/255) · V _C = (32/255) · V _C ,
V₂ _i (i : 2, 4, 6, 8) = (128/255) V _C ,

and

V ₂ _i (i : 5) = V _C.

The output signal V _{A of} the operational amplifier 331 is expressed as:

V _A = - (255 / K ₁9) · ((32/255) · 4 + (128/255) · 4 + (255/255)) · V _C = - (895/9) · (1 / K ₁) V _C (28),

while the output signal V _{B of} the operational amplifier 381 results as:

V _B = (895/9) · (K ₂ / K 1 · K ₃) · V _C
= (5 × 179/9) · ( K ₂ / K ₁ / K ₃) · V _C (29).

Assuming that the average value K ₁ with K ₁ = 5 × 20 = 100 is given, the output signal V _{A of} the operational amplifier 331 results as:

V _A = -0.994 V · _C,

if the output signal V _{A is} assumed to be approximately equal to the value - V _C. If one further assumes that the mean coefficients K ₂ and K ₃ with K ₂ = 9 × 20 = 180 and K ₃ = 179, it follows from equation (29) that the final output signal V _B becomes approximately equal to the value V _C as the average of the sum of the products of the new input signals.

In this context, it should be noted that even if the input signal I _i (I ₁ to I _n ) and weighting coefficient signals are applied to the terminals opposite one another, the same result is obtained as is immediately apparent from equation (9).

Although the present invention has been described with reference to a process of averaging the Buzzing of products to increase contrast, it can also find use in the following case.

By averaging four image signals according to the inventive method in a signal and Use of the mean signal in reproduction of images, as shown in Example 2, a  Reproduction image can be obtained by a quarter (half in the enlargement ratios of the Main and sub-scanning directions) as long as the ratio the pixel sizes on the input side and the Output side is 1: 1.

The following are various application examples of the method according to the invention.

When displaying a large picture on a display monitor is the image signal thus obtained for display reduced on the display monitor with everyone compressed pixel data (including the number of Pixel on the display monitor is less than that of the Image) by using the method of the present Invention.

On the other hand, when an enlargement conversion is performed, as shown in Figs. 4 (a) and (b), in which the relationship between the main scanning direction and the sub-scanning direction of the data stored in a storage means is input to a digital-to-analog converter 1 in succession are changed in the order of 3: 3, 2: 3, 3: 3. . . for one scan line and 2: 2, 3: 2, 2: 2 for the next scan line, the analog / digital converter 5 forms an output signal corresponding to an image with a magnification ratio of 2 / (2 + 3) = 2/5 (if the image signal corresponds to the actual size of the corresponding template) or from 2 × 10/5 = 4 (if the image data corresponds to 10 times the size of the corresponding template) for the display monitor. Image signals from the input scanner can also be fed directly to the digital / analog converter 1 instead of the image signals from the memory. Furthermore, the magnification ratio with respect to the main scanning direction and the sub-scanning direction can be changed independently of each other.

The present invention is also applicable to effecting some kind of optical filtering, such as a shadow mask, by choosing a weighting coefficient of 0 for a part of all pixels of the image signal which are input to the digital / analog converter 1 when such a filter signal is aimed at everyone central pixels or the surrounding pixels.

In a digital arithmetic operation, since the addition is carried out two signals with two signals, assuming that the number of signals to be summed is n , a total number of (n -1) adders are necessary. Instead, only resistors are present in the invention.

Unlike the digital addition, in which the Errors due to the addition or elimination of the least significant Adding up bits is the same with analog calculation the present invention, the error generated in the Perform a calculation of approximately 8 bits less.

On the other hand, it should be noted that the present Invention can be applied using relatively economical linear amplifiers as multipliers and digital / analog converters versus digital Multipliers. If table storage as Multipliers used are wires that are normally  for introducing a signal for driving of table storage in accordance with the change serve the weighting coefficient in the present case Invention not required. In this context it should be noted that limited table memory anyway if the weighting coefficients change cannot be used. The advantage of The present invention is particularly given when there are several input signals.

Claims (4)

1. Method for calculating the weighted mean value from a plurality of adjacent pixels present as stored digital signals, by multiplying signals corresponding to the pixels by weighting coefficients, adding the weighted signals and correcting the sum signal, characterized by digital / analog conversion of the image signals to be taken into account, Multiplying the analog image signals by the respective weighting coefficients, adding the weighted analog image signals, multiplying the analog sum signal by a correction value which is reciprocal to the sum of the weighting coefficients and analog / digital conversion of the image signals thus compressed. 2. Circuit arrangement for carrying out the method according to claim 1, characterized by a number of digital / analog converters corresponding to the number n of pixels to be taken into account ( 100 ₁ to 100 _n ), and a number of first analog multipliers corresponding to the number n of pixels to be taken into account ( 200 ₁ to 200 _n ), an adder ( 3 ) with the number n of the pixels to be taken into account corresponding summation inputs, a second analog multiplier ( 4 ) and an analog / digital converter ( 5 ). 3. A circuit arrangement according to claim 2, characterized in that the first analog multipliers ( 200 ₁ to 200 _n ) are formed by operational amplifiers ( 231 ₁ to 231 _n ), the series resistors of which are controlled by digital switches ( 211 to 218 ) controlled by the weighting coefficients. are switched. 4. Circuit arrangement according to claim 2 or 3, characterized in that the second analog multiplier ( 4 ) by a first operational amplifier ( 331 ), the negative feedback resistors ( 311 to 318 ) via a first correction value K ₁ controlled first digital switch ( 321, 328 ) are connected and by a second operational amplifier ( 381 ), the series resistors ( 341 to 348 ) of a second correction value K ₂ controlled second digital switches ( 351 to 358 ) are switched and the negative feedback resistors ( 361 to 368 ) of a third correction value K ₃ controlled third digital switches ( 371 to 378 ) can be controlled.