DE3485885T2 - DIGITAL PHASE BAR LOOP FOR MULTIPLE FREQUENCIES. - Google Patents

Description

Background of the invention

This invention relates to the field of digital phase-locked loops and, more particularly, to an improved digital phase-locked loop in which the operating center frequency of a circuit can be programmably varied without changing the frequency divider ratio within the feedback portion of the digital phase-locked loop.

Description of the state of the art

The conventional phase-locked loop is connected to a clock signal that provides a reference operating frequency and is typically divided down to the precise operating frequency of the loop. In addition to a frequency divider, the conventional phase-locked loop circuit includes a phase comparator and a phase equalization network. In operation, the divided operating frequency is connected to the phase comparator, which compares the phase of the divided operating frequency to the phase of a received data signal. The phase comparator commands the phase equalization circuit to adjust the phase of the divided clock by advancing or retarding the phase of the divided clock signal. A digital phase-locked loop of this type is shown and described in U.S. Patent 3,983,498 to Malek entitled "Digital Phase-Locked Loop" and assigned to the assignees of the present invention.

J.P. Gouyet, in "A High Precision Phase Lock Loop", Conference on Frequency Generation and Control for Radio Systems, London, 22-24 May 1966, pages 129-133, discusses the use of a bidirectional counter to sign-accumulate phase errors of a phase-locked loop and to supply phase correction information to the remainder of the loop.

Digital phase-locked loops of this type are satisfactory for single-frequency operation of a phase-locked loop, but the realization of a loop leading to multi-frequency operation capable, but usually requires complicated circuitry. Some conventional phase-locked loops achieve multi-frequency operation by coupling a programmable divider between the reference frequency source and the clock input of the loop. This technique severely limits the operating range of the phase-locked loop, and for small frequency shifts the divider ratios become impractical, if not impossible. Furthermore, phase-locked loops of this type are of limited use as tone demodulators because of the forbidden divider ratios required for small frequency shifts.

Summary of the invention

Accordingly, the present invention seeks to provide a digital multi-frequency phase-locked loop that can be implemented without disturbing the feedback divider ratio of the phase-locked loop.

According to one aspect of the present invention, there is provided a digital multi-frequency phase-locked loop (DPLL) for processing a received data signal and producing an output signal that is phase-locked to the received data signal, comprising:

(a) phase comparator means having first and second inputs, the first input connected to the received data signal and the second input connected to the DPLL output signal, and an output for providing an output signal indicative of the relative phase between the incoming data signal and the DPLL output signal;

(b) clock means for generating a reference clock signal;

(c) programmable divider means connected to the reference clock signal and having an output and programmable inputs for generating a programmable clock signal related to the reference clock signal according to a ratio controlled by the programmable inputs;

(d) digital means connected to the output of the programmable clock signal generating means and the means for generating a reference clock signal for generating first and second clock signals, one of which is delayed from the other;

(e) phase and frequency adjustment means, connected to the means for generating a reference clock signal, for generating a composite clock signal by periodically, selectively adding or subtracting the first and second clock signals at a rate defined by the programmable clock signal to effect frequency adjustment, or by individually adding or subtracting pulses in response to the phase comparator output signal to effect phase adjustment;

(f) frequency divider means (16) connected to the phase and frequency adjustment means for processing the composite clock signal to produce the output signal of the digital phase locked loop. A corresponding method for effecting phase and frequency adjustments is set out in claim 4.

Short description of the drawings

Figure 1 is a block diagram of the digital multi-frequency phase-locked loop of the present invention.

Figure 2a is an electrical diagram of the programmable divider, phase comparator, and phase and frequency adjustment network of the digital multi-frequency phase-locked loop of Figure 1.

Figure 2b is an electrical diagram of the frequency divider and lock detector circuit of the digital phase-locked loop of Figure 1.

Figure 3a is a timing diagram describing the operation of the frequency setting part of Figure 2a.

Figure 3b is a timing diagram describing the operation of the phase adjustment part of Figure 2a.

Figure 3c is a timing diagram describing the operation of the lock detector circuit of Figure 2b.

Detailed description of the drawings

Figure 1 shows a block diagram of the digital multi-frequency phase-locked loop (DPLL) 10 constructed in accordance with the present invention. The digital phase-locked loop includes a phase and frequency adjustment network 12 connected to a digital divider 16, a bandwidth controller 20, an AND gate 30, and an input clock terminal 14. The bandwidth controller 20 is also connected to a phase comparator 18. The phase comparator 18 receives inputs from both the output of the digital divider 16 and the received data signal.

In operation, a reference clock signal from a signal source is connected to the phase and frequency adjustment network 12 via terminal 14. The reference clock signal is additionally connected to the digital divider 26 and the programmable digital divider 28. The phase and frequency adjustment network 12 generates a shifted clock signal from the reference clock signal, and produces frequency shifts by selectively adding or subtracting the reference clock signal and the shifted clock signal at a rate determined by the programmable clock signal from AND gate 30, which is controlled by the programmable signals Y and Z. The phase and frequency adjustment network also effects phase shifts at the command of both a programmable control signal X and the signals generated by the bandwidth controller 20.

The phase and bandwidth adjustment network 12 provides a composite clock signal E which is connected to the digital divider 16. The digital divider 16 divides the frequency of the composite clock signal E and provides the output signal of the digital phase-locked loop. The output of the digital divider 16 is connected to an input of the phase comparator 18. A second input of the phase comparator 18 is connected to a received data signal. The phase comparator provides a signal related to the relative phase of the output from the DPLL and the received data signal. If the DPLL output signal and the input data signal are not exactly in phase, an output is displayed. The function of the phase comparator is discussed in more detail later.

The digital multi-frequency phase-locked loop is additionally provided with two frequency dividers 26 and 28 connected to the clock input 14 and an AND gate 30. The digital divider 28 receives the programmable inputs Y, Z which cause the divider 28 to perform a number of division ratios. The programmable controllers Y, Z and a controller X cooperate with a bandwidth controller 20 and cause the bandwidth controller to vary the loop correction bandwidth according to the operating frequencies of the loop. The programmable controller X also cooperates with the phase and frequency adjustment network 12 and controls the direction of frequency corrections through the digital phase-locked loop. The inputs to the phase comparator are also connected to an EXCLUSIVE-OR gate 24 which is further connected to a lock detector 22.

As previously mentioned, the multi-frequency DPLL operates with three programmable controllers X, Y, Z. The programmable control signals operate with the bandwidth controller 20, the phase and frequency adjuster 12, and the programmable digital divider 28 to determine the center frequency and bandwidth of the multi-frequency DPLL. In the preferred practice of the present invention, it is desirable to provide a first operating frequency with a wideband capability and several other operating frequencies with a narrowband capability. This feature allows a number of operating frequencies to be tested while the multi-frequency DPLL is programmed to a known single frequency. The bandwidth controller 20 effects loop bandwidth variation by changing the number of digital pulses added to or subtracted from the composite clock while performing loop phase adjustment.

The programmable controllers Y, Z also control the operating frequency of the loop in the following manner. The composite reference clock signal is connected to divider 16 via phase and frequency adjustment network 12. In the preferred embodiment, a reference clock signal of 1.92 MHz is provided and without any other interference, divider 16 would provide a loop operating frequency of 6000 Hz. The multi-frequency DPLL is therefore capable of approximately 6000 corrections per second. Furthermore, the dividers 26 and 28 are connected to the 1.92 MHz reference clock and the AND gate 30 to provide an output signal that can embody various possible frequencies based on the programmable control signals Y, Z. The output frequency of the AND gate 30 is equivalent to

fEderived = N/200 (fReference)

where N is provided by the programmable controllers Y,Z, as shown in Figure 1. Therefore, for example, for N=1 this output is

1.92MHz/200 = 9600Hz

The programmable clock signal is connected to the phase and frequency adjustment network 12, which either adds, subtracts, or neither shifted clock pulses from the 1.92 MHz reference clock signal at a rate determined by the programmable clock signal. Therefore, for N=1, the loop operating frequency would be calculated as follows:

1.92MHz + 9600Hz/320 = 6030Hz

As previously mentioned, the multi-frequency DPLL can perform approximately 6000 corrections per second for the frequencies described. If the phase and frequency adjustment network adds or subtracts 6000 pulses/s to the reference clock signal, the digital phase-locked loop can compensate for phase mismatches according to the following relationship:

1.92MHz + 6000Hz/320 = 6018.72Hz

Therefore, if the bandwidth controller 20 adds or subtracts 1 pulse/correction, the loop bandwidth can be defined as:

6000Hz ± 18.75Hz

The phase comparator 18 can be programmed to perform phase comparisons on the positive edges of fl or on the positive and negative edges of fo when X Y Z = 0 0 0. The last condition means that approximately 12,000 corrections per second are to be made and is used in conjunction with an additional pulse added or subtracted per correction to extend the locking bandwidth of the DPll.

1.92 + 2(12000)/320 = 6000 ± 75 Hz

The programmable control signals X, Y, Z instruct the bandwidth controller 20 to add/subtract 1, 2 or 4 pulses per correction. Therefore, according to the preferred practice of the present invention and the above relationships, the multi-frequency DPLL can have loop bandwidths of 18.75 Hz, 75 Hz or 150 Hz under the control of the bandwidth control circuit 20.

The relationship between the programmable control signals X, Y, Z and loop operating frequency and bandwidth is shown in Table 1 below. Table 1 Center frequency mode Bb ±

Figure 2a shows an electrical diagram of the phase and frequency adjustment network 12, the phase comparator 18, the bandwidth controller 20 and the digital dividers 26, 28 of Figure 1. The associated timing diagrams are shown in Figures 3a and 3b. According to Figure 2a, a reference clock signal is connected to terminal 14 and provides the Operating reference frequency for the multi-frequency DPLL. The reference clock signal is processed by flip-flop 101 which is further connected to NOR gates 103, 105. Flip-flop 101 and NOR gates 103,105 provide a reference clock, signal B, and a shifted reference clock signal, signal A, shown in Figure 3a. The output terminal of NOR gate 105, or signal A, is connected to a flip-flop 107 which forms an input to bandwidth controller 20. Signal A is also provided to a multiplexer 109 which is also associated with bandwidth controller 20. Signal A is additionally connected to a flip-flop 111 and an AND gate 113 which form part of phase and frequency adjustment network 12.

The output of NOR gate 103, signal B, is connected to flip-flops 115, 117, 119, 121, 123 which form part of frequency divider 26 of Figure 1. Further, signal B is connected to flip-flops 125, 127 and 129 which form part of programmable divider 28. Signal B is additionally connected to flip-flop 131 and multiplexer 133 in bandwidth control circuit 20. Further, signal B is connected to AND gate 135 in phase and frequency adjustment network 12.

Still referring to Figure 2a, the phase comparator 18 includes flip-flops 137, 139, 141, 145, 147 and 149, OR gates 151 and 153, AND gate 155 and NOR gate 157 connected as shown in Figure 2a. Specifically, flip-flop 137 is connected to flip-flops 141 and 143 which form part of the phase lead circuit of the phase comparator 18. Similarly, flip-flop 147 is connected to flip-flops 145 and 149 and form part of the phase delay circuit of phase comparator 18. Flip-flop 139 is connected to flip-flops 143 and 145 and provides signals to the phase advance portion and phase delay portion of comparator 18. OR gate 151 is connected to flip-flops 141 and 149 and provides a first output signal to phase comparator 18. OR gate 153 is connected to flip-flops 143 and 145 and provides a second output signal to the phase comparator circuit. AND gate 155 is connected to flip-flops 145 and 149 and cooperates with NOR gate 157 which is connected to flip-flops 141 and 143 to provide a reset function. to the phase comparator 18. It should be noted that flip-flops 137, 139, 141, 143, 145, 147 and 149 are D-type flip-flops which are well known.

The operation of the phase comparator 18 is explained in connection with Figure 3b. Figure 3b shows two clock signals fo and 2fo. These signals, discussed in more detail below, are derived from the reference clock signal by the digital divider circuit 16 of Figure 1. The three derived clock signals fo and 2fo of Figure 3a are connected to the phase comparator 18 of Figure 2a as shown. Specifically, clock signal fo is provided at the D terminal of flip-flop 139 and at the C terminal of flip-flop 137. The clock signal is provided at the C terminal of flip-flop 147. The 2fo clock signal is provided at the C terminal of flip-flop 139. The incoming signal, fo, is connected to the D input terminals of flip-flops 137 and 147.

Referring now to Figures 2a and 3b. Signal G of Figure 3b corresponds to the Q output signal of flip-flop 137 of Figure 2a. Signal H of Figure 3b corresponds to the Q output terminal of flip-flop 147 of Figure 2a. Signal I of Figure 3b corresponds to the Q output terminal of flip-flop 141 of Figure 2a. Signal G of Figure 3b corresponds to the Q output terminal of flip-flop 137 of Figure 2a.

As previously mentioned, the purpose of phase comparator 18 is to provide output signals indicative of the relative phase of the reference clock signal and the received data signal. The phase locked loop output signal fo is used to sample the received data signal fi. Three possible phase relationships can exist between these two signals. The signals can be in phase, or the phase locked loop output signal can lead or lag the incoming data signal. Flip-flops 137 and 139 provide a comparison of the incoming data signal and the DPLL output signal. If the incoming data signal (fi) leads the output of divider 16, as shown in Figure 3b, flip-flop 137 will cause signal G to go high. Since flip-flop 137 is clocked directly by fo, signal G will go high on the leading edge of a transition in fo. Flip-flop 139 is connected to fo and is clocked by a 2fo signal, therefore Signal L can be set high on any positive transition in fo, but 2fo is set high 1/2 cycle later than fo because of the 1/2 cycle delay provided by flip-flop 139. Actual phase corrections are made on a positive transition in signal L, so it is desirable to delay signal L to prevent phase corrections from occurring on an edge of the fo control clock.

For the phase condition shown in Figure 3b and described above, a positive transition in signal G followed by a positive transition in L will cause the output of flip-flop 141 to be set high (signal I). A high value in signal I indicates that fi is leading fo and therefore pulses should be added to the composite system clock to cause the phase of fo to advance. If the phase of the DPLL output signal leads the received data signal, the output of flip-flop 143, signal , will be set high, indicating that pulses should be subtracted from the composite system clock to cause fo to delay.

Flip-flops 145, 147 and 149 operate in an analogous manner, however flip-flop 147 is clocked on the negative edge of fo and produces phase comparison signals I' and , which are delayed with respect to signals I and . Flip-flops 145, 147 and 149 are held in reset by bandwidth control circuit 20 through AND gate 155. When the digital phase-locked loop circuit is set for narrowband operation, one phase comparison per period of fo is required. When the digital phase-locked loop is set for wideband operation, flip-flops 145, 147 and 149 are activated and phase comparator 18 provides two phase comparisons per comparison period. That is, one comparison on the leading edge of fo and one on the trailing edge of fo. Flip-flops 141, 143, 145 and 149 are also reset via AND gate 155 and NOR gate 157 whenever a phase adjustment has been performed.

Referring now to Figure 2a, the DPLL digital divider 28 is shown. Digital divider 28 is clocked by system clock B and provides a variable division ratio based on the programmable System controllers Y, Z. Digital divider 28 includes flip-flops 125, 127 and 129 as well as multiplexers 159 and AND gates 161, 163 and 173, NAND gates 167, 169 and 171, inverter 165 and EXCLUSIVE-OR gates 177 and 175 connected as shown in Figure 2a.

Digital divider 26 includes flip-flops 115, 117, 119, 121, 123 and NAND gates 181, 183, 185, 187 and 189 connected as shown in Figure 2a.

Divider 26 provides a fixed division ratio of 25. Divider 28 provides a variable division ratio from 1 to 8. The outputs of dividers 26, 28 are combined as duals by AND gate 30 to provide a composite division ratio of 200/N, where N is controlled by programmable controls Y, Z. It should be noted that digital dividers of this type are well known and various divider configurations will work satisfactorily. Therefore, dividers 26, 28 may be any suitable conventional 200/N digital dividers and are not limited to the specific configuration shown in Figure 2a.

Still referring to Figure 2a, the phase and frequency adjustment network 12 of Figure 1 is shown. The phase and frequency adjustment network 12 operates in conjunction with the programmable control signal X, the derived programmable clock signal, the reference clock signal B, the shifted reference clock signal A, and the output of bandwidth controller 20 to add or subtract pulses to the DPLL reference signal B to compensate for phase imbalances or frequency changes. The phase and frequency adjustment network 12 includes flip-flops 111 and 197 which effect frequency adjustments and flip-flops 209 and 211 which effect phase adjustments. The phase and frequency network additionally includes inverters 191, 195, 205, NAND gates 193, 203, 113, 135 and 217, AND gates 201 and 207, NOR gates 215 and 157 and OR gate 213, connected as shown in Figure 2a.

As previously mentioned, OR gates 151 and 153 in the phase comparator 18 provide an output signal in which an active signal appearing at the output of OR gate 151 indicates that pulses should be added to the composite clock, signal E, to equalize the phase and an active signal appearing at the output of OR gate 153 similarly indicates that pulses should be subtracted to equalize the phase. The phase and frequency adjustment network 12 also cooperates with the programmable signals X, Y, Z to produce frequency shifts in the operating frequency of the digital phase locked loop.

The phase and frequency adjustment network 12 provides phase and frequency adjustments by combining or subtracting a reference clock, signal B, and a shifted reference clock, signal A, to provide a composite clock signal E that operates the divider 16 of the digital phase-locked loop of Figure 2b. Furthermore, the phase and frequency adjustment network 12 is connected to the output of AND gate 30, which generates a programmable clock signal and sets the adjustment rate of the phase and frequency adjustment network 12.

The phase and frequency adjustment network 12 continues to operate in conjunction with the programmable input signal X, which indicates positive or negative frequency shifts from the operating center frequency of the loop.

In operation, the phase and frequency adjustment network 12 is continuously provided with clock signal A via flip-flop 111 and NAND gate 113, clock signal B via flip-flop 197 and NAND gate 135, and clock signal C via NAND gates 193 and 203. The programmable input signal X is connected to inverter 191 which selectively enables either flip-flop 197 (add frequency) or flip-flop 111 (subtract frequency) depending on the state of signal X. When the programmable signal X is low, the derived programmable clock signal C is connected to flip-flop 197 via NAND gate 193 and inverter 195. In a similar manner, when the programmable input signal X is high, the derived clock signal C is connected to flip-flop 111 via NAND gate 203 and inverter 205. When the programmable derived clock signal C appears at the delay input of flip-flop 197, clock signal B will allow signal C to pass through flip-flop 197 to OR gate 213. The next clock pulse B will reset flip-flop 197 and thus gate a single pulse through flip-flop 197.

The output of OR gate 213 is normally low except when pulses are to be added to the system master clock B, therefore, when the output of flip-flop 197 is high, clock A is summed with clock signal B through NAND gates 113, 135 and 217.

Pulses are subtracted from clock B in a similar manner. When the programmable input signal X is low, the programmable derived clock signal C is connected to flip-flop 111 through NAND gate 203 and inverter 205. The programmable derived clock signal C is clocked through flip-flop 111 with each positive transition of clock A, allowing the output to go high and thus drive the output of NOR gate 215 low. When the output of NOR gate 215 goes low, NAND gate 135 is turned off and the system master clock B is disconnected from the composite clock signal E.

Phase adjustments are also accomplished using OR gate 213, NOR gate 215, and NAND gates 113, 135, and 217. As previously mentioned, the output from OR gates 151 and 153 includes phase adjustment indication signals. That is, when the output of OR gate 151 is active, a positive phase adjustment is required. When the output of OR gate 153 is active, a negative phase shift is required. Referring now to Figure 2a, phase comparator 18 interacts with phase and frequency adjustment network 12 via AND gates 201 and 207. AND gates 201 and 207 also interact with NAND gates 193 and 203 and provide a decision between phase and frequency adjustment. If a frequency adjustment is currently in progress, AND gates 201 and 207 will prevent the phase adjustment from being performed until the frequency adjustment is completed. This feature will be discussed in more detail later.

Assuming that a frequency adjustment is not currently in progress, the phase comparison signals I, , I' or are connected to the delay inputs of flip-flops 209 and 211, respectively. The phase adjustment flip-flops 209 and 211 also operate with the clock signals A, B together via the bandwidth controller 20. The bandwidth controller 20 will be discussed in more detail below. But briefly, the bandwidth controller 20 provides control for the number of pulses to be added to or subtracted from the composite clock signal E for phase comparisons.

The bandwidth regulator circuit provides variable pulse control by providing a variable clock signal to flip-flops 209 and 211. When the delay input of flip-flop 209 is active, any positive transition of the signal appearing at the clock terminal will cause signal K to go high, activating the output of OR gate 213, which enables NAND gate 113. As mentioned above, when NAND gate 113 is enabled, pulses are added to the composite system clock E, with the actual number of phase pulses added being controlled by the clock terminal of flip-flop 209.

If a negative phase shift is required, pulses must be subtracted from the composite clock signal E. When the output of OR gate 153 is active, a negative phase adjustment is momentarily performed, the output of NAND gate 203 is high, enabling AND gate 207 which connects the output of NOR gate 153 to flip-flop 211. Flip-flop 211 cooperates with bandwidth controller 20 through the clock terminal of flip-flop 211. With each positive transition of the bandwidth control clock generated in the bandwidth controller circuit, the output of flip-flop 211 will go high when a negative phase shift is required. When the output of flip-flop 211 is high, the output of NOR gate 215 will go low and turn off NAND gate 135, thus preventing pulses from clock signal B from combining with the composite clock signal E.

As previously mentioned, phase adjustments are delayed if a frequency adjustment is currently in progress. Referring now to the phase comparator 18 of Figure 2a, the outputs of flip-flops 141, 143, 145 and 149 include signals indicative of phase adjustments. Once a phase adjustment signal appears, the signal is maintained until the associated flip-flop is reset. The reset signal indicates that a phase adjustment is complete. The phase adjustment reset signal is derived from the phase and frequency adjustment network 12 through NOR gate 157. The outputs of the phase adjustment flip-flops 209 and 211 are connected to the inputs of NOR gate 157 such that whenever a phase adjustment is complete, on the next bandwidth control clock the output of NOR gate 157 goes low and the flip-flops 141 and 143 are reset.

Still referring to Figure 2a, the bandwidth controller 20 of Figure 1 is shown in detail. The bandwidth controller 20 is controlled by the programmable control signals X, Y and Z and the programmable switches 223 and 225. The bandwidth controller 20 provides a variable control which determines the number of pulses to be added or subtracted during phase adjustments. Specifically, the bandwidth controller 20 can effect phase adjustments of one, two or four pulses based on the programmable input signals. As previously mentioned, the bandwidth controller 20 provides a variable clock signal to the flip-flops 209 and 211 of the phase and frequency adjustment network 12.

Bandwidth controller 20 includes flip-flops 131 and 221 connected as frequency dividers, flip-flops 107 and 219 also connected as frequency dividers, NOR gates 227, programmable switches 223 and 225, and multiplexers 133 and 109. In operation, flip-flops 131 and 221 are connected to clock B and provide signals at one-half and one-quarter the rate of reference clock signal B. Flip-flops 107 and 219 are connected to clock signal A and provide signals at one-half and one-quarter the rate of clock signal A. The divided clock signals B and A are connected to multiplexers 133 and 109 through programmable switches 223 and 225, respectively. The programmable switches 223 and 225 control which divided clock signal is connected to the multiplexers 133 and 109. When the mode one position is selected, divided clock signals of a higher rate are connected to the phase adjustment flip-flops 209 and 211, which causes the Q outputs of the flip-flops 209 and 211 to be set and cleared more quickly, thereby reducing the number of pulses to be added to or subtracted from the composite system clock, signal E.

When a relatively large number of pulses are added to or subtracted from the composite system clock, a larger phase shift is effected, thus providing a wider bandwidth capability of the loop. NOR gate 227 is connected to the programmable loop control signals X, Y, Z and has an output connected to the clock terminals of multiplexers 133 and 109.

A high output signal at the output of NOR gate 227 indicates that the digital phase-locked loop has been set for wideband operation. This output signal causes multiplexers 133 and 109 to select programmable switches 223 and 225, which were previously set for a required system configuration, causing flip-flops 209 and 211 to perform multiple pulse corrections. If the output of NOR gate 227 is low, the multi-frequency digital phase-locked loop is set for narrowband operation and multiplexers 109, 133 will select signals A or B to perform single pulse corrections.

Referring now to Figure 2b, there is shown a detailed electrical diagram of the digital divider 16 and the lock detector 22 of Figure 1. The various clock signals of Figure 2b are shown in Figure 3b and Figures 2a and 3c are referred to alternately.

The frequency divider 16 of Figure 1 is connected to the composite clock signal E of Figures 2a and 3a. The frequency divider 16 divides the composite clock signal E to provide the operating clock signal of the digital phase-locked loop 10. In addition, the frequency divider 16 provides a plurality of derived clock signals to operate the lock detector 22. The frequency divider 16 includes flip-flops 301, 303, 305, 307, 309, 311, 313, 315, 317 and NOR gates 319 connected as shown in Figure 2b, which is a well-known frequency divider configuration. The output of flip-flop 303 provides a signal at one-quarter the frequency of the composite clock signal E which is used to operate various parts of the lock detector 22. In addition, the flip-flops 311, 313 and 315 and NOR gate 319 form a 5:1 divider 310 which produces a signal of intermediate frequency with respect to the whole of divider 16. The combined outputs of divider 310 include a clock signal aligned with fo, the operating clock signal of digital phase-locked loop 10. In accordance with the preferred practice of the present invention, divider 16 provides an output signal which has been divided by 320 with respect to the composite clock signal E. It should be noted that many frequency divider configurations would work satisfactorily with the present invention and the present invention is not limited to the specific configuration shown in Figure 2b.

Still referring to Figure 2b, the lock detector circuit 22 is shown in detail. The lock detector 22 compares the digital phase-locked loop's output clock signal, fo, and a received data signal, fi, and provides an indication when the two signals are in phase. The lock detector circuit 22 allows the digital phase-locked loop of the present invention to be used as a tone demodulator. Since the digital phase-locked loop can be programmed to operate at a specific known frequency, the lock detector 22 can provide an indication that a specific frequency has been detected within the operating bandwidth.

The inputs of the lock detector circuit are provided by EXCLUSIVE-OR gate 329 which is connected to the incoming data signal, fi, and the output signal fo of frequency divider 16. The output of EXCLUSIVE-OR 329 is high whenever fo and fi are out of phase. The output of EXCLUSIVE-OR 329 is connected to a multiple-input AND gate 331. AND gate 331 is also connected to both the output of flip-flop 303, which represents the composite clock signal E divided by 4, (E/4), and the output of divider 310. The outputs of divider 310 provide a pulse aligned about fo and are used to insure that the results of the comparison of fi and fo are clocked through AND gate 331 free of fo jitter. If fo and fi are out of phase, the output of EXCLUSIVE-OR 329 will go high and AND gate will allow the (E/4) signal to clock flip-flop 335.

If the output of EXCLUSIVE-OR 329 is low, AND gate 331 is turned off and no E/4 clock pulses will reach flip-flop 335.

Flip-flops 335, 337 and 339 are connected in conventional divider configuration 334 and provide an overflow output pulse every eight E/4 clocked clock pulses are accumulated. Flip-flops 321 and 323 are connected in well-known divider configuration. Flip-flops 321 and 323 are connected to the output signal, fo, of the digital phase-locked loop and provide an output signal at one-quarter the frequency of fo. Flip-flops 325 and 327 and EXCLUSIVE NOR gate 333 form an edge detector circuit clocked with the relatively higher frequency clock E/4. Therefore, the output of EXCLUSIVE NOR 333 includes a signal having a pulse appearing on every fourth edge of the divided output signal of the phase-locked loop. In other words, the output of EXCLUSIVE NOR 333 comprises a signal having a pulse appearing at a rate of fo/2. The output of EXCLUSIVE NOR 333 is used to reset divider 334. If fewer than 8 (E/4) clocked pulses have been accumulated during two cycles of the output, fo, of the digital phase-locked loop, divider 334 is reset and no overflow pulse is generated. In the preferred practice of the present invention, frequency divider 334 can overflow from 0 up to 4 times during two fo cycles.

The overflow pulses from divider 334 are used to clock divider 341. Divider 341 provides an output pulse whenever divider 334 produces 8 overflow pulses. When signals fo and fi are sufficiently out of phase, a significant number of clocked (E/4) clock pulses are accumulated by dividers 334 and 341. The overflow pulses from divider 341 are used to clock and lock flip-flop 351, which is the input to the lock detector latch circuit 350. The lock detector latch circuit 350 accumulates overflow pulses, S, from divider 341 and indicates whether the digital phase-locked loop is in a locked state. The latch detector latch circuit 350 is controlled by signals P and R, which are the outputs of the EXCLUSIVE-OR gates 352 and 354, respectively.

Signals P and R are generated by divider 343 and a double edge detector formed by flip-flops 345, 347 and 349 and an EXCLUSIVE-NOR gate 354 and EXCLUSIVE-OR gate 352. Frequency divider 343 is connected to the output of EXCLUSIC-NOR 333, which is a pulsed signal having a frequency of fo/2. Divider 343 provides an output pulse every 512 fo pulses. The output of divider 343, referred to as signal O, has a frequency of about 11.7 MHz in the preferred practice of the present invention. Flip-flops 345, 347 and 349 are connected in a shift register configuration clocked by the (E/4) clock signal. EXCLUSIVE-OR 352 produces a pulse that appears on each edge of the signal O pulse. EXCLUSIVE-NOR 354 produces a pulsed output signal R that is identical in frequency to signal P but delayed therefrom. As previously mentioned, the various clock signals of the lock detector circuit 22 are shown in Figure 3c, which will be referred to alternately by the designations shown in Figure 2b.

Referring now to the latch detector latch circuit 350 of Figure 2b, flip-flop 351 forms the first stage of the latch detector latch circuit. When a pulse appears in the signal S, flip-flop 351 is latched and signal T is set high. Signal T will remain high until flip-flop 351 is reset by signal R. If no signal S overflow pulse has latched flip-flop 351, signal T will remain low. Flip-flop 351 is reset with a delayed signal R, so if no overflow pulses are received, signal T will remain inactive. If signal T is inactive, the following C clock pulse will clock flip-flop 353 and cause signal U to go high. The high signal pulse U is clocked by the C clock into the flip-flop 357, causing signal W to go high. A logic high state in signal W indicates that the digital phase-locked loop is in a locked state.

As soon as signal W is driven high, signal V is driven low. Signal V clocks flip-flop 357, so flip-flop 357 is turned off when signal V is latched low. Whenever W is latched high, signal W is forced to latch low. When the When the latch detection signal W is active and the last signal S segment, signal U, did not indicate a latch condition, flip-flops 359 and 361 are not reset. Flip-flops 359 and 361 will count C clock pulses as long as they are not reset. The output of flip-flop 361 is used to reset flip-flop 357 and causes signal W to indicate an unlatched condition. Therefore, two consecutive signal S unlatched indications must occur to reset the latch indication signal W. Additional divider stages can be combined with flip-flops 359 and 361 to provide the ability to request additional unlatched indication pulses needed for an unlatched indication.

In summary, an improved digital multi-frequency phase-locked loop circuit has been described. The digital multi-frequency phase-locked loop uses common circuitry to make frequency and phase adjustments in the digital phase-locked loop. The preferred practice of the present invention contemplates the use of a phase and frequency adjustment network to selectively combine a reference clock signal and a shifted reference clock signal or to selectively cancel pulses from the reference clock signal to produce a composite digital phase-locked clock signal. The operating center frequency of the digital phase-locked loop is programmably controlled by periodically adding shifted reference clock pulses to the reference clock signal at a rate determined by the programmable clock signal. The digital multi-frequency phase-locked loop can be used as a tone demodulator by adding a lock detection circuit. The digital multi-frequency phase-locked loop can be programmed to operate at a known frequency. If the lock detection circuit indicates a lock condition in the digital lock loop, a known frequency within the loop bandwidth has been necessarily detected. The digital multi-frequency phase-locked loop could also be used as a multi-tone demodulator by programmed sequential shifting of the digital multi-frequency phase-locked loop's operating frequency between the required frequencies.

Claims (7)

1. Digital multi-frequency phase-locked loop (DPLL) for processing a received signal and producing an output signal that is phase-locked to the received signal, comprising: (a) a phase comparator device (18) having first and second inputs, the first input connected to the received data signal and the second input connected to the DPLL output signal, and an output for generating an output signal indicative of the relative phase between the incoming data signal and the DPLL output signal; (b) a clock generator device for generating a reference clock signal; (c) a programmable divider device (26, 28, 30) connected to the reference clock signal and having an output and programmable inputs for generating a programmable clock signal connected to the reference clock signal according to a ratio controlled by the programmable inputs; (d) digital means (101, 103, 105) connected to the output of said clock signal generating means and said means for generating a reference clock signal, for generating first and second clock signals, one of said signals being delayed with respect to the other; (e) phase and frequency adjustment means (12) connected to said means for generating a reference clock signal, for generating a composite clock signal by periodically, selectively adding or subtracting said first and second clock signals at a rate defined by said programmable clock signal to effect frequency adjustment, or by individually adding or subtracting pulses in response to said phase comparator output signal to effect phase adjustment; (f) frequency divider means (16) connected to the phase and frequency adjustment means for processing the composite clock signal to produce the output signal of the digital phase-locked loop. 2. A digital phase-locked loop according to claim 1, having a phase and frequency compensation network, wherein the multi-frequency phase-locked loop further comprises: (a) a first inverter device (191) having an input connected to the programmable inputs and indicating positive or negative frequency settings; (b) a first NAND gate device (193) having first and second inputs and an output, the first input connected to the programmable clock signal and the second input connected to the programmable inputs; (c) a second NAND gate device (203) having first and second inputs and an output, the first input connected to the programmable clock signal and the second input connected to the output of the first inverter device (191); (d) a first AND gate device (207) having first and second inputs and an output, the first input connected to the output of the second NAND gate device (203) and the second input providing an input in which the input indicates a positive phase setting; (e) a second inverter device (195) having an input and an output, the input being connected to the output of the first NAND gate device (193); (f) a third inverter device (205) having an input and an output, the input being connected to the output of the second NAND gate device (203); (g) a first flip-flop device (197) having delay and clock inputs and a non-inverting output, the delay input being connected to the output of the second inverter device (195) and the clock input being connected to the second derived clock signal; (h) a second flip-flop device (111) having delay and clock inputs and a non-inverting output, wherein the delay input is connected to the output of the third inverter device (205) and the clock input is connected to the first derived clock signal; (i) a third flip-flop device (211) having delay and clock inputs and a non-inverting output, the delay input being connected to the output of the first AND gate device (207) and the clock input being connected to the first derived clock signal; (j) a second AND gate device (201) having first and second inputs and an output, the first input connected to the output of the first NAND gate device (193) and the second input providing an input in which the input indicates a negative phase setting; (k) a fourth flip-flop device (209) having delay and clock inputs and a non-inverting output, the delay input being connected to the output of the second AND gate device (201) and the clock input being connected to the second derived clock signal; (l) a NOR gate device (215) having first and second inputs and an output, the first input being connected to the output of the second flip-flop device (111) and the second input being connected to the output of the third flip-flop device (211); (m) a first OR gate device (213) having first and second inputs and an output, the first input being connected to the output of the first flip-flop device (197) and the second input is connected to the output of the fourth flip-flop device (209); (n) a third NAND gate device (135) having first and second inputs and an output, the first input being connected to the second derived clock signal and the second input being connected to the output of the NOR gate device (125); (o) a fourth NAND gate device (113) having first and second inputs and an output, the first input being connected to the first derived clock signal and the second input being connected to the output of the first OR gate device (213); and (p) a fifth NAND gate device (217) having first and second inputs and an output, the first input being connected to the output of the third NAND gate device (135) and the second input being connected to the output of the fourth NAND gate device (113), and the output comprising the output of the phase and frequency adjustment network. 3. The apparatus of claim 2, wherein a bandwidth adjustment can be performed by applying a reduced clock rate to the third and fourth flip-flop devices, respectively. 4. Method for performing phase and frequency adjustments in a digital multi-frequency phase-locked loop comprising a phase comparator with data and loop inputs and a phase and frequency adjustment network with a composite output signal, the method comprising the following method steps: (a) generating a reference clock signal; (b) generating a clock signal programmably divided from the reference clock signal according to a division ratio controlled by a first programmable signal; (c) generating a derived clock signal and a shifted derived clock signal from the programmably divided clock signal, the derived clock signal and the shifted derived clock signal operating at the same frequency and having a relatively small duty cycle, the shifted derived clock signal being shifted in a time-delayed relationship to the derived clock signal; (d) inputting to the phase and frequency adjustment network a second programmable signal indicative of positive or negative frequency shifts, and inputting a third programmable signal comprising the output signal generated by the phase comparator and indicative of positive or negative phase shifts, the third programmable signal being based on a phase comparison between the data and loop inputs; and (e) generating a composite clock signal by selectively, periodically combining or subtracting the reference clock signal and the shifted, derived clock signal at a rate determined by the programmable divided clock signal to perform frequency adjustments, and by selectively combining or subtracting the derived clock signal and the shifted derived clock signal on a single pulse basis and independently of the frequency adjustments to perform phase adjustments, the composite clock signal comprising the composite output signal of the phase and frequency adjustment network. 5. The method of claim 4, wherein the phase adjustments are delayed if a frequency adjustment is currently being performed. 6. The method of claim 4 or 5, wherein the programmably divided clock signal generating step depends on a plurality of programmable inputs to produce a frequency control. 7. Method according to one of claims 4 to 6, wherein the number of phase adjustments performed per phase comparison is variably increased or decreased depending on programmable input signals in order to perform an adjustment in the bandwidth of the phase-locked loop.