DE3485885D1 - DIGITAL PHASE BAR LOOP FOR MULTIPLE FREQUENCIES. - Google Patents
DIGITAL PHASE BAR LOOP FOR MULTIPLE FREQUENCIES.Info
- Publication number
- DE3485885D1 DE3485885D1 DE8585900442T DE3485885T DE3485885D1 DE 3485885 D1 DE3485885 D1 DE 3485885D1 DE 8585900442 T DE8585900442 T DE 8585900442T DE 3485885 T DE3485885 T DE 3485885T DE 3485885 D1 DE3485885 D1 DE 3485885D1
- Authority
- DE
- Germany
- Prior art keywords
- digital phase
- multiple frequencies
- phase bar
- bar loop
- loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/662—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by adding or suppressing pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
- H03L7/0993—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US56772584A | 1984-01-03 | 1984-01-03 | |
US06/567,724 US4573017A (en) | 1984-01-03 | 1984-01-03 | Unitary phase and frequency adjust network for a multiple frequency digital phase locked loop |
US06/567,714 US4617520A (en) | 1984-01-03 | 1984-01-03 | Digital lock detector for a phase-locked loop |
US06/567,715 US4574243A (en) | 1984-01-03 | 1984-01-03 | Multiple frequency digital phase locked loop |
PCT/US1984/002133 WO1985003176A1 (en) | 1984-01-03 | 1984-12-31 | Multiple frequency digital phase locked loop |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3485885D1 true DE3485885D1 (en) | 1992-09-24 |
DE3485885T2 DE3485885T2 (en) | 1993-02-04 |
Family
ID=27536352
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585900442T Expired - Fee Related DE3485885T2 (en) | 1984-01-03 | 1984-12-31 | DIGITAL PHASE BAR LOOP FOR MULTIPLE FREQUENCIES. |
Country Status (2)
Country | Link |
---|---|
KR (2) | KR940002451B1 (en) |
DE (1) | DE3485885T2 (en) |
-
1984
- 1984-12-31 DE DE8585900442T patent/DE3485885T2/en not_active Expired - Fee Related
- 1984-12-31 KR KR1019930701544A patent/KR940002451B1/en not_active IP Right Cessation
- 1984-12-31 KR KR1019930701543A patent/KR940002450B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE3485885T2 (en) | 1993-02-04 |
KR940002451B1 (en) | 1994-03-24 |
KR940002450B1 (en) | 1994-03-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |