DE3484542D1 - Fehlerausrichtungssteuerungssystem und -schaltungen. - Google Patents

Fehlerausrichtungssteuerungssystem und -schaltungen.

Info

Publication number
DE3484542D1
DE3484542D1 DE8484102533T DE3484542T DE3484542D1 DE 3484542 D1 DE3484542 D1 DE 3484542D1 DE 8484102533 T DE8484102533 T DE 8484102533T DE 3484542 T DE3484542 T DE 3484542T DE 3484542 D1 DE3484542 D1 DE 3484542D1
Authority
DE
Germany
Prior art keywords
circuits
control system
alignment control
fault alignment
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484102533T
Other languages
English (en)
Inventor
Shanker Singh
Vinjendra P Singh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3484542D1 publication Critical patent/DE3484542D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
DE8484102533T 1983-03-24 1984-03-09 Fehlerausrichtungssteuerungssystem und -schaltungen. Expired - Fee Related DE3484542D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/478,594 US4534029A (en) 1983-03-24 1983-03-24 Fault alignment control system and circuits

Publications (1)

Publication Number Publication Date
DE3484542D1 true DE3484542D1 (de) 1991-06-13

Family

ID=23900556

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484102533T Expired - Fee Related DE3484542D1 (de) 1983-03-24 1984-03-09 Fehlerausrichtungssteuerungssystem und -schaltungen.

Country Status (4)

Country Link
US (1) US4534029A (de)
EP (1) EP0120371B1 (de)
JP (1) JPS6024659A (de)
DE (1) DE3484542D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5067105A (en) * 1987-11-16 1991-11-19 International Business Machines Corporation System and method for automatically configuring translation of logical addresses to a physical memory address in a computer memory system
US5809043A (en) * 1996-10-08 1998-09-15 Ericsson Inc. Method and apparatus for decoding block codes
WO1999064953A1 (en) * 1998-06-08 1999-12-16 Intel Corporation Redundant form address decoder for cache system storing aligned data
US6341327B1 (en) 1998-08-13 2002-01-22 Intel Corporation Content addressable memory addressable by redundant form input
US6172933B1 (en) 1998-09-04 2001-01-09 Intel Corporation Redundant form address decoder for memory system
US6678836B2 (en) * 2001-01-19 2004-01-13 Honeywell International, Inc. Simple fault tolerance for memory
FR2854747A1 (fr) * 2003-05-09 2004-11-12 St Microelectronics Sa Dispositif et procede d'addition-comparaison-selection- ajustement dans un decodeur

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3812336A (en) * 1972-12-18 1974-05-21 Ibm Dynamic address translation scheme using orthogonal squares
JPS5721799B2 (de) * 1975-02-01 1982-05-10
US4047163A (en) * 1975-07-03 1977-09-06 Texas Instruments Incorporated Fault-tolerant cell addressable array
US4051354A (en) * 1975-07-03 1977-09-27 Texas Instruments Incorporated Fault-tolerant cell addressable array
US4191996A (en) * 1977-07-22 1980-03-04 Chesley Gilman D Self-configurable computer and memory system
JPS5562594A (en) * 1978-10-30 1980-05-12 Fujitsu Ltd Memory device using defective memory element
US4441170A (en) * 1980-09-30 1984-04-03 Intel Corporation Memory redundancy apparatus for single chip memories
US4355376A (en) * 1980-09-30 1982-10-19 Burroughs Corporation Apparatus and method for utilizing partially defective memory devices
US4389715A (en) * 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
US4450559A (en) * 1981-12-24 1984-05-22 International Business Machines Corporation Memory system with selective assignment of spare locations
US4459685A (en) * 1982-03-03 1984-07-10 Inmos Corporation Redundancy system for high speed, wide-word semiconductor memories
US4489403A (en) * 1982-05-24 1984-12-18 International Business Machines Corporation Fault alignment control system and circuits

Also Published As

Publication number Publication date
JPS6024659A (ja) 1985-02-07
JPS6326418B2 (de) 1988-05-30
EP0120371B1 (de) 1991-05-08
EP0120371A2 (de) 1984-10-03
US4534029A (en) 1985-08-06
EP0120371A3 (en) 1988-03-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee