DE3445723C2 - - Google Patents

Description

The invention relates to a device for compensating Shades assigned to an original reader according to the preamble of claim 1.

Such a device for compensating shades is known from US-PS 38 00 079. With this known device can compensate for shades by one white surface of a template reflected light to form a shading characteristic can be evaluated. The well-known Device contains a photoelectric converter to convert the originating from the white surface of a template Light into corresponding video signals, these video signals initially integrated in a charging current integration stage will. The integrated signal is then via a differential amplifier led and from there to a divider circuit, their division number over a parallel Circuit is adjustable. The division number of the divider circuit can over the parallel circuit so  can be set to a video signal by the shading characteristic to share.

The parallel circuit contains an analog / Digital converter to the integrated video signal, which has been read from a white surface, an A / D conversion to undergo. The digital signal obtained in the process is stored in a memory circuit so that the memory content of the memory circuit has a shading characteristic can play. At the output of the memory circuit a digital / analog converter is connected, which is an analog output signal corresponding to the memory content delivers which in a zoomer amplifier too is summed with a reference voltage signal. That way received sum signal goes directly to the divider circuit, to set the division number, but also comes to the aforementioned differential amplifier, which at the output of the Integration stage is switched on. In this known circuit arrangement is the analog / digital converter in the above Parallel circuit included.

From US-PS 31 87 323 is an automatic scale generator known for an analog / digital converter. According to one Embodiment of this known scale former is in parallel to the input of an amplifier circuit a voltage divider network switched, which consists of several resistance combinations exists, each with the help of a controllable switch device to be connected to ground can. So here are several resistance combinations jointly connected on one side to ground, so that the Voltage division ratio of the arrangement changed accordingly can be.  

From DE-OS 32 29 586 is a device for balancing of shades in connection with an original reader known that an image reading station with a white Reflective surface with even reflection factor distribution contains. The known device also includes one photoelectric converter to convert the from the reflector originating light in corresponding video signals, further storage means for storing signals stored in Relationship to the video signals from the photoelectric converter stand and a digital / analog converter. The well-known Circuit arrangement essentially serves video signals gain and with the help of shutdown compensation coefficients to correct that in a memory circuit are saved.

From the Steinbuch, K., Taschenbuch der Message processing, Berlin / Göttingen / Heidelberg 1962, Springer-Verlag, pages 768-773 is a circuit arrangement known with several resistors arranged in parallel, each connected in series with its own switch are. The common connection point of the resistors is with an input terminal of a summing amplifier connected, which also has a feedback resistor.

Finally, from Schilling, D., Belove, Ch., Electronic Circuits, 2nd ed., New York 1979, MacGraw-Hill Book Company, pages 706-717, the principle of one Digital / analog converter known, in which the inverting Input connection a parallel connection of several Resistors is turned on, these resistors selectively switched out of the parallel connection and can be connected to ground at one end.  

An electrical solution to compensate for shades is, for example, the system described in Japanese Patent Application Laid-Open No. 55-79 567/1980. This system is designed such that a calibration signal generated by a flat white reflector is stored in a digital memory to divide a video data output from a solid state image sensor by an output signal from the digital memory. Such a conventional system is described below with reference to Figs. 1, 2A and 2B.

In Fig. 1, 2A and 2B, the reflected light via a mirror 14 and a lens assembly 16 to a solid-state image sensor 18 when a light source 10 is scanned a white reflector 12, fed. The data which corresponds to one line of an original 20 and which have been generated by the image sensor 18 represent a shading characteristic especially for the original reader and are used as a calibration signal. A switch 22 is connected to a terminal a so that the calibration signal is digitized by an analog-digital (AD) converter 24 and then stored in a digital memory 26 . When the original 20 is to be scanned, the switch 22 is connected to a connection b instead of connection a . The image sensor 18 detects a video signal fi from the light, which has been emitted by the light source 10 , which has scanned the original 20 , and which has then been reflected by the reflector 12 . The video signal fi is applied by the image sensor 18 to a dividing circuit or to a divider 28 .

Details of divider 28 are shown in FIG. 2A, while associated equivalent circuit is shown in FIG. 2B. The video signal fi is converted by a dividing network from an input resistor Ri , a feedback resistor Rf and an inverting amplifier 30 into a video signal fo ' = (Rf / Ri) fi . The divided video signal is inverted by an inverting amplifier 32 to become a signal fo = - fd = (Rf / Ri) fi . The feedback resistor Rf is variable for calibration in accordance with a digital signal fs . The feedback resistor Rf is created by a resistance value of a digital-to-analog (DA) converter 34 . This DA converter 34 has a number of switches S ₁ to S _n , which are actuated by corresponding bit components of the digital signal fs , resistors R ₁₁ to R _{1 n} , each having a resistance value of 2 R , and resistors R ₂₁ to R _{2 n -1} , each of which has a resistance value R. If now the respective bit components of the digital signal fs A ₁, A ₂,. . . A _n , the feedback current I _{f can be} expressed by:

Thus the feedback resistance value Rf is generated by:

If Ri = R , the following applies

As a result, when the gain of the inverting amplifier 32 is "1":

The denominator of the right term of Eq. (4) are 1 (one) when the digital input fs is the maximum, and are less than 1 when it is different. It follows that the output video signal fo is proportional to the digital calibration signal fs , and consequently a video signal with a balanced shading component is achieved.

With the help of the above fundamental considerations, the conventional system shown in FIGS. 1, 2A and 2B offers accurate shading compensation over a wide dynamic range. However, some difficulties remain unsolved. Since the circuit node is the inverting input of the inverting amplifier, the instantaneous voltage is amplified during the switching of the switches S ₁ to S _n and appears on the output side. It takes a considerable time for such an instantaneous voltage to converge because amplifier 30 has an operational amplifier, ie the impedance at the inverting input is high.

Another difficulty with the system described above is that fast sampling is not possible due to the fact that the crosstalk of the digital calibration signal fs at the inverting input, by which the switches S 1 to S _{n are} switched off, is amplified on the output side appears.

The object underlying the invention is a device for balancing the shades of the to create specified genus that with simple circuitry Build a balance of shades for a document reader at high speed.

This object is achieved by the in the labeling part of the features listed solved.

Particularly advantageous refinements and developments the invention result from subclaims 2 and 3.

In the following, the invention is based on exemplary embodiments explained in more detail with reference to the drawing.  

Fig. 1 is a block diagram of a conventional device for compensating shades, the device being associated with an original reader;

Figs. 2A and 2B is a detailed circuit diagram of a divider which is provided in the apparatus of Figure 1 and a diagram showing the equivalent circuit.

3 is a block diagram of an apparatus for compensating for an original reader shades with features according to the invention.

Fig. 4 is a circuit diagram showing details of a divider provided in the device of Fig. 3;

Fig. 5 is a circuit diagram showing details of an A / D converter of Fig. 3, and

Fig. 6 is a circuit diagram of another embodiment of the divider shown in Fig. 3.

In Fig. 3 to 5 a designated in its entirety by 40 means for equalizing of shades is shown with features according to the invention. FIG. 3 shows a light source 10 , a white reflector 12 , a mirror 14 , a lens arrangement 16 , a solid-state image sensor 18 and a template 20 , which are the same as the elements shown in FIG. 1 and therefore also have the same reference numerals are designated. As shown, the device 40 includes a DC regeneration circuit 42 to remove a DC component from a video signal output by the image sensor 18 , a dividing circuit 44 , a background sensor 46 to hold, as a reference level REF, the maximum value of white levels which are related of the white reflector 12 are provided, an A / D converter 48 and a digital memory (RAM) 50 , which is supplemented by a digital memory for storing a signal to compensate for shades. Digital memory 50 is switched to write mode when a store command STORE (logic) is "1"; it is switched to read mode when this command is "0".

In the embodiment described above, when the light source 10 scans the white reflector 12 for the first time, the reflected light is directed through the mirror 14 and the lens arrangement 16 onto the image sensor 18 . The resulting data, which are output by the image sensor 18 and correspond to one line of the original 20 , represent a shading characteristic, in particular for the reader, and are used as a shading calibration signal. The output of the image sensor 18 is a signal containing a DC component and is not applied to the divider circuit 44 until the DC component has been removed by the regeneration circuit 42 .

In FIG. 4, the divider circuit is shown in a preceding detailed block diagram 44th The divider circuit 44 has an operational amplifier Ao , a feedback resistor Rf with a resistance value of 31 R and a series connection of bit-weighted input resistors R , 2 R , 4 R , 8 R and 16 R. The feedback resistor Rf and the series circuit comprising the input resistors R to R 16 are connected to an inverting input of the operational amplifier A. Controllable switching elements S ₀ to S ₃ are connected in parallel with the resistors R , 2 R , 4 R and 8 R. The switching elements S ₀ to S ₃, which have, for example, field effect transistors (FET), are driven by NOR gates NOR ₀ to NOR ₃, so that each of them can be switched off when the STORE memory command or one of the bit inputs b ₀ to b ₃ of the digital output of the assigned digital memory (RAM) 50 is "1".

While the light source 10 scans the white reflector 12 , the store command STORE is "1", and consequently all switching elements S ₀ to S ₃ are switched off. Under this condition, the gain G of the divider 44 can be expressed as G = 31 R / (R + 2 R + 4 R + 8 R + 16 R) = 1. That is, while the light source 10 is scanning the reflector 12 , the video signal that has been applied from the DC regeneration circuit 42 to the divider circuit 44 is passed directly to the background sensor 46 and the A / D converter 48 . The background sensor 46 holds the maximum white level, which has been reflected by the reflector 12 , as a reference level REF and applies it to the A / D converter 48 .

As shown in detail in Fig. 5, the A / D converter 48 has operational amplifiers A ₁ to A ₁₅, a latch 52 , an encoder 54 to convert a 15-line input to a 4-line output, one Inverter 56 , a switch S ₄ and resistors R and 16 R on. In this embodiment, when the store command STORE is "1", the switch S ₄ is turned off. Then the operational amplifiers A ₁ to A £ §, the locking element 52 and the encoder 54 set 50 to 100% of the reference level REF , which has been applied by the background sensor 46 , by means of the sixteen resistors R and 16 R into a digital 4-bit Value around, which is formed from bits b ₀ to b ₃. The 4-bit digital value is written into the digital memory (RAM) 50 as a digital signal for shading calibration. A white waveform sensitivity S at any sample point on the reflector 12 can be expressed in terms of a value related to the reference level REF , which is the maximum white level:

The bits b ₀ to b ₃ create a binary value, the least significant bit (LSB) b ₀ and the most significant bit (MSB) is b ₃. In this way, a digital signal for shading calibration is stored in the random access memory (RAM) 50 , which is created by scanning the white reflector 12 over an area that corresponds to a line of the original 20 .

The shading compensation operation in the illustrated embodiment will now be described. The store command STORE is made "0" at this time, whereby the switch S ₄ of the A / D converter 48 is turned off in order to condition the digital memory (RAM) 50 for a read operation. The one line of a white waveform sensitivity S , which is stored in the digital memory 50 , is now read out from this and immediately synchronized with a scanning of the template 20 to the NOR gates NOR ₀ to NOR ₃ of the divider circuit 44 . If the store command STORE is "0", the switch elements S ₀ to S ₃ of the divider circuit 44 are switched on and off in dependence on the values of the bits b ₀ to b ₃ of the binary input assigned to them, ie the calibration signal, thereby causing a sensitivity of Divider circuit is set. If now one of the switching elements S ₀ to S ₃, which is assigned to one of the bits b ₀ to b ₃, which is "1", is switched off and the switching element which is assigned to the bit, which is "0", is switched on, the gain Gv of the divider circuit 44 is given by:

Thus, the sensitivity of the divider circuit 44 or the relationship between the input and output levels is the product SGv of the aforementioned white waveform sensitivity S and the gain Gv when the white reflector 12 is scanned. The product SGv is then as follows:

This confirms that shading is complete is balanced.

In the A / D converter 48 of FIG. 5, the reason why the switch element S ₄ is turned off when the store command STORE is "1" is because the white waveform sensitivity is in a range from 50 to 100% of Reference level REF scatters, it is unnecessary to subject the sensitivity range from 0 to 50% to an A / D conversion. This is effectively used in the present invention. Particularly since the required range of A / D conversion is only 50 to 100% of the reference level REF , a 4-bit A / D converter successfully offers a resolution of essentially five bits. Among the input resistances of the divider circuit 44 , the resistance of the resistor 16 R , which is connected to the input of the operational amplifier A ₀, must be fixed and must not be switched on or off by a switch in parallel with it. The fixed resistor 16 R creates a gain of 31/16, namely at the junction A between the resistors 8 R and 16 R of the divider circuit 44 of FIG. 4, so that even if crosstalk from the digital inputs b ₀ to b ₃ may be present, it is only doubled at the maximum, so that noise and instantaneous voltage due to switching the switch elements S ₀ to S ₃ on and off in practice become negligible.

The number of switch elements S ₀ to S ₃ or the number of input resistors connected in series, which have been shown and described, do not constitute a limitation, but are only used for explanation; this also applies to a further embodiment, which will be described below.

FIG. 6 shows the further embodiment of the divider circuit described with reference to FIG. 3. The divider circuit 44 a corresponds essentially to that of FIGS. 3 to 5, except that values which are assigned to the input resistance parts of the divider circuit 44 a are different and are not the same as those of the divider circuit 44 of FIG. 4. In general, the input resistance and the feedback resistance of a divider affect the response characteristics of the divider; the smaller the resistance values, the higher the response. A difficulty, however, is that reducing the input resistance and / or the feedback resistance creates a substantial resistance value when the switch elements S ₀ to S ₃ are turned on, and also causes gain errors. For example, in Fig. 4, even when the switching element S ₀ has been turned on, the resistance value, which should be 0 ohms, becomes γ ₀ R / ( γ ₀ + R) under such a condition, where γ ₀ is the "turn on" resistance value of the switch element S ₀. This resistance value cannot be set to a relationship R ⟩⟩ γ ₀. If field effect transistors are used for the switch elements S ₀ to S ₃, the resistance value γ ₀ becomes large enough to create a non-negligible state.

In the embodiment shown in FIG. 6, gain errors due to the fact that the resistance value γ ₀ arises when the switch elements are turned on are compensated for as will be described below. The fixed resistor, which is connected to an input of the operational amplifier A ₀, is compensated for a value R ₅, which is smaller than the fixed resistance value 16 R , and vice versa, the resistors, which are the resistors R , 2 R , 4 R and 8 R in accordance with the Fig. 4, balanced so that they are larger than the latter. The resistances are balanced according to the following equations:

The resistance values R ₁ to R ₅ are obtained by first setting the value R and then solving the quadratic equations. For the resistor R ₁, the following is obtained by reducing the equation:

When R ₁ = 1000 Ω and γ ₀ 100 Ω, the resistance of the resistor R ₁ is 1091.6 Ω. The resistance value of R ₅ is then calculated using Eq. (9) derived from the resistance values R ₁ to R ₄.

It will now be briefly described how, in order to create the aforementioned equations associated with the resistors R ₁ to R ₃, the resistance R ₃ can be obtained from the condition that the sum of the resistances of the respective switch parts and the resistance R ₅, which arises when all switches S ₀ to S ₃ are switched on, is equal to the resistance value 16 R. This means:

This results in:

The resistance value R ₁ can be obtained from the condition that the total input resistance 17 R is when only the switch element S ₀ is open; the resistance value R ₂ results from the condition that the total input resistance is 18 R when only the switch element S ₁ is open; the resistance value R ₃ results from the condition that the total input resistance is 20 R when only the switch element S ₂ is open, and the resistance value R ₄ results from the condition that the total input resistance is 24 R when only the switch element S ₃ is open. With regard to the resistance value R ₁, the following results, for example:

By substituting the value that has been generated as the value R ₅ and rearranging the equation, the equation described above is then obtained:

By selecting the input resistance values R ₁ to R ₅, as described above, gain errors due to resistance values can be successfully excluded, which are due to the switching on and off of the switch elements S ₀ to S ₃, while at the same time the fast response characteristic of the divider circuit is further increased, which then enables the reader to be scanned at high speed.

The invention thus creates a device which automatically and accurately compensates for shades; at the same time is the influence of an instantaneous tension or crosstalk of a switching signal as a result of a switching process, which occurs during the equalization, and the scanning process is an original reader by increasing the responsiveness of a divider accelerates.

Claims (3)

1. Device for compensating for shades, which are assigned to an original reader, with a white reflector, which is arranged in an image reading station in the original reader, with a photoelectric converter for converting the light coming from the white reflector into corresponding video signals, with a divider circuit, which receives the video signals at their input and the division number thereof is adjustable to divide a video signal by the shading characteristic with an analog-to-digital converter to A / D convert the video signal read from the white reflector , and with a digital memory for storing the shading characteristics in digital form, characterized in that

• a) the analog / digital converter ( 48 ) is arranged in the useful signal circuit and behind the divider circuit ( 44 ),
• b1) the divider circuit ( 44 ) contains an operational amplifier (A ₀) with a feedback resistor (Rf) between the output terminal and the inverting input terminal,
• b2) the divider circuit ( 44 ) contains a series circuit comprising a number of bit-weighted input resistors (R -8 R) which are connected to the inverting input terminal of the operational amplifier (A ₀),
• b3) each of the bit-weighted input resistors (R -8 R) of the divider circuit ( 44 ) can be bridged by a controllable switching element (S ₀- S ₃), and
• b4) the switching elements (S ₀- S ₃) are each assigned to an output of the digital memory ( 50 ) and can be controlled by this in order to set the number of divisions of the divider circuit ( 44 ) in accordance with the memory content of the digital memory ( 50 ).

2. Device according to claim 1, characterized in that the divider circuit ( 44 ) has at least one bit-weighted input resistor (16 R) , which is not equipped with a switching element. 3. Device according to claim 1 or 2, characterized in that the resistance value of each of the bit-weighted input resistors (R to 8 R) of the dividing circuit ( 44 ) is selected to compensate for a resistance value which arises when the associated switching element is switched on.