DE3438855A1 - Method for evaluating traffic in digital transmission systems - Google Patents

Abstract

The invention relates to a method for evaluating the traffic in digital transmission systems with pulse code modulation, the transmission frame containing a number of time channels comprising useful channels, a signalling channel, a synchronisation channel and a message channel, an 8-bit binary word being transmitted in each time channel which is coded according to the respective sampled level value for a speech channel according to CCITT Recommendation G.732 in a symmetrical dual code with decreasing bit value according to either the A-Law or mu -Law coding specifications, and is characterised in that the 8-bit binary word of a useful speech channel is compared bit by bit with the word for the level value 0, in that the evaluated useful channel is regarded as unoccupied if correspondence occurs in r consecutive frames and as occupied if no correspondence occurs, r being predefinable. The method enables accurate traffic evaluation, speech pauses of a specific predefinable length being evaluated as non-traffic. Background line noise can also be taken into account by the method by including only the middle part of the 8-bit binary word (e.g. a 5-bit window) in the comparison, only an insignificant, negligible error occurring in the case of a 5-bit window width. A low-cost circuit arrangement to carry out the method is shown in Figure 2. <IMAGE>

Description

Procedure for recording traffic in digital

Carrying systems The invention relates to a method for detection of the traffic in digital transmission systems according to the preamble of the claim 1.

For the tariffing of permanently switched leased lines of the Germans Bundespost is recently provided, the fees from the period of use or to make dependent on the occupancy. For this it is necessary to check the traffic times to eat.

Such traffic recording is also required in PCM systems such as PCM 30 necessary. In such a system, 30 telephone signals are digitized, encoded, in a time frame according to the CCITT recommendation G.732 and transmitted.

The coding rule p-Law applies to America and the coding rule applies to Europe A-Law, on which the rest of the text is based. However, the same also applies accordingly for u-law.

The coding rule according to the above recommendation states that the 256 quantization intervals (8-bit) are represented in a symmetrical dual code with decreasing significance of the bits and with inversion of every second bit according to the following table: @ Bit position - 1 2 1 3 4 it 5 s 6 1 7 1 8 Regulation ni 1 ni 1 ni 1 1 ni It means n = not inverted and i = inverted. The bits of time channels 0 and 16 remain unaffected by the inversion. If a user channel is provided for the transmission of digital signals, then this coding rule is also not applicable for these bits. Bit 8 has the lowest value, the highest value bit number 1 has the function of the so-called polarity bit, its polarity reflects the polarity of the signal that has just been scanned.

The word of an unoccupied voice channel, i.e. a channel without information content, thus has the binary value 01010101.

The present invention was based on the following object To specify procedures of the type mentioned above, which allow in an inexpensive way, the voice traffic in a PCM system per transmission frame and for each individual To capture voice channel.

The solution takes place with those specified in the characterizing part of claim 1 Features. The subclaims 2 to 4 contain optimal configurations of the method. Claims 5 to 7 provide a circuit arrangement for carrying out the method on, wherein the circuit arrangement according to claim 6 is an embodiment with simple Switching means represents.

The comparison method according to the invention requires little effort. The comparison with the binary word 01010101 in all bits is then possible and correct, if there are ideal line conditions with a noise level of less than 80 dBm. However, there are also lines that have a higher background noise, which means that the least significant bit or bits different from 0 Can accept value. The sign bit (1) is also given different ones Values. In order to be able to carry out a comparison even under such conditions, is proposed according to dependent claims 2 and 3, the two outermost bits or the The last n bits should not be included in the comparison. For example only bits 2 to 6 are included in the comparison, which is then with a bit pattern 10101 are compared, only a very small detection error in Taken, the value of which corresponds to a signal level of -66 dBm. Such Acquisition is practically error-free because every PCM word is queried every 125 microseconds and is used to record traffic. Such a detection also corresponds a net acquisition, since pauses are hidden, whereby the pause length can be specified is by the number r consecutive transmission frames in which a match of examined PCM word with the above bit pattern is determined.

The invention will now be described with reference to the figures. the FIG. 1 shows a block diagram of a traffic sensor for direct traffic detection of telephone channels. FIG. 2 shows an embodiment of the memory Sp and the evaluation logic AL according to FIG. 1.

An 8-bit shift register SR can be seen in FIG. 1, in its data input the PCM bit stream is introduced, which is clocked with the bit clock TB of about 2 MHz and its parallel outputs are connected to the inputs of a comparator VG are. There is also a counter Z, which is also clocked by the bit clock which is synchronized by the word clock TW of 256 kHz, which is the first counts six bits and then supplies the comparator with a control pulse, see above that the comparison of the shift register functioning as a series-parallel converter SR stored last five bits number 2 to 6 with that stored in the comparator Bit pattern 10101 is carried out. The comparator output is connected to the input of the already mentioned memory Sp led with evaluation logic AL. If the comparison is negative, so the PCM word is counted as traffic.

However, a single positive comparison in a channel by no means means Non-traffic, because there are zero crossings in the speech signal. Only when several for example r = 3, positive comparisons will occur one after the other in the channel detected on non-traffic. This multiple evaluation is made with the help of the memory and its evaluation logic implemented. With such a sensor, the non-traffic times are therefore measured while the traffic counter is recorded. The acquisition can be channel-dependent or implemented independently of the channel. In the case of channel-dependent detection, the traffic counter must be advanced for each occupied channel. With channel-independent acquisition the traffic counter per PCM frame is determined to be occupied once the first time Channel advanced.

FIG. 2 shows an exemplary embodiment of the memory and the evaluation logic for r = 3. The memory consists of three shift registers SR1 to SR3 of each of length 30 bits.

The shift registers are clocked by the useful word clock TW ', at which interrupts the clocking of the time channels ZK 0 and ZK 16. At the entrance of the The register connected in series to a chain of shift registers is the output of the Comparator VG connected. The first parallel bit output of each of the three shift registers are connected to the three inputs of an AND element &, its negated Output operated a traffic counter VZ. With each new useful word cycle there are the comparison results of the corresponding voice channel to the three inputs of the AND gate of three consecutive PCM frames. Only if all three results non-traffic display, the traffic counter VZ is not actuated, otherwise it is traffic recognized. It is advisable to have a VZ between the AND element & and the traffic counter D flip-flop D-FF inserted, which is also clocked by the useful word clock TW ' will.

Claims (7)

Method for capturing traffic in digital Transmission systems with pulse code modulation, the transmission frame being a number Contains time channels, which are made up of useful channels, a signaling and a Put the synchronization and reporting channels together, and one in each time channel 8-bit binary word is transmitted, which is for a voice channel according to the recommendation CCITT G.732 in a symmetrical dual code with decreasing significance of the bits after a Coding rule is coded, with each sampled level value one after this Coding rule corresponds to coded 8-bit binary word, characterized in that the 8-bit binary word of a useful voice channel bit by bit with the word for the level value = 0 (| Der |, Zero, with the coding rule A-Law X1010101 and with the coding rule u-Law X1111111) is compared to the fact that the detected useful channel matches in r consecutive frames as unoccupied and, if they do not match, as occupied applies, where r can be specified is. 2. The method according to claim 1, characterized in that in the comparison the two outermost bits are not included. 3. The method according to claim 2, characterized in that in the comparison the last n bits are not included, where n can be specified as a function from the background noise level of the unoccupied useful channel, for example n = 2 for one Background noise level of <66 dBm. 4. The method according to any one of the preceding claims, characterized in that that the comparison is independent of the channel. 5. Circuit arrangement for performing the method according to a of claims 1 to 4, characterized in that a shift register (SR), a Comparator (VG), a memory (SP) with evaluation logic (AL) and a counter (Z) are provided are that at the input of the shift register clocked with one bit TB (SR) the bit stream to be detected is carried out, that the shift register (SR) has parallel outputs has, which are connected to the inputs of the comparator (VG) that the with the bit rate (TB) clocked, counting to the number of bits of the word length (Z) is started by a word clock (TW) and a control pulse at its output for the comparator (VG), which supplies the pending at its data inputs Compares bits with the given bit pattern, and that the comparator output is connected to the memory input (Figure 1). 6. Circuit arrangement according to claim 5, with r = 3, characterized in that that as a memory (Sp) three serially coupled, for the voice user channels with the Useful word clock (TW ') clocked shift registers (SR1 to SR3), each 30 bits long are provided, whereby the useful word clock (TW ') for time channels 0 and 16 (ZK16) does not contain a pulse that the first parallel output of the shift register (SR1 to SR3) are led to the inputs of an AND element (&), its negated Output is connected to the input of a traffic meter (VZ) (Figure 2). 7. Circuit arrangement according to claim 6, characterized in that A D flip-flop (F-FF) is inserted between the AND element (&) and the traffic counter (VZ) is clocked by the useful word clock (TW ').