DE3430711C2 - Frequency-to-voltage converter - Google Patents

Abstract

The invention relates to a frequency-voltage converter in particular as a high-precision tachometer, in which a ramp-shaped signal with a constant slope is generated from a clock signal determining the period with a variable, adjustable duty cycle, which is fed to a peak value memory with a discharge monitoring circuit and a low-pass filter. In this case, a signal enveloping the maxima of the ramp-shaped signal is generated, which is fed to an operational amplifier that forms the difference. At its output there is a voltage signal that is directly proportional to the frequency or speed.

Description

3 4

FIGS. 1 a - 1 d do not directly relate to the actual

object of the invention and are only used as decimal values of the ramp-shaped signal enveloping Si

standing aid intended for the invention. It shows gnalUcrp according to FIG. 3 generated

Fig. La a low-pass RC element with a ramp-This signal Uctp is inversely proportional

moderate input signal, 5 for frequency or speed, d. H. a great frequency

F i g. 1 b the clock signal t / 7-, or speed, which determines the period, generates a small voltage Uctp and

F i g. 1 c the output signal Uffi of the bistable toggle reversed

stage FF ₃ , in a downstream operational amplifier OP ₂

Fig. Id the input and output signal at the low according to Fig.2 becomes a frequency or speed

pass-RC element according to FIG. 1 a, 10 directly proportional output voltage Uoutganc 2

F i g. 2 a block diagram for a frequency voltage generator The operational amplifier is designed as a differential controller

voltage converter or tachometer, more heavily wired. The voltage Uctp is supplied via the

F i g. 3 the voltage curves of ramp signal Ur, resistor A ₅ fed to the negative input The off-voltage curve Ucsp at the storage capacitor, voltage output of the operational amplifier OP2 is fed back to the negative input via the winding curve i / cTP on the low-pass RC element, 15 derstand Rs

Fig. 4 a detailed block diagram of a Fre- The positive input is at the voltage divider tap A ₃

frequency voltage converter or. The tachometer is connected to the voltage divider Ri, Ra, which is connected to the

measured the block diagram of FIG. 2, constant supply voltage U _{8 is} fed.

Fig.5 the course of the output voltage the time course of the output voltage of the

OUTPUT! of the frequency-to-voltage converter or operational amplifier OP _{2 is} shown in FIG. The period

Tachometer according to FIG. 4 for a ramp duration is the same as in FIG. 3.

shaped signal according to FIG. 3, frequency-voltage converter, especially as a rotary

F i g. 6 shows the pulse diagrams of the frequency chip counter according to the detailed block diagram in the voltage converter or tachometer according to FIG. 4. Fig. 4 operate on the principle that a clock signal Ut with a variable, adjustable duty cycle low-pass RC element according to FIG. Ia not proportion in a transmitter circuit, not shown, is suitable From measurements and calculations, for example a Hall transmitter, is generated according to the fact that the output voltage according to FIG. Id at the low pass F i g. 1 b or 6a. Within each period, a con-RC member will not follow the Etynamik the ramp-shaped signal to the capacitor Cs from a 30 Konstantstroiiiquelle in a detection of the respective peak values of the ramp generator having a constant slope R gekann. load so that the respective period maxima of the output

The clock signal Ut shown in Fig.Ib determines the output signal Us a measure of the period or

Period duration of the ramp-shaped signal of constant frequency or speed are. For this purpose the clock signal

Slope and has a variable adjustable pulse duty factor 35 Ur through a bistable flip-flop FF3 with the fre-

nis. frequency divider ratio before / 2: 1 divided down and the

For this purpose, a frequency dividing bistable tilting Uffz output voltage of the bistable multivibrator FF ₃

stage FF ₃ with the frequency divider ratio of 2: 1 according to FIG. Ic and F i g. 6b discharges with every switching

Signal Uff ₃ generates the capacitor Cs of the ramp generator R with each switching edge of this Si edge

In a digital circuit, the ramp 40 is set to reference potential. At the exit of the ramp generator

nerators R discharge the capacitor Cr , as this the gate produces the signal Ur according to F i g. Id or 6a Zur

F i g. Id shows the storage of the peak of the ramp-shaped signal for each

In the case of the in F ii g. 2 for one of the periods is a storage capacitor Csp of a

Frequency voltage converter, in particular as a rotary charging circuit, consisting of a current source Q, a

counter, the clock signal U _{T of} the bistable Kipp- 45 ner diode D \ and a comparator K \ is loaded. Of the

stage FF3, at the output of which the signal Uff ₃ charging process continues until the ramp-shaped

arises. This signal is sent to the ramp generator R signal has reached its maximum In the comparator K \

with the capacitor Cr supplied, at the output of which there are ramp-shaped signals! that of the plus input

the ramp-shaped signal Ur according to FIG. 3 pending In is supplied and voltage is applied to the storage capacitor

a peak value memory SP with the memory con- 50 Csp, which is fed to the minus input of K _{1, with one-}

capacitor Csp , the peak values of the ramp conveyor are compared, and its output prevents the charging

The signal Ucsp, which stores a moderate signal, is generated according to the process on the storage capacitor when the ramper-

F i g. 3. shaped signal is smaller than the stored voltage

The clock signal i / r is also sent to a discharge over arn S,> eicherkondensator Csp. So that the memory

monitoring circuit, EU supplied, which by its logic 55 capacitor then not via the output of the compa-

recognizes when the signal Ucsp can discharge the dynamics of the Spit- rators K \ , is between the output of the

zenwerte of the ramp-shaped signal not to follow comparator Kt, to which also one connection of the

is able, as is the case, for example, in the 5th period T ₅ in Fig. 3 power source Q is connected, and the memory con-

This case occurs when the capacitor switches a diode D \ in such a way that its

ratio of the maximum of a period of the ramp-shaped cathode with a live connection of the

gen signal to the maximum of the immediately preceding storage capacitor Csp , whose other

pending period a fixed, adjustable percentage rer connection is at ground potential

The ratio falls below, for example, from grain The voltage across the storage capacitor Csp is on

For reasons of failure, this can be 70%. Positive pole one non-inverting op amp

The storage capacitor Csp of Spitzenwertspei- 65 OP \, whose Min'iseingang to its output to-

In this case, the discharge is fed back to the reference potential.

and in the subsequent period for the storage tion amplifier OPi is as large as the voltage on

the next peak width released again. Storage capacitor Ucsp and feeds a voltage

divider consisting of the three resistors R \, R ₂ and Ri with the voltage divider taps A \ and A ₂ and the associated voltages U _A ι and U _{A 2} . Furthermore, the output of the operational amplifier OPi is connected to one terminal of the resistor Rtp of a low-pass RC element, the terminal of which is connected to the time constant-determining capacitor C _T p , the other terminal of which is at ground potential

The voltage divider tap A \ is fed to the positive input of a second comparator K ₂ and the voltage divider tap Ai is fed to the negative input of a third comparator K _3. The ramp-shaped signal is fed to the minus input of the second and the plus input of the third! The outputs of the comparators Ki and K ₃ are each connected to an input of an AND gate C , the output voltage Uo of which is fed to a monostable multivibrator M \ . We also have this sign! fed to one input of an OR gate £, the output of which controls a discharge transistor Tan via a resistor A4, the collector of which is directly connected to the live connection of the storage capacitor Csp . The emitter of the discharge transistor is at ground potential.

If at the end of a period the voltage at the storage capacitor Csp is equal to the peak voltage value of the ramp-shaped signal, the charging process at the storage capacitor Csp via the comparator K \ is interrupted when the ramp signal breaks. The voltage of the storage capacitor Csp is then applied with graduated percentage values on the one hand to the positive input of the comparator K ₂ via the voltage divider tap A \ and on the other hand to the negative input of the comparator Ki via the voltage divider tap A ₂ . If the ramp-shaped signal in the following period from a certain point in time is smaller than the voltage applied to tap> \ 1 and higher than the voltage applied to voltage divider tap A ₂ , then a high level occurs at the output of AND gate G The input of the OR gate £ controls the discharge transistor Tan. This now discharges the voltage capacitor Csp. The duration of the discharge process is regulated. The voltage on the storage capacitor decreases very quickly due to the discharge process. Its instantaneous voltage Ucsp is also applied to the voltage divider R \, R ₂ and R ₃ via the operational amplifier OPi. After a relatively short time, the voltage U _A 1 at the voltage divider tap A \ is smaller than the instantaneous ramp-shaped voltage, which means that the comparator output from K _{2 is} at a logic low level and the output of the AND gate G is thus also on logic low level. The discharge transistor 7 is blocked. In this way, it is controlled by discharge pulses whose pulse width is regulated, so that the storage capacitor Csp is only discharged to the current value of the ramp-shaped signal within one period. The output of the comparator K \ then enables the current source Q for charging the storage capacitor Csp again for storing the new peak value.

The course of the ramp-shaped signal Ur and the voltage course Ucsp at the storage capacitor and at the output of the low-pass RC element for the case described are shown in FIG. 3 up to the 4th period and from the 7th period as well as the F i g. 6c up to the 2nd period and from the 7th period.

Cases are assumed in which the voltage Ucsp of the peak value memory can follow the dynamics of the voltage peaks of the ramp-shaped signal.

If in the following period the ramp-shaped signal remains lower than the voltage value present at the voltage divider tap A ₂ , the output of the comparator K _{3 is} at a logic low level, as is the output of the AND gate G. As a result, the discharge transistor T is not activated and the storage capacitor Csp maintains its voltage value constantly and can no longer follow the current peak values of the ramp-shaped signal.

To avoid this, a discharge monitoring circuit according to FIG. 2 and 4 have been developed for a peak value memory that does not have this decisive disadvantage.

In Fig.3 their basic mode of operation is shown. Through the discharge monitoring circuit, ift7t lifvn F.ntlaHptransistnr am F.nHe rlpr S. Pftrinrle in 4- - - - - ■ - - ■

F i g. 3 a pulse controlled in its pulse width is supplied, which discharges the storage capacitor Csp almost completely and then the storage capacitor is charged again to the peak value of the ramp-shaped signal and the voltage on the storage capacitor Cj / 'can now follow the dynamics of the peak values of the ramp-shaped signal again.

The Entladeüberwachungsschaltung according to Figure 4, there is a ^r ls a monostable multivibrator M \ an OR gate B, a frequency divider stage FF ₂ to the divider ratio of 2: 1, a differentiating circuit D, a further monostable multivibrator M _2, an AND gate C of a bistable Flip-flop FF \ and a further OR gate E

The output pulses Uc of the AND gate G , whose pulse width is regulated, are fed to a monostable multivibrator M] , where they are broadened to pulses of constant pulse width. The output pulses Um ι of the monostable multivibrator M \ are fed to one input of the OR gate B together with the clock signal Ut. Its output pulses Ub control the frequency divider stage FF ₂ with the division ratio 2: 1. The output signal Uffi of the frequency divider stage FF ₂ is fed to the differentiating element D , only its positive output pulses triggering the downstream monostable multivibrator M ₂ , so that pulses of constant pulse width arise at its output. These pulses Um ₂ are fed to one input of the AND gate C. The clock signal i / r is also fed to the set input S of the bistable multivibrator FFi , the reset input R of which is controlled by the output signal of the AND gate G. The output signal Uff ι of the bistable multivibrator FFi is fed to the other input of the AND gate C. Its output signal Uc controls the other input of the OR gate E , one input of which is controlled by the output signal Uc of the AND gate G. The output signal Ue of the OR gate E controls the discharge transistor T via the resistor R * . This is triggered by regulated or controlled pulses in their pulse width, depending on how it is necessary for reasons of the dynamics of the peak values of the ramp-shaped signal

In Fig. 6 are the detailed block diagram the F i g. 4 associated pulse diagrams are shown

F i g. 6a shows the time profile of an assumed clock signal Ut . The output signal Uff3, shown in FIG. 6b, of the bistable multivibrator FF3 with the frequency divider ratio of

2: 1. F i g. 6c shows the associated ramp-shaped signal Ur of the ramp generator R as well as the profile of the voltage on the storage capacitor Ucsp and the profile of the voltage at the output of the low-pass RC element Ucm F i g. 6d shows the course of the needle pulses Uc, whose pulse width is regulated, at the output of the AND gate C. In the third and fifth periods, these pulses cannot be formed in the peak value memory.

With its LOW / HIGH edge, the clock signal sets a flip-flop FFi and with the output pulse Uc of the AND gate G it is reset. F i g. 6e shows the output signal of the bistable multivibrator Uff \ - Fig.6f shows the constant in its pulse width output pulses of the monostable multivibrator M \, which are obtained from the output pulses of the AND gate G Uc. In the OR gate B , the clock signal Ut and the output signal Um \ are the monostable. Flip-flop M \ linked to one another, whose Äusgangssignai Ub F i g. Ög shows, in the downstream frequency divider stage FF2 with the frequency divider ratio of 2: 1 is formed from the output signal Ub of the OR gate Baas output signal Uff2 , the course of which F i g. 6h shows.

At this frequency divider stage is level if the output signal complementary to Uffi TJfTI to g in accordance with F i. 6i. This signal is fed to a differentiating high-pass filter RC-GIied D, whose output signal Uo F i g. 6k shows. Only its positive needle pulses trigger a further monostable multivibrator M ₂ , the output pulses of which Um ₂ F i g. 61 show

A combination of these output pulses Um 2 and the output pulses Uff \ of the bistable multivibrator FFi in a further AND gate C results in pulses Uc as shown in FIG. 6m at its output. It can be seen from the illustration that these pulses, which are controlled in their pulse width, occur only at the end of the third and fifth periods, i.e. where the storage capacitor Csp is to be almost completely discharged so that it can follow the dynamics of the peak values of the ramp-shaped signal again. The output pulses t / c of the AND gate C are fed to the other input of the OR gate E , the output signal Ue of which is shown in FIG. This output signal of the OR gate E is fed to the base of the discharge transistor T via the resistor Rt, whereby the storage capacitor Csp is discharged within one period to the instantaneous value of the ramp-shaped signal when the pulse width of the control pulses at the base of the discharge transistor T is regulated, and the storage capacitor Csp is almost completely discharged at the end of a period when the drive pulses are controlled at the base of T of their pulse width.

To achieve a directly proportional to the frequency or speed voltage present at the low-pass filter Rtp, Ctp voltage UcTP 5 is fed via a resistor /? The negative input of an operational amplifier OP _2, its positive input to a voltage divider A ₃ of a voltage divider, comprising two resistors Ri Rg is connected, which is fed by a supply voltage source Ub . The output of the operational amplifier OP2 is fed back to the negative input via a resistor Ä6

As a result, a voltage directly proportional to the frequency or speed is generated at the output of the operational amplifier OP _{2 according to FIG.} 60, which can be fed directly to a frequency or speed measuring device or an X-V recorder.

The implementation of the circuit according to the detailed block diagram in FIG. 4 can be carried out using commercially available Components take place. However, overall integration is also conceivable.

In addition 6 sheets of drawings

Claims (6)

1 2 Establishing, controlling and regulating technical proprietary claims: processes necessary. Among other things, monostable tilting struc- 1. Frequency-voltage converter in particular as a fen of a clock signal forming the period attached tachometer for a periodic, the frequency 5 encounter. The pulse time constant output signals or speed-determining clock signal (Ut) with the monostable multivibrator are then fed directly to a variable, adjustable pulse duty factor, which is fed to a moving-coil measuring frequency-dividing bistable multivibrator (FF ₃ ) that is integrated over several periods and is brought into the analog display, which controls a ramp generator (R) . If an analog X- ! ^ recorder is controlled by a frequency that is followed by a peak value memory (SP) or a tachometer of this type and whose output signal (Uscp) is used to record the Frequency or speed curve, tele-forming low-pass filter RC-GBed (Rtt, Ctp), pulling the output pulses of the monostable Kipp leads, characterized in that the voltage (Uctp) at the low-pass RC element is previously transferred via an averaging low-pass filter RC-Ged (Rtt, Ctp) a member can be formed into a continuous voltage, a resistance (Rs) to the negative input of a differential 15 These frequency or speed limit generating operational amplifiers (OPi) measuring devices controlled in this way, however, have the disadvantage that they are conditionally controlled, the analog voltage, which is stable to the frequency or rotational speed through the integration of the output pulses of the mono number, and the associated therewith (UAUSGANG2) , and that via a discharge time constant in the case of a sudden frequency or monitoring circuit (EU), which is also supplied with the speed acceleration or increase in the un-clock signal (& ßj) , large dynamic indirectly successive periods only after Frequency or speed fluctuations indirectly several periods the corresponding voltage can be detected if the ratio of the maximum value can display. It is therefore not possible to display a fixed, adjustable ratio or speed value from period to period for the current frequency-related period . B. in the gate (Csp) in these cases of the Entladeüberwa- KFZ electronics is the ^ but not portable, chungs circuit (EU) is completely discharged. Hence the object of the present invention 2. Frequency-to-voltage converter according to claim 1, based on a frequency-to-voltage converter or characterized in that the positive input of the 30 tachometer indicates which one of the frequency or operational amplifier (OPi) supplies a voltage signal that is directly proportional to the voltage control speed, ler attack ( A ₃ ) a voltage divider, which is made up of two resistors (Rj, Rs), each obtained within a period. Connected is the dynamic friend, great thanks to a logic circuit, that the voltage divider (Rj, Rg) is momentarily detected by a frequency or speed fluctuations and the supply voltage source (Uu) is traveled . 35 so that a continuous frequency or speed generator 3. Frequency-voltage converter according to claim 1 version and processing under all operating conditions or 2, characterized in that the negative opinion is assured output of the operational amplifier (OPi) via a This task is performed by a frequency resp. Resistance (Rs) to the output? of the surgical tachometer connected to the features of claim 1 amplifier (OPi) is solved 40 4. Frequency-to-voltage converter according to one of the further advantageous embodiments of the invention The preceding claims, characterized thereby, emerge from the subclaims. net that the output voltage (Uout) of the Opera- This can be used in advantageous developments tion amplifier (OPi) happen directly to the input of one that the input of the peak value memory Frequency or speed measuring device supplied 45 a ramp-shaped periodic signal with a constant will. Slope is fed that a discharge monitor 5. Frequency-voltage converter according to one of the chung circuit discharges the storage capacitor in certain preceding claims, characterized by th cases and that it is thereby possible that use in automotive engineering. Frequency or speed to be determined within each period 6. Take a frequency-voltage converter according to one of the 50. preceding claims, characterized by the frequency-voltage converter according to the invention using ir mobile hand-held works or rev counter has the advantage that it has a high machine tools, in particular drilling machines. Accuracy of the frequency or speed propor tional output voltage, namely from periodic 55 de to period. This can be particularly with regard to controls or regulations that are frequency or speed dependent The invention relates to a frequency-voltage are necessary if only very small control deviation converters, in particular as a tachometer for a perio- are permissible and the regulation is relatively fast disches, the frequency or speed determining 60 should be. Clock signal with variable, adjustable duty cycle. In a modified form, the frequency of a frequency-dividing bistable multivibrator can be operated as a digital-to-analog converter that controls a ramp generator that is used. a peak value memory is connected downstream and its further advantageous embodiments of the invention The output signal of an averaging low-pass filter RC-65 result from the subclaims. Member is fed. Exemplary embodiments of the invention are shown in The acquisition of frequencies or rotational speeds are shown in drawings and are described in the following by electronic measuring devices for the Oberwa- her.