DE3374829D1 - Phase-locked clock - Google Patents
Phase-locked clockInfo
- Publication number
- DE3374829D1 DE3374829D1 DE8383430029T DE3374829T DE3374829D1 DE 3374829 D1 DE3374829 D1 DE 3374829D1 DE 8383430029 T DE8383430029 T DE 8383430029T DE 3374829 T DE3374829 T DE 3374829T DE 3374829 D1 DE3374829 D1 DE 3374829D1
- Authority
- DE
- Germany
- Prior art keywords
- data
- clock
- multiplexer
- input
- internal clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP83430029A EP0134374B1 (de) | 1983-09-07 | 1983-09-07 | Phasenverriegelter Taktgeber |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3374829D1 true DE3374829D1 (en) | 1988-01-14 |
Family
ID=8191505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8383430029T Expired DE3374829D1 (en) | 1983-09-07 | 1983-09-07 | Phase-locked clock |
Country Status (4)
Country | Link |
---|---|
US (1) | US4569065A (de) |
EP (1) | EP0134374B1 (de) |
JP (1) | JPS6072438A (de) |
DE (1) | DE3374829D1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0262609A3 (de) * | 1986-09-30 | 1990-04-04 | Siemens Aktiengesellschaft | Digitaler Phasenregelkreis |
US4756011A (en) * | 1986-12-24 | 1988-07-05 | Bell Communications Research, Inc. | Digital phase aligner |
ES2030476T3 (es) * | 1987-07-31 | 1992-11-01 | Siemens Aktiengesellschaft | Instalacion de sincronizacion para un desmultiplexor de senales digitales. |
JPH0821856B2 (ja) * | 1987-12-24 | 1996-03-04 | シャープ株式会社 | デジタルpll装置 |
US4972443A (en) * | 1987-11-24 | 1990-11-20 | Siemens Aktiengesellschaft | Method and arrangement for generating a correction signal for a digital clock recovery means |
US5036528A (en) * | 1990-01-29 | 1991-07-30 | Tandem Computers Incorporated | Self-calibrating clock synchronization system |
US5109394A (en) * | 1990-12-24 | 1992-04-28 | Ncr Corporation | All digital phase locked loop |
US5455935A (en) * | 1991-05-31 | 1995-10-03 | Tandem Computers Incorporated | Clock synchronization system |
FR2680058B1 (fr) * | 1991-07-30 | 1994-01-28 | Sgs Thomson Microelectronics Sa | Procede et dispositif de synchronisation d'un signal. |
DE4442506A1 (de) * | 1994-11-30 | 1996-06-05 | Sel Alcatel Ag | Synchronisierungsüberachung in einem Netzwerk |
US5487092A (en) * | 1994-12-22 | 1996-01-23 | International Business Machines Corporation | System for high-speed synchronization across clock domains |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3646452A (en) * | 1971-02-16 | 1972-02-29 | Ibm | Second order digital phaselock loop |
US3983498A (en) * | 1975-11-13 | 1976-09-28 | Motorola, Inc. | Digital phase lock loop |
US4057768A (en) * | 1976-11-11 | 1977-11-08 | International Business Machines Corporation | Variable increment phase locked loop circuit |
JPS5797251A (en) * | 1980-12-09 | 1982-06-16 | Fujitsu Ltd | High speed phase lock system for digital phase locking circuit |
US4424497A (en) * | 1981-04-30 | 1984-01-03 | Monolithic Systems Corporation | System for phase locking clock signals to a frequency encoded data stream |
-
1983
- 1983-09-07 DE DE8383430029T patent/DE3374829D1/de not_active Expired
- 1983-09-07 EP EP83430029A patent/EP0134374B1/de not_active Expired
-
1984
- 1984-07-13 JP JP59144584A patent/JPS6072438A/ja active Granted
- 1984-08-31 US US06/645,963 patent/US4569065A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPS6072438A (ja) | 1985-04-24 |
EP0134374B1 (de) | 1987-12-02 |
US4569065A (en) | 1986-02-04 |
EP0134374A1 (de) | 1985-03-20 |
JPH0316056B2 (de) | 1991-03-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |