DE3363913D1 - Test circuitry for determining turn-on and turn-off delays of logic circuits - Google Patents

Test circuitry for determining turn-on and turn-off delays of logic circuits

Info

Publication number
DE3363913D1
DE3363913D1 DE8383105617T DE3363913T DE3363913D1 DE 3363913 D1 DE3363913 D1 DE 3363913D1 DE 8383105617 T DE8383105617 T DE 8383105617T DE 3363913 T DE3363913 T DE 3363913T DE 3363913 D1 DE3363913 D1 DE 3363913D1
Authority
DE
Germany
Prior art keywords
turn
delays
logic circuits
test circuitry
determining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383105617T
Other languages
German (de)
English (en)
Inventor
Mark Harrison Mcleod
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3363913D1 publication Critical patent/DE3363913D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/03—Logic gate active element oscillator

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
DE8383105617T 1982-07-06 1983-06-08 Test circuitry for determining turn-on and turn-off delays of logic circuits Expired DE3363913D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/395,173 US4489272A (en) 1982-07-06 1982-07-06 Test circuit for turn-on and turn-off delay measurements

Publications (1)

Publication Number Publication Date
DE3363913D1 true DE3363913D1 (en) 1986-07-10

Family

ID=23561978

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383105617T Expired DE3363913D1 (en) 1982-07-06 1983-06-08 Test circuitry for determining turn-on and turn-off delays of logic circuits

Country Status (4)

Country Link
US (1) US4489272A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0098399B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5917174A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3363913D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4660197A (en) * 1985-11-01 1987-04-21 Teradyne, Inc. Circuitry for synchronizing a multiple channel circuit tester
US4712061A (en) * 1986-02-24 1987-12-08 Gould Inc. Small propagation delay measurement for digital logic
US5013944A (en) * 1989-04-20 1991-05-07 International Business Machines Corporation Programmable delay line utilizing measured actual delays to provide a highly accurate delay
JP2503245Y2 (ja) * 1991-02-15 1996-06-26 ダイワ精工株式会社 魚釣用リ―ルのクラッチ装置
JPH0643220A (ja) * 1992-07-23 1994-02-18 Hitachi Ltd 半導体集積回路装置
US5256964A (en) * 1992-07-31 1993-10-26 International Business Machines Corporation Tester calibration verification device
US5787092A (en) * 1997-05-27 1998-07-28 Hewlett-Packard Co. Test chip circuit for on-chip timing characterization
CA2308820A1 (en) 2000-05-15 2001-11-15 The Governors Of The University Of Alberta Wireless radio frequency technique design and method for testing of integrated circuits and wafers
US6850123B1 (en) * 2003-05-27 2005-02-01 Xilinx, Inc. Circuits and methods for characterizing the speed performance of multi-input combinatorial logic
US7373560B1 (en) 2004-12-08 2008-05-13 Xilinx, Inc. Circuit for measuring signal delays of asynchronous inputs of synchronous elements

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051352A (en) * 1976-06-30 1977-09-27 International Business Machines Corporation Level sensitive embedded array logic system
US4392105A (en) * 1980-12-17 1983-07-05 International Business Machines Corp. Test circuit for delay measurements on a LSI chip

Also Published As

Publication number Publication date
JPS5917174A (ja) 1984-01-28
EP0098399A3 (en) 1984-08-01
EP0098399A2 (en) 1984-01-18
EP0098399B1 (en) 1986-06-04
US4489272A (en) 1984-12-18
JPH0322949B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee