DE3311731A1 - BIDIRECTIONAL WORKING ARRANGEMENT FOR ADJUSTING DATA BYTES IN A DIGITAL DATA PROCESSING SYSTEM - Google Patents

Description

NER &

LANDWEHTiSTR. 37 COOO MONOMS ■ TEI-0 BO / CO 9T 84

Munich, March 28, 1983 / M Attorney's files .: 27 - Pat. 335

Raytheon Company, 141 Spring Street, Lexington, MA 02173, United States of America

Bidirectional arrangement for adjusting data bytes in a digital data processing system

The invention relates to a random access memory and relates in detail to an arrangement for bidirectional adjustment of data bytes for the transmission of an or several bytes of a digital word to and from one or more memory locations within a memory cycle time.

Computers or data processing systems typically include a memory subsystem having a plurality of memory locations for the storage of digital words derived from a particular Number of bits, for example 8, 16, 24 or 32 bits. The computer architecture of some popular 32-bit general-purpose computers uses variable-length instructions that consist of a sequence of bytes, the first or the first two bytes specify the operation to be performed, while the subsequent ones Bytes specify the operand. The average An instruction is approximately three bytes long, although the total instructions in a computer are one to sixteen bytes long can. Allows a mixture of variable length instructions and data to be stored in a 32-bit longword memory

the best possible use of the available storage space,; if, for example, part of a 32-bit command or data] word is saved under the same memory address as ί a 16-bit command or data word and the rest under a subsequent

\ following memory address.

I In the prior art, efficient use of the j storage space through a combination of hardware and software ' Measures achieved. Often there is more than one memory cycle time; required if part of a command or data word is below ■ one memory address is stored and the other part is stored under a following memory address. In other cases there are only certain Addresses of a memory system available for the storage of multi-byte words. Or precautions must be taken to convert an unadjusted memory request into a sequence of shorter, adjusted requests, for which purpose several storage cycle times are required. The result was a more efficient use of the storage space, however the computer's processing speed has decreased.

In the prior art, there were restrictions on byte addressability in a storage system, resulting in an improved utilization of storage space, but a reduced operating speed results. The invention is based on the object of providing the possibility of accessing any memory system and to create a one, two or four byte sequence beginning at any byte address without any adjustment constraints on the part of the programming and operating system, and thus maximum system performance with minimum hardware expenditure enable.

This object is achieved by an arrangement with the features of claim 1.

Advantageous refinements and developments of the invention emerge from the subclaims, which are hereby to be shortened the description is expressly referred to.

~ 2 -

The invention thus discloses an arrangement for bidirectional adjustment of data bytes with a system bus for supply digital information bytes to a memory and for receiving digital information bytes from this memory, furthermore with transceiver devices for transmission at least one of a plurality of digital bytes between the memory and the system bus, with a first byte bus for transmission at least one of the bytes between the system bus and a first access of the transceiver devices, with a second byte bus for transmitting at least one of the bytes between a second access point of the transceiver devices and the memory, means for controlling the memory accesses reading and reading of the memory beginning at any byte memory location in the memory, as well as means for controlling of the transceiver devices when transmitting at least one of the bytes between the memory and the system bus. Of the Memory includes at least one memory segment with an even number and at least one memory segment with an odd address which can be accessed simultaneously To provide memory access for a plurality of sequence bytes. The transceiver devices contain a plurality of bidirectional ones Transceiver arrangements, each of which has a plurality of bidirectional multiple-bit bus transceivers included. the Means for controlling the memory access further comprise a device for writing in and reading out a plurality of Bytes that extend beyond the boundaries of the memory segment. The memory control and the control of the transceivers include a plurality of programmable logic arrangements. In addition, means are provided that have a right-justified zero extension when transmitting at least one of the bytes during a memory readout cycle, and means for right-justifying Sign extension if at least one of the bytes is transmitted during a memory readout cycle.

The invention also relates to a memory for storing a plurality of digital information bytes, the at least one Storage segment with even-numbered and at least one storage

• Has a segment with an odd address and also has the following features: A byte adjuster for access to a byte of information at any of a plurality of byte storage locations in the memory within a memory cycle and for access to a plurality of bytes of a byte sequence! within a memory cycle, this byte sequence can begin at any of the byte storage locations in the memory, furthermore a system bus for transmitting the digital bytes to the memory and for receiving the digital bytes from the memory. The memory segment with the even-numbered addresses and the memory segment with the odd-numbered addresses comprise means which enable simultaneous access within a memory cycle time, so that access to a plurality of consecutive bytes is possible. The individual memory segments include byte adjusters that are interconnected by the bus system. The memory access includes memory readout cycles and memory write cycles. The byte adjuster further comprises a plurality of bidirectional transceiver arrangements, whose. each including a plurality of bi-directional multi-bit bus transceivers and a plurality of programmed logic assemblies. The latter include devices for generating control signals for the memory and the bidirectional transceiver arrangement,

The invention also relates to a method for accessing a memory with the possibility of byte addressing, the following Process steps include: Digital information bytes are made transferred to a system bus; the bytes are anc on a first byte bus between the system bus and a bidirectional send / receive transfer facility; the transceiver performs a byte adjustment; the bytes are on a second byte bus between: see the bidirectional transceiver and the Speicl transfer; the cycles of writing and reading of the memory are controlled with programmed logic arrangements; the bidirectional The transceiver is also controlled with the programmed logic arrangements. The memory includes at least one Memory field with an even address and at least one saliva

field with odd-numbered address; on the memory fields can be accessed simultaneously, allowing memory access to a plurality of consecutive bytes is possible. The procedural step the control of the write-in and read-out cycles makes use of a device that starts at any Allows byte storage location within the memory and which extends beyond the boundaries of the memory field. The bidirectional transceiver comprises a plurality of bidirectional transceiver arrangements, the in turn, a plurality of bidirectional multiple-bit bus transceivers in each case include.

The invention is explained in more detail below with reference to the drawings:

1A and 1B show together a block diagram of a bidirectional adjustment arrangement according to FIG of the invention using a 16K random access memory for 32-bit words connected is,

Fig. 2 shows a block diagram of a memory system that are independent of one another Segments are organized with even-numbered addresses and odd-numbered addresses, each of these memory segments containing the arrangement according to Figure IA and IB.

In Figure IA and IB is the block diagram of a 16K memory segment 110 for 32-bit longwords which includes a bidirectional data byte adjuster 18 which is provided with a 16K memory array 28 for 32-bit longwords. The data byte adjuster 18 enables a memory to be addressed with individual Byte limits instead of the usual two-byte (VJort) limits or four-byte (longword) boundaries, (each byte being 8 bits). If the memory segment 110 is connected to a different memory

. s ^ ament 112 is connected (Figure 2), a 32K longword storage system is created, which is organized in 32-bit words,

^{: is} addressable byte by byte and allows random access. The memory segment 110 includes adjusted even longword addresses, while the memory segment 112 includes adjusted odd longword addresses. Both memory segments 110 and 112 operate in parallel and allow access to two long words, with eight bytes (quadruple word) being generated. This accelerates the memory access to bytes that are not adjusted according to the memory word boundaries. If a memory longword address is an even-numbered base address, a memory location (n) of the memory segment with odd-numbered addresses is accessed, which then supplies four bytes (0-3); At the same time, a memory location (n + 1) of the memory segment with odd addresses is accessed, which then supplies an additional four bytes (4-7). If the base address is odd, the memory segment with odd addresses accesses a memory location (n) which supplies four bytes (0-3); At the same time, the memory segment with the odd-numbered addresses accesses a memory location (n + 1) which supplies an additional four bytes (4-7). The data byte adjuster 18 of each memory segment selects a maximum of four of the eight bytes and outputs them to a system bus 19 during a memory readout cycle.

As can be seen from Figure 2, in addition to the memory segments 110 and 112 further memory segments to increase the memory capacity be provided. If a memory access exceed that the limit of a 32K longword (or 128K byte) pair of memory segments creates a fast carry lookahead circuit known type in the memory segment 112 a carry signal COUT-113 at the CIN-109 signal input of the next higher Address in memory segment 114. If the base address is an even number, no such carry is generated, since it is on four consecutive bytes can be accessed without exceeding the limit of the memory segment pair. If the

Base address odd and the highest address in that Address field of a 32K longword memory segment pair, the COUT-113 signal is generated to initiate a memory cycle in initiate the next higher memory segment and to prevent that the lower memory segment with even-numbered Addresses responds by sending the COUT-113 signal to an ABORT-115 input of the memory segment 110 with even-numbered addresses connected, thereby avoiding a bus conflict.

The data byte adjuster 18 in memory segment 110 (FIGS. 1A and 1B) includes field programmable logic arrays (FPLAs) 10, 12, 14 and 16, and a bidirectional transceiver array 30 connected to a memory array 28 and a system bus 90. The transceiver field carries out the bidirectional multiplex functions and the bidirectional bus interface functions under the control of the four FPLAs 10, 12, 14 and 16. The memory array 28 enables 16K longwords of 32 bits (4 bytes) to be stored. The data byte adjuster 18 is responsible for performing read and write cycles in the memory array 28 and selects those of the eight accessible bytes (from two memory arrays) to be used. Each memory segment 110 and 112 has its own data byte adjustment circuit 18, the response of each data byte adjuster being determined by the external jumper input EVEN + of the FPLAs 14-16. The Datenbytejustierer can select one _r two or four bytes for both read and write cycles for and treat the data in either right-aligned or right-aligned zero extended vorzGichenerweiterter form. The same data byte adjuster circuitry is used for both the memory read and memory write cycles. This is an important advantage of the arrangement according to the invention.

As can be seen from FIG. 1B, the memory array 28 is shown in FIG four byte sections of memory 20, 22, 24 and 26 organized random access memory (RAMs), each section being 16K words

7 -

comprises eight bits. The four sections together allow the storage of 16K longwords of 32 bits. To the realization the memory arrangement 28 is a static 16K χ 1-bit RAM, for example an INMOS IMS1400 integrated circuit. Each eight-bit byte section of memory array 28 is associated with the Transceiver arrangement 30 via individual RAM byte buses 82,; 84r 86 and 88 connected which allow each byte to be and transmitted from any byte position via the bi-directional transceiver assembly 30 onto the system bus 90.

From Figure IA and IB it can be seen that the bidirectional transceiver arrangement 30 16 separately controlled octal transceivers 32-62 for the transmission of information bytes between the System bus 90 and memory array 28 includes. Each transceiver consists of a bidirectional 8-bit tristate circuit. It can be, for example, the integrated circuit AM 73/8303 from AMD. A T / R entrance to -iedem The transceiver determines the direction of the logic signals through the same, i.e. i.e., whether the Α-entrance or the B-entrance is the entrance or the exit is. A WR signal is with the T / R inputs all transceivers 32-62 connected. The input labeled CD is the blocking input, the control input for chip selection is working. The FPLAs 10 and 14 generate sixteen control signals to individually select each of the sixteen transceivers 32-6 ^ Three buffers 64, 66 and 68, along with logic gates 96 and 27, serve to zero or sign extension, if only one or two Bytes in the memory segment 110 are selected. Buffers 64, 66 and 68 can be integrated circuits F 244 from the company Be fairchild. Byte buses 72, 74, 76 and 78 make up the dataweq between system bus 90 and the B terminals of transceivers 32-62. Byte buses 72, 74 and 76 also provide a connection to the buffers 64, 66 and 68 respectively. Further byte buses designated 82, 84, 86 and 88 form the data paths between the A-terminals of transceivers 32-62 and RAMs 20, 22, 24 and 2

The FPLAs 10, 12 and 16 (Figures IA and IB) control the memory array 28 and the transceiver assembly 30. In order for everyone Memory segments 110-120 (Figure 2) to get identical hardware, Each FPLA 10, 16 is coded to include the logic required to create a memory segment for both to make both even-numbered and odd-numbered addresses suitable. The use of the FPLAs enables a maximum functional density for the required control logic. Whether a memory segment 110-120 responds to even-numbered or odd-numbered addresses, is determined by the EVEN + signal, which is connected to the I 7 inputs of the FPLAs 10-16. When the signal EVEN + is a HIGH signal, the relevant FPLA works for even numbers Addresses. When the EVEN + signal is a LOW signal, an FPLA operates for odd numbered addresses. As already mentioned a signal ABORT- of the individual FPLAs 10-16 blocks a lower-value memory segment with even-numbered addresses, if on the next most significant memory segment with even-numbered ones Addresses is accessed. A LOCKOUT- signal is fed to the I 5 inputs of the FPLAs 10-16 and causes activation such that the output control signals do not perform status switching while an input address bit is changing. A TEST- signal applied to an input of each FPLA 1-16 provides a means of testing these FPLAs. the FPLAs 10-16 can be integrated tristate circuits 82S 153 from Signetics with Fuse-Loqik, the 32 AND gates and 10 Include OR gates that are used to program the I / O polarity and direction are equipped with fusible connection lines using conventional logic programming devices. Tables 1 to 4 show the programming of the individual FPLAs 10, 12, 14 and 16 in detail and in a format that the data specifications for an integrated circuit 72S 153 is prescribed.

In Tables 1 to 4 are the inputs with I and the outputs labeled B (although the B terminals can also be used as inputs). For the inputs, an H means one high logic level and an L a low logic level;

-in line (-) means that the logic level · has no meaning is. For the outputs, an A means that it is an active output and a period (.) / That it is is an inactive output. The rows labeled D represent ten direction control gates. When a such D line contains zeros, a B terminal is used as an input. A dash (-) on a D line indicates that a Output is activated for all conditions. Further information on a PPLA can be found in the specification sheets for the integrated tristate circuit FPLA 82S 153 from the company Signetics. The logic required for control purposes is divided so that the number of devices and the FPLA coding effort are minimal when described in the book "Digital Circuits and Logic Design" by Samuel C. Lee, Prentice Hall 1976 Quine-McCluskey technique is applied.

Tables 1 and 2 provide the control program for the transceiver arrangement 30. The outputs of the transceiver control FPLA 10 and 14 are connected to the transceivers 32-62 and control the transfer of data bytes between system bus 90 and RAMs 20-26. An output signal, for example that Signal MOB3 of the transceiver control FPLA 14 causes, for example the activation of a transceiver and determines at Presence of the WR write control signal, which is an eight-bit byte from RAM 16, (identified as MO in Table 6 is), via the transceiver 56 to the Ryte bus 3 72 is to be transmitted (which is designated as B3 in Tables 6 and 7). The remaining output signals of the transceiver control FPLA 10 and 14 perform analog functions for the separate activation of each of the octal transceivers. The charts 3 and 4 show the control program for generating the write control signals MWRTO-, MWRT1-, MWRT2- and MWRT3- for the RAMs 26, 24, 22 and 20, which are generated by the RAM controllers FPLA 12 and 16, respectively. In addition, FPLA 12 and 16 generate control signals for a sign extension for one byte (IBYSE +) and two bytes (2BYSE +). The signal IBYSE + of the FPLA 16 is with a

- 10 -

Input of a NAND gate 97 and an AND-OR inverter 96, furthermore with the input of an inverter 92 tied together. The output of the inverter 92 is connected to the inputs of the buffer 68. The signal 2BYSE + der FPLA 12 is connected to one input of AND-OR inverter 96 tied together. The FPLA 16 also generates the WORDEX- signal which is coupled to buffers 64 and 66 for sign extension will. The AND-OR inverter is, for example, the integrated one Circuit 74F64 from Fairchild.

During a read cycle, the data byte adjuster 18 presents the requested number of bytes to the system bus 90. This number 'is' a function of the inputs of the FPLAs 10-16 (Figure IA) applied signals SZl + and SZO + for controlling the data field size, furthermore address signals Al + and AO + as well as control signals SIGNEX + for sign extension. The signals for controlling the data field size determine whether to 1, 2 or 4 information bytes is accessed, as can be seen from Table 5.

The two least significant bits (LSB) of a memory address presented by Al and AO in Table 6 indicate which byte is the first byte within a controlled long word. If identified by the size and address field Data exclusively in an even or single odd-numbered memory segment, only this segment outputs data to the system bus 90, if the requested data is partially are in a memory segment with even-numbered addresses and partly in a memory segment with odd-numbered addresses transfer the appropriate bytes from both the even and odd storage elements to the system bus 90. If a memory access with a memory segment with odd numbers Addresses starts, the address for an even-numbered memory segment is automatically increased by 1 before a data adjustment takes place. As a result, consecutive bytes of data are always backed up. If sign extension during a read cycle what should take place by the presence of the signal

- 11 -

SIGNEX + is displayed at inputs B8 of the FPLAs 12 and 16-, this is linked with addresses and size control signals, 'which generate the signals IBYSE + and 2BYSE + depending on them, whether a memory access of one or two bytes is required. The most significant bit (MSB) of the most significant of the requested Bytes is generated by the NAND gate 97 and the AND-OR inverter 96 checked. The output of NAND gate 97 is

• with the buffer 68 and the output of the AND-OR inverter 96 is provided with the sign extension buffers 64 and 66

• bound. Based on the status of the MSB of the most significant byte of the word that is being accessed are either all zeros or all ones to the left of the addressed byte on the System bus 90 is filled, thereby placing the sign information in the MSB position of an information word. If because of In the absence of the SIGNEX + signal at FPLA 12 and 16, a sign extension is not required, all zeros to the left become of the activated byte on the system bus 90 is filled. Sign stretching is nonexistent during a memory write cycle valid operation.

Table 6 summarizes the data multiplexing performed during a read cycle together. In addition to the address bits Al and AO, which are the starting byte within a selected word

■ identify, the address bit A2 determines whether an even-numbered Memory segment or an odd-numbered memory segment containing the first byte. The number of bytes included with the Sign extension statuses are requested are indicated to the left of the address bit. B3, B2, Bl and BO refer to the byte bus 3 72, the byte bus 2 74, the byte bus 1 76 and the byte bus 0 78, which are connected to the 4-byte system bus 90. MO to M7 relate to bytes 0 to 3 of RAMs 26, 24, 22 and 20 in a memory segment with even-numbered addresses and the corresponding RAM bytes 4 to 7 in a memory segment 112 with odd-numbered addresses. S refers to that Sign of the addressed byte with the highest priority. Although a total of 8 bytes of memory segment 110 with even-numbered and · of the memory segment 112 with odd-numbered

Addresses can be controlled, only four of the eight bytes from both memory segments are used by the data byte adjustment logic in each memory segment for transmission to the system, bus 90 selected. This selection is made under the control of the bidirectional transceiver arrangement 30 in each memory segment.

Further reference is made to Table 6 and consider the case that there is no sign extension, two bytes are requested, the memory segment with an even number . Addresses is called (A2 = 0) and the first byte in the RAM byte M3 is (Al., AO = 1.1). Then the column shows BO under the Address N (even-numbered memory) that the RAM byte M3 is placed on byte bus 0 78 and to byte BO of system bus 90 is transmitted. In addition, the column Bl shows under the address N ■ + 1 (odd-numbered memory) that the RAM byte M4 on the Byte bus 1 76 placed in an odd memory segment and transferred to byte B1 of system bus 90, with 90 zeros extend to the left in bytes B2 and B3 of the system bus.

The memory segments are accessed during a write cycle with even and odd addresses under the control of data byte adjuster 18. The adjuster checks the size of the control field flagged bit shown in Table 5 and the least significant bit shown in Table 7 LSBs of the address bits AO and A1 and determines which bytes of the memory segment are to be written. When a write cycle is executed in the bytes so specified, the rest of the Bytes not disturbed.

Table 7 summarizes the data multiplexing performed during a write cycle together. MO to M7 relate to bytes 0 to 7 of RAMs 20-26 of a memory segment 110 with even numbers Addresses and a memory segment 112 with odd addresses. BO to B3 refer to bytes 0 to 3 of the

- 13 -

! System bus 90. Considering the case in which two Bytes BÖ and Bl are to be written into the memory j and the starting byte (BO) in a memory segment with an even number Addresses (A2 = 0) and in the byte storage location M3 (Al, AO = 1,1) 'is to be written, then Bl is written into byte M4 of a memory segment with odd-numbered addresses, as shown in Table 7. The signal WR- (Figure IA and

Figure IB) is present during a write cycle and causes that the entrance B of all transceivers 32-62 forms an entrance and the entrance A forms the exit. The signal WR- delivers one Path for the data to be transmitted from the system bus 90 to one or all bytes of the memory arrangement 28.

- 14 -

Tabel

FLPA A program transceiver control (bytes 0 and 1)

.Outputs

Input

HHtIIlI] IU ΪΙ | Β | Β | Β | Β | Β | Β | Β | Β | Β | Β | 716 | 5Γ4 | 3 | 2Ι1 | 0 | 918 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | -I-ILILILILILILILILI

B | BtB | B | B | B | B | B | B | B! 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | l | 0 |

H H L H H H L H - H H H L H L H H H-L H H H H H-L H H H L H H H L H

H H

H H

H H HH

ti _

H- H

H H

H -

H -

H H

H H

H H

H H

H H

H H

H -

H -

H H

H L

H H

H L

HLH

HLH HHH HHH

- L

- H H H H L

- H

- L H H H L

- H

- L H L H H

LL-L L-LHH LHH LHH LHH L H H LHH H. H H H .H H LL-LL-

A. • • · . A. »· A. • . A. Ä A. A. . A. *. • A. . A. • • A. • · : a • * ·

A.
A.
A.
A.

A A

A.

A.

. A.

. A.

D9
D8
D7
D6
D5
D4
D3
D2
Dl
DO

000000000000000000 000000000000000000 mil
==! 11

- 15 -

Table 2

FPLA B program transmitter / receiver control (bytes 3 and 4)

Exits

--1-ILILlLlLlLlLlLiLl

φ Il
71 Il
61 Il
51 Il
41 il
31 Chants Il
U U
01 Bl
91 Bl
81 Leaf
7161 Bl
51 Bl
41 Bl
31 Bl
21. Bl
H BI
Oil BlBl
9181 -. Bl
71 Bl
61 B.
5 Il Il Il IB
14th I. 13th
13th 1 IB
12th I. I. Il Il Il IBl
Ul B.
0 I.
1 • E.
R.
H j M CN A. I. I. rf. I. • - H H L. A. I. A. 1 H H H H- H Yy L. S = A. » A. * 2 L. H H H H L. L. L. A. Il Il Il
Il Il Il Il Il Il
Il Il Il A. 3 L. H H H H H L. H 14th - A. A. 4th H H H H H H L. H H _ A. • * • 5 L. H H H L. ti L. H _ .. A. • » 6th H H H H - H ti L. H _. ^ A. 7th L. H H - H L. ti H H A. 8th H H H - H H ti H H ... A. 9 L. H H H - L. ti H U _ A. 10 H H H H - H ti H H A. 11th H H H H H L. ti ti H ._ A. 12th L. H H H H H ti ti H _. A. A. 13th L. H H H -. L. L. ti 14th _ A. A. 14th H H H H - H L. ti H - = - = I ι 15th L. H H - H L. H L. H 16 H H H - H H H [j H 17th 0 0 0 0 0 L. 0 0 0 0 0 0 0 0 0 0 0 0 1
I. 1
ι 1 1 I. 1 r> 9 0 0 0 0 0 0 0 0 0 U U U U U Ü 0 0 0 - = I. I. I.
1 D 8 0 =! D7 Il Il I
ti ti ι
Il Il I
Il Il I
Il 11 I.
Il ti I
Il Π 1
11 Il I
1 Il Il I D6 I. D5 1
I. D4 11 Il I
Il Il I Il Il Il
Il Il Il == j D3
D2
Dl

- 16 -

z%

T E. R. M.

Tabel

FPLA C program RAM control (bytes 0 and 1)

Entrances

IllllIlUIUllllBlBlBlBlBlBlBlBlBlB 7 | 6I5 | 4 | 3 | 2ll | 0l9 | 8 | 7 | 6 | 5 | 4 | 3l2 | l | 0 outputs

J-IH-I-I-JLIHILILI

B'lBlBlBlBlBlBlBlBlB) ! 8 I 7 I 6 I 5 I 4 I 3 I 2! 11 0.Ί

H
L.
H
L.
H
L.
H
L.
L.
H
H
L.
L.
H
H
H
L.
L.
L.
H
L.
H

H H HHL H H L HHH HHH HHH HHH HHH H H H H II H H H H H 11 Η "H H H H H H H H H Il H H. FI H H H HHH HHH H H H HH-HH-

H L

H H

L L

L H

L L

L H

L H

L L

- H

- L H H H L H H H L

- H H H

- L H L

- fl

- L H H H L

-LL

-LL

L-L

L-L

HHL

H H L

L H H-

L Fl H -

HHH-

-HH-

HHH-

-HH-

LLH-

LLH-

LLH-

LLH-

L L

H H

H H

H H

H H

H H

H H

H H

H H

- H

- H

- Il

- H

- H

- H

- H

- H

- H

- H

- H

- H

- H II AA
AA

H
A.
A.
A.
A.

A.

A.

A A

A A

A.

Λ.

. A.

. A.

. A.

A A A A A

D9 D8 D7 D6 D5 D4 D 3 D2 Dl DO

00000000000000 0 oooooooooooooooooo 00 0-00..0 00000000 0 0.0 0000000000000000 oooooooooooooooooo 00 0 000000000000000 ItII

ι ι

I.

= 1 1

. I.

" 1

- 17 -

Table H.
FPLA D program RAM control

(Bytes 2 and 3) inputs

IIIlIlIllUllUlBlBlBlBlBlBlBlBlBlB 7 | 6 | 5 | 4 | 3 | 2 | l | 0l9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | l | 0i outputs

I-I-I-I-I-I-IHILILI

3IBIBI3IB1BIBIB1BIBI 9 | 8j7 | 6 | 5 | 413 | 2 | l | 0 |

- HH
HHH
LHH
HHH
LHH
HHH
LHH
LHH
HHH
LHH
HHH
LHH
HHH
LHH
HHH
LHH
H FI H
LHH
HHH
LHH
HHH
HHH
LHH

HLL
HLH
HLL
HLH
HLH
HLL
HH
HL
HHH
HHL
-HH
- FI

-LL -LL L-L L-L HHL HHL

L L

H H

H H

H H

H H

H H

H H

A A

Η - U _ "~ Π -

H-H-

Η
H
H
H

L.
H
L.
H
L.

HHH
Fl HL
- HH
-HL

HHH

HHL

- - H H H H H H H H L H H L H LHH L H II

L L H

H H

HLH HHH H H H

H H Ii H H H H

H El H

IJ

ίι

H H

A.
A.
A.

A.
A.

A.
A.
A.
A.
A.
A.

A A A A A A A A A A

D9
D8
D7
D β
D5
ϊ) 4
D3
D2
Dl

oooooooooooooooooo ====== ι! ill

======= I I 1 1

I.

oooooooooooooooooo

0 0 0 0 0 0

00000000000 oooooooooooooooooo oooooooooooooooooo 00000000000000000 Ό oooooooooooooooooo

Table 5 Control field size

0 0 1 1

SZ

0 1 0 1 required Bvtes number

O 1 2

_ 18 -

If

Table 6 Data multiplexing during read cycle

number A2 Al AO Address N + 2 Address N + 1 B2 B1 BO B address M. straight. N L. B2 Il Bra B the O 0 0 M straight L. M; odd L. S storage segment S. 0 0 MO Vo γζ. Bytes 0 ' 0 1 S storage segment S. S storage segment S. 0 0 M1 first 0 1 0 B B3_ B2 Bl BO B B B3_ 0 0 0 M2 0 1 1 0 0 0 M3 1 0 0 0 0 M4 0 1 1 0 1 0 0 M5 0 no 1 1 0 0 0 M6 1 1 1 0 0 0 M7 0 0 0 0 S. S. MO 0 0 1 0 S. S. M1 0 1 ο - 0 S. S. S. M2 0 1 1 S. S. S. M3 1 0 0 S. S M4 S. 1 1 0 1 S. S M5 S. Yes 1 1 0 S. S M6 1 1 1 S. S. S M7 0 0 0 S. 0 M1 MO 0 0 1 S. 0 M2 M1 0 1 0 S. 0 0 M3 M2 0 1 1 0 M4 - 0 - - M3 1 0 0 0 M5 M4 0 2 1 0 1 0 M6 M5 - No . 1 1 0 0 0 M7 M6 1 1 1 , 0 _ - M7 0 0 0 0 S. M1 MO 0 0 1 0 S. M2 M1 0 1 0 Q 0 MO- _ S. S. M3 M2 0 1 Ϊ S. M4 - S. - - M3 1 0 0 S. M5 M4 S. 2 1 0 1 S. M6 M5 - Yes 1 1 0 S. S. M7 M6 1 1 1 S. - - M7 0 0 0 S. M2 M1 MO 0 0 1 S. - _ _ M3 M2 M1 0 1 0 S S MO - - M4 - - M3 - M3 M2 0 1 1 M5 M4 - - - - M3 1 0 0 M4 M6 M5 M4 - same- 4th 1 0 1 M5 M7 M6 M5 - oül- 1 1 0 M6 - M7 M6 tig 1 1 1 M7 - - M7 MON - - - - M1 MQ - - - 112 M1 MO - -

Note: S refers to the sign of the most significant bit of the most significant Bytes to be accessed. MO to M7 refer to Memory bytes 0 to 7. BO to B3 refer to the system bus bytes to 3

- 19 -

Table 7 Data Multiplexing During Write Cycle

A2 Al AQ Address N + 2 Address I. M2 al MO B address N L. HO B number O O O M straight L. M straight S storage segment S. BO the O O 1 S storage segment S. M odd L. B 111 IE HL - Bytes O 1 O B M3_ M2 Ml MQ B S storage segment S. - - - - O 1 1 B M3_ - - BO - 1 O O - - BO -BO- 1 O 1 - BO - BO - - 1 1 1 O BO - - 1 1 1 - - - O O O - BO O O 1 - - O 1 O - - - B1 - O 1 1 BO - - B1 - BI BO _ 1 O O - B1 BO B1 EO - 1 O 1 B1 BO - BO - - 2 1 1 O BU _ - 1 1 1 - - - - O O O - BO O O 1 - - - B3 - O 1 O - - - B1 B1 - B3 B2 B3 B2 B1 - O 1 1 BO B3 B2 B1 B2 B1 Bu - 1 O O B2 B1 BO B1 BO - 1 O 1 - B1 BO - BO - - • 4 1 1 O - BO _ - 1 1 1 - - - - - - B3 B3 - - B3 B2 B2 - B3 B2 B1 B1 BO

Note: MO to M7 refer to bytes 0 to 7 of the memory.

BO to B3 relate to bytes j to 3 of the system bus

Claims (29)

33UU1 Godfather ta e nsprüch Bidirectional arrangement for adjusting data bytes in a digital data processing system with a system bus for outputting digital data comprising one or more bytes to a storage device and for receiving such data from the storage device
marked by - Transceiver devices (30) for transmission at least one byte of a plurality of bytes between the storage means (28) and the system bus (90), - A first byte bus device (72, 74, 76, 78) for transmission at least one of the bytes mentioned between the system bus (90) and a first access (IT) of said transceiver devices (30), - A second byte bus device (82, 84, 86, 88) for transmission at least one of the said bytes between a second access (A) of the transceiver devices (30) and the Storage device (28), - A control device (12, 16) for controlling any byte memory location of the said memory device (28) beginning read-write memory accesses - As well as a control device (10, 14) for controlling the transceiver devices (30) during the transmission of at least one of the said bytes between the memory device (28) and the system bus (90). 2. Arrangement according to claim 1, characterized by - a device for right-aligned zero extension in the Transmission of at least one of the said bytes during a memory read cycle - as well as a device for right-aligned sign extension when transmitting at least one of the bytes mentioned during a memory read cycle. ' 3. Arrangement according to claim 1, characterized in that on a byte of information at any one of a plurality I of Bytespeicherstellen in the memory means (28) within ^1/2 of a memory cycle is accessible and further that an access to a plurality of consecutive bytes within a memory cycle and is given starting from any byte location in the memory means (28). 4. Arrangement according to one of the preceding claims, characterized in that; in that the memory means comprises at least a 'storage segment (110) with even-numbered addresses and at least ¹ comprises a memory segment (112) with odd-numbered addresses and in that a possibility for simultaneous access to these memory segments (110, 112) and thus the opportunity to access a A plurality of consecutive bytes is given. : 5. Arrangement according to one of the preceding claims, characterized in that the transceiver devices have a plurality 'comprise bidirectional transceiver fields (30). I 6. Arrangement according to claim 5, characterized in that each said bidirectional transceiver fields (30) for their part a plurality of bidirectional transceivers (32 to 62) each to transmit a plurality of bits appropriate buses (e.g. 82 and 72) are connected). 7. Arrangement according to claim 4, characterized in that the Control device for controlling the memory access the writing and allows reading out a plurality of bytes, said plurality of bytes extending beyond the limits of said Memory segments (even, odd) extends. 8. Arrangement according to one of the preceding claims, characterized in that the control device for controlling the Memory access and the control device for controlling the Transceiver devices comprise a plurality of programmable logic arrangements (FPLA 12, 16 or 10, 14). 9. Arrangement according to claim 8, characterized in that each of the said memory segments (110-120) are formed identically Groups of programmable logic arrangements are assigned. 10. The arrangement according to claim 2, characterized gekennzeihnet that the device for sign extension means for checking the contains the most significant bits of a most significant byte. 11. Arrangement according to one of the preceding claims, characterized characterized in that each memory segment has a byte adjustment device (18) is assigned, and that the byte adjustment devices of the individual memory segments through the system bus (90) are connected to each other. 12. The arrangement according to claim 11, characterized in that the byte aligner of each memory segment comprises a plurality of programmed logic arrangements. 13. Arrangement according to claim 12, characterized in that the programmed logic arrangements (12, 16 or 10, 14) Control signals for the memory device (28) and the bidirectional Generate transceiver field (30). 14. Arrangement according to one or more of the preceding claims, characterized in that the memory access operations Include memory read and memory write cycles. 15. The arrangement according to claim 11 or 12, characterized in that with the help of the byto-adjusting device also a right-justified Zero and / or sign extension can be carried out if at least one of the bytes mentioned during a memory read cycle from the memory device (28) to the system bus (90) is transmitted. 16. The arrangement according to one or more of the preceding claims, characterized in that each transceiver (z. B. 32) of the bidirectional transceiver field (30) for the transmission of at least one byte of digital information is set up. 17. The arrangement according to claim 1, characterized in that the first byte bus device has a plurality of byte buses (72, 74, 76, 78) for the transmission of one byte (0, 1, 2, 3) of the system bus (90), which are parallel to each other switched first accesses (B) of a first group of transceivers (32, 40, 48, 56) are connected. 18. The arrangement according to claim 17, characterized in that the system bus (90) with a plurality of first byte bus devices is connected, via which it (90) consisting of a plurality of bytes of digital information to a memory moment (e.g. 110) with even-numbered addresses and to a memory segment (e.g. 112) with odd-numbered addresses. receives from these memory segments. 19. The arrangement according to claim 1, characterized in that the second byte bus device consists of a plurality of byte buses (82, 84, 86, 88), each one byte of a memory field (28) of the memory segments (e.g. 110, 112) with two-tone accesses (A) of a group connected in parallel to one another of transceivers (e.g. 32, 34, 36, 38). 20. The arrangement according to claim 1, characterized in that the control device (12, 16) for Steuerunq the memory access can be acted upon bidirectionally by memory addressing signals and is connected to a memory field (28) of a memory segment (z. B. 110) in such a way that it enables read and write accesses controls within the memory segment boundaries and over these memory segment boundaries. 21. The arrangement according to claim 1, characterized in that the Control device (10, 14,) for controlling the transceiver devices (30), which can be controlled by memory address signals, with a transceiver field of the transceiver device is connected in such a way that it prevents the transmission of at least one byte from said plurality of information bytes between the memory field (28) and the system bus (90) controls. 22. The arrangement according to claim 17, characterized in that the first group (32, 40, 48, 56) of transceivers is arranged is that with their help, a byte of the system bus (90) can be transferred from or to any byte position in the memory field (28) is. 23. The arrangement according to claim 19, characterized in that the second group (z. "R. 32, 34, 36, 38) of transceivers like this is arranged that with their help a byte of the memory field (28) to or from eirv; r any byte position of the system bus (90) is transferable. 24. Arrangement according to claim 22 and 23, characterized in that the control devices (12, 16 or 10, 14) from a plurality consist of programmable logic arrangements. 25. The arrangement according to claim 24, characterized in that the Control device (12, 16) for controlling memory access a control logic for executing a right-justified zero and / or sign extension during the transmission at least contains one of the bytes mentioned within a memory read cycle. 26. Memory access method for an arrangement according to an or several of claims 1 to 25, characterized by the following process steps: - Digital information bytes are transferred to a system bus (90) given, - These bytes are on a first byte bus device (72, 74, 76, 78) between the system bus (90) and a bidirectional transceiver device (30) transmitted, - With the help of the transceiver device (30) is a Byte adjustment carried out, - The bytes mentioned are on a second byte bus device (82, 84, 86, 88) between the bidirectional transceiver arrangement (32) and the storage device (28), - with the help of programmed logic arrangements (10, 12, 14, 16) write and read cycles of the memory device (28) are controlled, - The bidirectional transceiver (30) is with Controlled using the said programmed logic arrangement. 27. The method according to claim 26, characterized in that the step of controlling the write and read cycles Measure includes that at any byte memory location of the memory device is started and the access is over extends the boundaries of the individual memory fields of the memory device. 28. The method according to claim 26 or 27, characterized in that a right-aligned zero and / or sign extension is executed when at least one of said bytes is transferred to the system bus (90) during a memory read cycle will. 29. The method according to claim 28, characterized in that the right-aligned sign extension measures for checking the contains the most significant bits of a most significant byte.