DE3303868A1 - Circuit arrangement for digitising and storing video images for further digital processing - Google Patents

Abstract

The digitisation and storage of the information contained in a video frame at the rate of the system clock has the following problems: Random access to the memory content and simple postprocessing are not possible due to the predetermined clock times; in particular, overwriting of freely selected data in the memory has not been possible with previous systems. The solution is obtained by dividing the memory into four subdivisions which operate in parallel by advantageously selecting addressing, in such a manner that in each case one subdivision is ready for reading/writing the data present. Due to this preaddressing, the entire memory area can be considered from the outside as if its read/write cycle were four times shorter than that of its individual chips. This makes it possible to digitise the image supplied by a CCD camera at a clock rate of 7 MHz and to store it in a 256-kByte memory formed from 4116-type RAMs. An interface provides for the reading-out, writing and controlling of the sequence by means of any computer. If the computer does not address the system, the memory content is periodically output for generating a still image on a monitor. The system can be used for recording intensity profiles in two dimensions, storing and processing images which do not last less than one frame period of a complete video frame.

Description

The invention relates to a circuit arrangement for digitization

and storage of video images for subsequent digital processing. The information contained in two successive fields (frame) of one B / W television or The video image should be read out at the same speed in the recording device is carried out with high resolution in digital signals and converted into be stored on a corresponding storage medium. To simplify further processing Access to any selected data must be possible. To check the saved Information must guarantee a permanently visible display on a monitor be.

To prepare the data, it is necessary to have data in the memory can be changed. the control must be with any computer, microprocessor or hardwired.

The assignment of the pixels to digital information should be possible be precise in order to enable a high spatial resolution.

Technical solutions are in the form that a) images in the raster process are scanned b) Circuit arrangements are used which are similar to a shift register function c) mechanically complex storage media (partly analog intermediate storage, e.g. video tape) can be used (e.g. disk storage).

The disadvantages in method a) are that none are rapidly changing Images can be captured since reading is done for several television images b) that no data points can be accessed without complex logic, since the complete picture is always run through c) that sensitive mechanical components are necessary which, for example, place high demands on the operating conditions.

The invention is based on the object using commercially available Memory modules to digitize a B / W video image of a CCD camera, to save it and to enable further processing in a simple form.

The object is achieved according to the invention in that the video information with the system clock (operating frequency, furthermore referred to as clock signal) in one Analog-digital converter (ADC, e.g. from TRW) (Fig. 1) pixel by pixel in 8 bit digital data is transmitted.

This enables 256 levels of gray to be recognized. At the same time is through a pixel counter (0 corresponds to the beginning of the image) the associated address (or spatial Position of the pixel) of the data byte. This address consists of 19 bits; 9 bit code the line, 9 bits the position in the line; 1 bit indicates whether the first or second field is present and is used to recognize the complete digitization. The exact description of these signals is e.g.

from the data sheets from Fairchild for the CCD camera.

The storage takes place in 4 memory blocks of 64 kB each (in the following referred to as a bank).

Each of the 4 banks is equipped as follows: It consists of 32 memory ICs of type 4116 or the same addressing type (e.g. manufacturer Motorola MCM 4116 BP-15 or BP-30).

The control signals and designations correspond to those of the associated Data Sheets. The addressing assignment and generation of these signals are below described.

Each IC stores 16 kBit and is addressed via 2 x 7 addresses. The organization takes place in 8 bits, so a bank has 4 blocks of 16 kByte.

With the exception of the data inputs / outputs, each block is wired completely in parallel, so that addressing takes place byte by byte.

The two fastest changeable addresses, A17, A16 are opened the four 2 to 4 decoders of the individual bank (74 S 139, IC 1) (Fig. 2) are given each of which one of the decoding outputs is wired so that always exactly one which sends four decoders 'LOW' to the bank assigned to it. Are at the same time entrance 15 and 1 to 'HIGH', this has the following effect: a) the counter IC 3 (74 LS 161) (Fig. 2) is started and counts 1101, 1110, 1111, 0000 in time with the system clock.

b) the multiplexer IC 2 (74 LS 154) (Fig. 2) forwards the one write or read access assigned signals to the memory modules and switches (corresponding to reading / writing) the bus line drivers IC 5a, b (74 LS 241) (Fig. 2) in the direction of the memory or data bus according to the state of the counter outputs 14 and 13.

c) the line driver IC 4a, b (74 LS 241) (Fig. 2) are through the Counter output 13 switched so that first the addresses on the memory AR - A6, then addresses A7 - A13 are present.

d) the counter output 12 is inverted and delivers directly to the Processing of the first 7 addresses A - A6 necessary pulse (hereinafter called R -: - S) to all 32 memory modules.

e) the counter output 13 is inverted and results from an 'OR' link with the addresses A14, A15 decoded in IC 1 (FIG. 2) for processing of the second 7 addresses A7 - A13 necessary pulse (hereinafter referred to as C'A-§). This only affects a memory area of 16 kByte, depending on the addresses A14, A15.

This division ensures that every data byte is accurate is assigned to a memory location.

The RAS inputs of all 4 blocks are connected.

The CAS inputs are only connected within one block, the four Blocks are separated (CASp - 3).

The RD / WR inputs of all four blocks are connected.

The data inputs / outputs of all four blocks are corresponding to Bit - Bit7 connected so that 8 data lines lead to the outside.

This organization has the following effects: a) that of dynamic memories necessary refresh is automatic by the running RAS signal and the fast variable addresses A - A6.

b) which byte is addressed determines the combination: Ap - A6: A row is selected in all ICs A7 - A13: in a block there is a column selected A14-A15: a block is selected in a bank A16-A17: a bank is selected selected.

c) the access time (cycle time) of the memory modules is not the Limit for the storage system: because the addressing process after selecting the bank continues to run automatically with A16 -A17, there are 4 clock cycles left to read in or To enable the data to be read out.

This pre-addressing only has the effect of shifting the data (here original address + 3) can be stored in the memory. The one that can be reached with four banks Time is at least 1/4 of the cycle time of a block.

(here: 94 ns) d) by combining the RD / WR signals and the Control signals of the IC's 5a, b with the counter IC 3 (Fig. 2) ensures that it is only written or read when valid data is pending or the data bus free is.

The control of the overall process (access, start of digitization) takes place through an interface (Fig. 1: Interface).

The structure of this component is as follows (see Fig. 3): a) The connection 3 8-bit buffers for the computer.

(74 LS 373): 2 data registers (input / output) 1 command register The strobe input reports that valid data is pending. The ready output allows feedback that new commands can be given.

b) A wired microprogram is made up of various logical ones Links and a 4 bit counter 74 LS 191 in connection with a 4 to 16 decoder.

The links exist between the outputs of the decoder and of the command register.

c) The address line is either supplied with the one supplied by the pixel counter Addresses or with 2 x 9 bit counters located in the interface (6 x 74 LS 161) Driven through a 19 bit multiplexer.

d) A 4-bit counter controls when a whole picture is over.

e) Two flip-flops synchronize the process with commands from the computer.

-f) A flip-flop ensures that all memory units (banks) work in the right rhythm.

The function is as follows: With the strobe pulse the 4 bit counter is started (15--) if there is no refresh pause or the program is still working.

With each of the 15 steps the outputs of the decoder are linked to execute a specific function with outputs of the command register.

A maximum of 256 commands can be executed in parallel in one counting step will.

The functions wired here are TAB. 1 can be found.

The commands wired here are TAB. 2 can be found.

This allows the sequence control to be carried out by an 8-bit computer or can be specified by means of switches.

The contents of the memory are reproduced in such a way that always if no program is running, the memory with the addresses generated by the camera system is addressed and the associated data with the help of a commercially available digital / analog Converter (e.g. from TRW) can be converted into analog signals in a mixer (Mixer Fig. 1) the standardized synchronous pulses are added to this signal, see above that there is a standard video signal that can be displayed on each monitor can.

The pending data are bit by bit in parallel in a comparator compared with the set bit pattern (image modification Fig. 1) and the output signal controls the DAC so that the set gray level is switched to either black or white if there is equality.

This means that all pixels of the same gray are reproduced in black or white ('Contour Lines').

A further embodiment of the invention is given in that a commercially available video camera can be used.

This is made possible by having the control unit (Fig. 1) not as a unit with the camera - as is customary with the CCD camera - but built up separately will.

According to the state of the art, two modes of operation are possible: The pixel counter (Address generator) is driven by a clock and this clock is synchronized the camera control process. This is possible with cameras with external synchronization (e.g. Bosch).

If this is not possible, the camera must be used The address generator generates synchronous signals (picture start, line start, picture change) be synchronized.

TAB. 1: Counter function 15 Synchronization of banks, reading in data from Computer, commands from computer 14 Increasing the pixel counter, increasing the line counter 13 Clear pixel counters, clear line counters 12th 11 End of synchronization 10 9 8 Read data from memory, WR = H 7th 6th 5 4 Write data to memory, WR = L 3 2 Clear pixel counter (start full screen) 1 Start of digitization TAB. 2: Bit function O Increase pixel counter 1 Increment line counter 2 Clear pixel counters 3 Clear line counters 4 Write to memory 5 Read from memory 6 Start full screen 7 Start digitization

Claims (2)

Circuit arrangement for digitizing and storing video images for subsequent digital processing, characterized in that a) the Digitization and storage in time with the video image takes place b) as a storage medium RAMs of a certain type of addressing are used, their read / write cycle time can be up to four times longer than the clock time of the video information; this will possible through parallel processing and pre-addressing c) the stored information can be displayed as a still image on a monitor d) a full image (two fields) e) a CCD camera is used as the image source. 2.) As la-d), characterized in that the arrangement supports the use a commercially available video camera (Vidicon, Plumbicon, Newicon).