DE3303380C2 - Semiconductor memory - Google Patents

Description

The invention relates to a semiconductor memory according to the preamble of claim 1.

In the magazine ELEKTRONIK 79 issue 12 / S. 39 to (W. RIENECKER) such a semiconductor component is described. The information in the memory cells is not accessible by random access.

In the magazine ELEKTRON IK 76 / issue 10 / S. 53 to (GOSER) describes a semiconductor component that has a one-transistor cell based on the CCD principle. This has the disadvantage that "moving" of a date from one memory cell to an adjacent one can only be done by reading out the date and rewriting it at the new address. Should the contents of several memory cells be moved this process must be repeated accordingly often.

Searching for certain elements in datasets, e.g. B. Entries in tables can be sorted by sorting the Data volumes are accelerated. The Z. This is one of the most effective search methods on sorted amounts of data Binary search. In data processing systems, the binary search method is z. Currently implemented by software.

to This method is only efficient if the data is in a memory with fast random access are filed. For the following considerations we will assume that the data is stored in a conventional semiconductor random memory (RAM) and that each element of the data set occupies exactly one memory word. The time required to search for a datum is then proportional to the number of memory accesses required, where η is the number of elements of the ordered data. amount is.

The cheapest time to spend binary searching applies but only as long as the amount of data is not changed. If data is to be inserted or deleted, some of the data must be relocated in the memory in order to maintain the sorting required for the binary search procedure (when inserting) or the complete storage of the data (when deleting). When inserting a date, the address under which it is to be entered according to the order must be determined.

jo must be carried. Before this can happen, you need to the element under this address and all subsequent elements are shifted by one position in the memory in the direction of higher-order addresses. It is assumed that the data in the lower part (low

J5 addresses) of the memory and the free spaces in upper part. When deleting, the elements that are behind the item to be deleted have to move to a position be shifted in the direction of lower-order addresses.

Because of the above-described disadvantages of conventional auxiliary equipment packages, the expenditure of time is increased for the shifting of a date, the statistical mean is proportional to jn, with an equal distribution of the Probability for inserting or deleting at a certain address is assumed. So on average γ shift operations have to be performed

can be made when a date is to be inserted or deleted, with each move operation depending read and write access are necessary.

The object of the invention is therefore to provide a semiconductor module according to the preamble of claim 1 in such a way to train that random access is enabled, whereby the following conditions must be met:

a) From the address; Shift all data under the addresses A> i simultaneously by one place in the direction of higher addresses (forward shift due to a control signal).

b) Shift up to the address / all data under the addresses A> i at the same time in the direction of lower addresses by one place (backward shift due to a control signal).

c) Random access to the memory cells for writing and reading the data.

The capacity should be in the order of magnitude of today's semiconductor memories.

A random access memory (RAM) is to be subjected to this, the memory cells of which are as follows are such that the information from a cell / to of the neighboring cell / - 1 (move backwards) or / + 1 (move forward) in one (Mchrphasen-) Clock interval can be pushed. This memory is referred to in the following as "Shift-RAM". The shifting effort would be reduced to the time required for the one parallel shifting operation described all selected da'a lowered,

and there would no longer be an average "T" sequential Shift operations necessary.

This object is achieved by the measures specified in the characterizing part of claim 1. Further Refinements of the invention are described in claims 2 and 3.

The invention is explained in more detail using exemplary embodiments. It shows

1 shows a schematic representation of a CCD shift register,

F i g. 2 equivalent circuit diagram of a CCD shift register,

Fig. 3 One-transistor cell according to the CCD principle and equivalent circuit,

F i g. 4 cell Z, of the shift RAM,

F i g. 5 Line selection for the move process,

F i g. 6 Shift RAM cell Z ₁ with cell selection for shifting process,

F i g. 7 memory word of the shift RAM, consisting of 4 1-bit cells.

In Fig. 1 a known CCD shift register is shown schematically. MOS capacitors Q, C ₂ , d are applied to a substrate P-Si. There are clock phase lines Φ \, Φ ₂ , Φι provided. Furthermore, two Al electrodes (input gate, control gate) are applied to a SiCV layer. The connections for channel K are N ⁺ zones. The MOS capacitors Ci, C ₂ , Ci have the channel K as a common electrode. The channel AC consists of an N-Si zone. The clock phase lines Φ \, Φ ₂ , Φι are connected to the other electrodes of the capacitors Ci, C ₂ , C \ .

In Fig. 2 is an equivalent circuit diagram corresponding to 1 ^; i g. 1 shown. Here, the channel K is shown by a double arrow, which makes the possibility of charge transport along the channel clear.

FIG. 3 shows a one-transistor memory according to the CCD principle and the associated equivalent circuit diagram. On the substrate P-Si a SiO - layer is applied, on which there are two Al electrodes. One electrode is the gate of the MOS transistor T, the other electrode belongs to the MOS capacitor C. The N ⁺ zone in the substrate P-Si is the data line (bit line). The gate of the MOS transistor T is connected to the word line (word line).

F i g. FIG. 4 shows an embodiment of a cell structure according to the invention. It arises from the combination of a CCD cell according to FIG. 1 or 2 with a one-transistor cell according to Fi g. 3. The capacitor Ci in Fig.4 replaces the capacitor C in Fig.3. The transistor Γ «corresponds to the transistor Tin Fig.3. Z, ι and Z _{1 1} ι indicate where the next cells with the next lower or next higher address are located.

The memory module according to the invention has two operating modes, the Lcse-write mode and the shift mode.

In Fig. 5 shows the scheme for selecting rows when moving. For each cell '/., Of the shift RAM, as shown in FIG. 4 indicates an additional transistor T ₁ is provided which is connected in the clock line of the Taktphasc <l> \. With the help of the additional selection line RS " which is connected to the gate of the transistor T =", the clock phase Φι can be interrupted by blocking the transistor T , so that the cells whose index is smaller / is separated from the clock phase Φι. This is because the clock phase Φ \ is fed in from the cell with the highest address value.

ίο For the shift operations, it must be specified from which address A the data should be shifted.

a) With the »up shift«, all data under the addresses A ' > A are shifted.

b) With the »down shift« all data under the addresses A '> A are shifted.

The direction of movement is determined by the sequence of the cycle phases:

Φ2, Φι. S ⁶ I -. "Upshift"
Φ \, Φι, Ά: »down shift«

2ϊ Taking into account points a) and b) it follows that for the shift operations ("up shift" and "down shift") from address A onwards, all shift RAM cells A '> A with the multi-phase clock Φ \, Φ ₂ , Φ> must be supplied and the cells with the addresses, 4 "< A are separated from the 3-phase cycle.

For the cells that are not participating in the move operation

involved, it must be prevented that the charges of these shift RAM cells to an adjacent cell hike. Also, these cells must not have any charges from

V) neighboring cells are preserved. This is achieved by interrupting the trunk lines to the cells. This results in an additional expense of 3 additional (pass) transistors per memory cell. However, more detailed investigations have shown that only one additional transistor is required per memory cell to interrupt the cycle phase Φ \. This is illustrated by the following consideration with the aid of FIG. 5.

Let RS, = 0: block the transistor T).
4 ^r > all other RSj - \, j Φ i: conducting transistors T).

For the cells with Φι = 0 (j < ; ^ then applies:

_{5 ()} »up shift«: ^ 2. 'Aj. <l '\

Phase of transport direction

»Down shift«: Φ3, Φ2, Φ \
Phase of transport direction

Φι C ₁ .C ₂ Φι φ> G -C-, Φ, = ( )! Φ; φ, G -egg' φ.

G-C,

In the cases described, the charges do not leave the shift RAM cells when they are separated from Φι.

For addressing the memory cells for the dispatch operations, only one additional transistor per memory word is therefore necessary. This transistor is controlled via the additional control line “row beet” (RS,) , which is selected by the address decoder when the shift RAM is in shift mode.

In I'ig. b is an embodiment of the shift RAM cell '/ . 4th

is expanded by the transistor T ₁ for cell selection for the shift operation.

The selection line RS for the transistor T ₁ and the word selection line word line are selected by the address decoder. In the Lesc-Schrcib mode ^r > only the word line selection is important, since in this mode the clock lines for the phases Φχ, Φι, ίί * »are inactive.

The addressing of the shift RAM cells for the read and write operations is carried out according to the methods used in DRAM modules (DRAM: Dynamic Random Access Memory): Selection of the lines via "word line" and a subsequent selection of the data on the "bit lines". This addressing only affects Ci derShift-RAM-Zel- r> le (vg |, Fig. 4). Since the relevant information is in the charge of the capacitor Q in the read-write mode, refreshing can take place according to the method used in dynamic RAMs, namely reading and rewriting in blocks by addressing via the word line. This eliminates the need to continuously move the data with CCD memories.

In the shift mode, the transistor 7 "", the Cell Z, through the word line word line, can be disabled. This applies to all cells of the memory module.

Only one additional external signal is required to differentiate between the two operating modes.

7 shows an embodiment of the invention jo in which a memory word W ₁ consists of four 1-bit cells Z,. _u , Z ₁ . 1. Z ₁ . 2, line ₁ . \. Each clock phase is connected to the four associated capacitors. Since all bits of a memory word W are always shifted together in shift operations, only one transistor T _{1 is} necessary for each J5 memory word to interrupt the line of the clock phase Φ \.

Since by the series connection of the MOS transistors 7; (F i g. 5) a signal attenuation of Φ> takes place, an amplification of the signal Φι is required after a certain number of cells.

For this purpose 3 sheets of drawings

45

55 gr

Claims (3)

Patent claims: 1. Semiconductor memory, consisting of a CCD shift register, which has a MOS transistor as an input transistor, a plurality of MOS capacitors and three clock phase lines and in CCD cells of three MOS capacitors each. which are adjacent and each connected to a different one of the three clock phase lines, the first capacitor of the first CCD cell being connected to the input transistor, characterized in that the input tratisistor is configured as word and data lines as input / Output transistor (T _K ) works and in connection with the first CCD cell forms a memory cell (Z ₁ ) with direct access that all other CCD cells in the same way as the first CCD cell by providing an input / Output transistor (T _WI ) to memory cells (Z) are designed with direct access that the information to be output from a memory cell (Z) is always present in the first MOS capacitor (C \) and that when suitable clock phases (Φι, Φ ₂ , Φή the information stored in the first MOS capacitor CCi) of a memory cell (ZJ through the second and third MOS capacitors (C2, Ci) into the first MOS capacitor (G) d he adjacent memory cell (Z, _ 1. Zi + 1) is transferred so that a memory area with a contiguous address can be shifted by one memory location in one shift cycle without activating the word and data lines (FIG. 4). 2. Semiconductor memory according to claim 1, characterized in that a further transistor (T) is provided per memory cell (Z ₁ ) which is connected to the capacitor (Cj) and the line (Φ \) , that the gate of this transistor (Ti ) is connected to a selection line (RS ₁ ) . that the capacitor (C2) with the line of the clock phase (Φ2) and the capacitor Ci) are connected to the line of the clock phase (Φ \) (Fig. 6). 3. Semiconductor memory according to claim 1 or claim 2, characterized in that / to structure a memory word (W ₁ ) of more than one bit word length several memory cells (Z ,. _n , Zi. 1, Z ₁ ; ₂ , Zj. 3) are connected to one another in such a way that they have the lines of the clock phases (Φι, Φι, Φι) and the transistor (T) in common (FIG. 7).