DE3303380A1 - Semiconductor memory - Google Patents

Abstract

When inserting and deleting data in or from sorted data bases in digital computers, data have to be shifted by program in order to maintain the sorting. In cases of large quantities of data, such a shifting operation is time-consuming. The subject of the invention is a semiconductor memory chip having the following functions: - storage of digital data - writing and reading of the data by random access - time-parallel shifting of all the data of a selected subset of the data located in the memory chip (within a single clock cycle). The figure shows the equivalent circuit diagram of an embodiment of a memory cell according to the invention. This memory cell combines the functions of a dynamic single-transistor memory cell with the functions of a CCD memory cell. The function of the dynamic memory cell is ensured by the transistor TWI and the capacitance C1, the function of the CCD memory cell is ensured by the capacitances C1, C2, C3, the multiphase clock PHI 1, PHI 2, PHI 3 and the channel K. The selection of the subset of data to be shifted is made possible by the transistor Ti. <IMAGE>

Description

SEMICONDUCTOR MEMORY COMPONENT

The invention relates to a semiconductor memory module according to the preamble of claim 1.

In the magazine ELEKTRONIK 79 / issue 12 / S. 39 to 47 (W. RIENECKER) such a semiconductor module is described. The information in the memory cells is not accessible through random access.

In the magazine ELEKTRONIK 76 / issue 1O / S. 53 to 56 (GOSER) a semiconductor module is described which has a one-transistor cell based on the CCD principle having. This has the disadvantage that "moving" a date from a Memory cell in an adjacent one only by reading out the date and rewriting it can be done at the new address. Should the content of several memory cells are moved, this process must be repeated accordingly often.

Searching for certain elements in data sets, e.g. entries in tables, can be accelerated by sorting the amount of data. The currently most effective The binary search method in data processing systems is the search method on sorted data volumes the binary search procedure is currently implemented by software.

This method is only efficient when the data is in memory are stored with fast random access. We want for the following considerations assume that the data in a conventional semiconductor random memory (RAM) are stored and that each element of the data set occupies exactly one memory word. The time it takes to search for a date is then measured by the number of necessary memory accesses, proportional 2109 n, where n is the number of elements the ordered amount of data.

However, the cheap time required for binary searching only applies while the amount of data is not changed. When data is inserted or deleted should, so some of the data in the memory must be relocated to allow for the binary search process necessary sorting (when inserting) or the complete storage of the data (when deleting). When inserting a date, the address must be determined under which it must be entered in accordance with the regulations. Before this can happen, the element at this address and all of the following be shifted by one position in the memory in the direction of more significant addresses. It is assumed that the data is in the lower part (low addresses) of the memory stand and the free spaces in the upper part. When deleting the elements, who stand behind the one to be deleted, to one position in the direction of the lower order Addresses are moved.

Because of the disadvantages of conventional semiconductor memory components outlined above the time it takes to move a date is proportional to the statistical mean 7 n, where a uniform distribution of the probability for insertion or deletion is accepted at a specific address. So an average of 7 shift operations are required can be made when a date is to be inserted or deleted, whereby per Shift operation each one read and one write access are necessary.

The object of the invention is therefore to provide a semiconductor module to develop the preamble of claim 1 in such a way that the random access is made possible, whereby the following conditions must be met: a) From the address i all data under the addresses A> i simultaneously in the direction of higher addresses Shift one position (forward shift due to a control signal).

b) Up to address i, all data at addresses A i at the same time move one place in the direction of lower addresses (move backwards due to a control signal).

c) Random access to the memory cells for the Writing and reading the data.

The capacity should be in the order of magnitude of today's semiconductor memories lie.

a) With the "up shift" all data are shifted under the addresses A '> 4.

b) With the "down shift" all data under the addresses A '> A postponed.

The direction of movement is determined by the sequence of the clock phases # 2, # 3, # 1: "up shift" # 3, # 2, # 1: "down shift".

Taking into account points a) and b) it follows that for the shift operations ("up shift" and "down shift") from address A all Shift RAM cells A '> A must be supplied with the multiphase cycle # 1, # 2, # 3 and the cells with the addresses A "<A are separated from the 3-phase clock.

For the cells that are not involved in the move operation, must be prevented that the charges of these shift RAM cells to an adjacent one Cell wander. These cells are also not allowed to receive any charges from neighboring cells. This is achieved by interrupting the clock lines to the cells. It results This results in an additional expense of 3 additional (pass transistors per memory cell.

However, more detailed investigations showed that per memory cell only an additional transistor to interrupt the clock phase 03 is necessary.

This is illustrated by the following consideration with the aid of FIG.

Let RSi = O: block the transistor Ti. All others RS = 1, j + i: conductive transistors Tj For the cells with # 3 = 0 (j <i) the following then applies: "up shift ": # 2, # 3, # 1" down shift ": # 3, # 2, # 1 phase transport direction phase transport direction # 2 C1 # C2 # 3 C1 # C1, # 3 = O! # 3 C2 # C2, # 3 = O! # 2 C1 # C2 # 1 C2 # C1 # 1 C2 # C1 the Charges do not leave the shift RAM cells in the cases described, if they are separated from C3.

For addressing the memory cells for the shift operations so only one additional transistor per memory word is necessary. This transistor is controlled via the additional control line "row select" (RSj), which is carried out by the address decoder is selected when the shift RAM is in shift mode.

In Fig. 6 an embodiment of the shift RAM cell Zj is shown, the opposite of the shape in Fig. 4 to the transistor T. for cell selection for the Move operation is extended.

The selection line RS1 for the transistor Ti and the word selection line word linei are selected by the address decoder. Is in read-write mode however, only the word selection line word linej is important, since in this mode the = clock lines for the phases oels (1> 2 'C2, O3 are inactive.

Addressing the shift RAM cells for read and write operations takes place according to the methods used in DRAM modules (DRAM: Dynamic Random Access Memory) can be used: Selection of the lines via "word line" and one subsequent selection of the data on the bit lines. This addressing concerns only C1 of the shift RAM cell in each case (cf. FIG. 4). Since in read-write mode the relevant Information is stuck in the charge of the capacitor Cl, the refreshing after the Methods used in dynamic RAMs, namely reading and rewriting in blocks by addressing via the word line. This is not the case with CCD memories necessary continuous moving of the data.

In the shift mode, the transistor Twi of the cell Zj must through the Word selection line word line. be blocked. This applies to all cells of the memory module.

To differentiate between the two operating modes, only one additional external signal required.

In Fig. 7, an embodiment of the invention is shown at the one memory word Wi consists of four 1-bit cells Zi0, / i1, Zi2, Zi3. Every cycle phase is connected to the four associated capacitors. As with move operations all bits of a memory word W. are always shifted together is per memory word only one transistor T is necessary to interrupt the line of clock phase # 3.

Since the series connection of the MOS transistors Ti (Fig. 5) a Signal attenuation of # 3 occurs after a certain number of cells is one Amplification of signal (1) 3 required.

Claims (3)

SEMICONDUCTOR MEMORY COMPONENT PATENT CLAIMS Semiconductor memory component, using capacitors to store the information, with transistors for input and output of charges for the capacitors, with a three-phase cycle, one electrode of the capacitors through the channel (K) of the semiconductor module is formed (CCD memory module) characterized in that per 1-bit memory cell a transistor (Twi) is provided, which is connected to the data line (bit line) and a Capacitor (C1) of this memory cell (Fig. 4) via the channel (K) of the CCD memory module is connected, that the gate. of this transistor (Twi) with the selection line (word linej) is connected. 2. Semiconductor memory module according to claim l, characterized in that that a transistor Ti is provided with the capacitor (C3) and the line the clock phase ((1) 3) is connected that the gate of this transistor (Tj) with the Selection line (RSi) is connected that the capacitor (C2) with the line of the Clock phase (C2) and the capacitor (C1) connected to the line of the clock phase (# 1) are (Fig. 6). 3. Semiconductor memory device according to claim 1 and claim 2 thereby characterized in that for the construction of a memory word (Wi) of more than 1 bit word length several memory cells (Zj Os Zi, 1, Z. Zi, 3) are connected to one another in such a way that that they share the lines of the clock phases (ml 2 O3) and the transistor (Tj) have (Fig. 7).