DE3279996D1 - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- DE3279996D1 DE3279996D1 DE8282112020T DE3279996T DE3279996D1 DE 3279996 D1 DE3279996 D1 DE 3279996D1 DE 8282112020 T DE8282112020 T DE 8282112020T DE 3279996 T DE3279996 T DE 3279996T DE 3279996 D1 DE3279996 D1 DE 3279996D1
- Authority
- DE
- Germany
- Prior art keywords
- memory circuit
- memory
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56215269A JPS58114391A (ja) | 1981-12-25 | 1981-12-25 | センスアンプ回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3279996D1 true DE3279996D1 (en) | 1989-11-23 |
Family
ID=16669507
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8282112020T Expired DE3279996D1 (en) | 1981-12-25 | 1982-12-27 | Memory circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US4559619A (de) |
EP (1) | EP0083099B1 (de) |
JP (1) | JPS58114391A (de) |
DE (1) | DE3279996D1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4961166A (en) * | 1984-05-07 | 1990-10-02 | Hitachi, Ltd. | Dynamic RAM having a full size dummy cell |
US4825409A (en) * | 1985-05-13 | 1989-04-25 | Wang Laboratories, Inc. | NMOS data storage cell for clocked shift register applications |
US4780850A (en) * | 1986-10-31 | 1988-10-25 | Mitsubishi Denki Kabushiki Kaisha | CMOS dynamic random access memory |
JP2610598B2 (ja) * | 1987-03-16 | 1997-05-14 | シーメンス・アクチエンゲゼルシヤフト | 半導体メモリへのデータの並列書込み回路装置 |
US5694143A (en) * | 1994-06-02 | 1997-12-02 | Accelerix Limited | Single chip frame buffer and graphics accelerator |
FR2809222A1 (fr) * | 2000-05-17 | 2001-11-23 | St Microelectronics Sa | Memoire eeprom comprenant un systeme de correction d'erreur |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2443529B2 (de) * | 1974-09-11 | 1977-09-01 | Siemens AG, 1000 Berlin und 8000 München | Verfahren und anordnung zum einschreiben von binaersignalen in ausgewaehlte speicherelemente eines mos-speichers |
US4081701A (en) * | 1976-06-01 | 1978-03-28 | Texas Instruments Incorporated | High speed sense amplifier for MOS random access memory |
JPS53134337A (en) * | 1977-03-25 | 1978-11-22 | Hitachi Ltd | Sense circuit |
DE2919166C2 (de) * | 1978-05-12 | 1986-01-02 | Nippon Electric Co., Ltd., Tokio/Tokyo | Speichervorrichtung |
JPS5647988A (en) * | 1979-09-20 | 1981-04-30 | Nec Corp | Semiconductor memory device |
-
1981
- 1981-12-25 JP JP56215269A patent/JPS58114391A/ja active Pending
-
1982
- 1982-12-27 EP EP82112020A patent/EP0083099B1/de not_active Expired
- 1982-12-27 US US06/452,986 patent/US4559619A/en not_active Expired - Lifetime
- 1982-12-27 DE DE8282112020T patent/DE3279996D1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
US4559619A (en) | 1985-12-17 |
EP0083099B1 (de) | 1989-10-18 |
EP0083099A2 (de) | 1983-07-06 |
EP0083099A3 (en) | 1985-11-27 |
JPS58114391A (ja) | 1983-07-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |