DE3235412A1 - INTEGRATED SEMICONDUCTOR CIRCUIT DEVICE AND METHOD FOR THEIR PRODUCTION - Google Patents

Description

- 6 description

The invention relates to a semiconductor integrated circuit device and a method for their production. In detail, according to a specific structure, the semiconductor integrated circuit device according to the invention comprises a linear circuit and a UL (integrated Injection logic) circuit formed in a single semiconductor substrate.

A semiconductor integrated circuit device falls on the inventor (hereinafter referred to as IC for short), which has the above-mentioned circuit structure for the control having a power supply. Such a power supply control IC used in industrial robots, for example, and has an IC chip level pattern as shown schematically in FIG. According to Fig. 1, this power supply control IC is composed of one IIL element section 2, which is in a semiconductor substrate 1 is designed for the construction of an IIL circuit, and a linear element section 3 which is thus formed in the semiconductor substrate 1 for the construction of the linear circuit is that it encloses the IIL element section 2, together. Furthermore, the IIL element section is set in detail 2 made up of a fast IIL element section 2a which is made operative at a high speed and a low speed IIL element section 2b which is operated at a low speed will, together. This fast and slow IIL element section 2a and 2b form such a special logic circuit as shown in FIG. In detail The logic circuit shown in FIG. 2 consists of an inverter INV and η cascaded flip-flop circuits F / F-1, F / F-2, F / F-3, ..., F / F-n together, with which a frequency divider circuit is constructed. A clock signal is sent to the input line A of this frequency divider circuit.

nal of, for example, 400 kHz given while its input line B receives a reset signal. A signal is also present on the output line C of the frequency divider circuit decreased, its frequency through the η flip-flop circuits is divided.

As shown in FIG. 3a, the circuit of the inverter INV is composed in detail of a PNP transistor Q ₁ and an NPN transistor Q 1 having multiple outputs (or collectors) OUT ₁ to OUT and thus forms a well-known one IIL inverter circuit. Further, since even the IIL inverter circuit of Fig. 3a can be expressed as a logic circuit as shown in Fig. 3b, the inverter is constructed INV FIG. 2 by the outputs (or collectors) of the transistor Q ₂ of the IIL inverter circuit shown in detail in FIG. 3a. The connection of the outputs of the transistor Q ₂ takes place in order to improve the drive capacity of the inverter INV.

On the other hand, the flip-flops are F / F-1, F / F-2, F / F-3, ..., F / F-n as shown in Fig. 4, respectively constructed from a number of inverters INV1 to INV8. Here, each of the inverters INV1 to INV8 is similar to that above-mentioned inverter INV is constructed by the IIL inverter circuit shown in Fig. 3a. One such shown in FIG F / F receives a clock signal at its control terminal T and a reset signal at its reset terminal R. An output signal of the flip-flop circuit F / F is also picked up at the output terminal Q. At an output port Q, on the other hand, an output signal is picked up, which is opposite in phase to the signal taken from the output terminal Q. This output signal Q becomes however, in the frequency dividing circuit shown in FIG not used.

In order to increase the speed of the frequency divider circuit described and its. Power consumption to

reduce, a method for controlling the fast IIL element section 2a and the slow IIL element section 2b devised by injection streams which are different from one another. For example, in the (the inverter INV and the flip-flop circuits F / F-1 and F / F-2 containing) fast IIL element section 2a,. Of the clock signals from 400 kHz to 100 kHz, an injection current I. shown in Fig. 3a. (i.e., the injection current of a single IIL inverter circuit) to 20 to 30 μΑ set so that faster operation is possible. In the (containing the flip-flop circuits F / F-3 through F / F-n) slow IIL element section 2b which is to receive a clock signal of 100 kHz or less, since there is no need for fast operation, the injection current is reduced to 5 to 6 μΑ in order to reduce the power consumption to be kept as low as possible.

Since there are separate injection currents to achieve the mentioned different injection currents built up in the IC the number of included elements is increased, which also increases the number of wirings

for connecting the injection power sources and the IIL element sections and thus brings about the problem that the integration density of the IC is decreased. According to the invention it becomes possible not only to increase the operating speed and the power consumption to reduce, but also to solve the above problem.

The invention is therefore based on the object of creating a semiconductor integrated circuit device, those with a high density integrated IIL element section is designed, which has a high operating speed and low power consumption.

Furthermore, a semiconductor integrated circuit device is to be provided which has the aforementioned IIL element section and includes a linear element section disposed therearound.

Another object of the invention is to provide a method for manufacturing a semiconductor integrated circuit device which includes such a
Includes IIL element section and linear element section.

The invention proposes to solve the first-mentioned problem a semiconductor integrated circuit device, which comprises a first IIL element section which is for a Operation with a first injection flow is set up, and a second IIL element section adapted to operate on a different from the first injection stream second injection stream, the injection areas of the first and second IIL element sections with a single injection flow

source are connected and a device for establishing this second injection stream with the injection area of the second IIL elementary section is connected.

Embodiments of the invention are described below in Connection described with the accompanying drawing. On this shows or show

1 shows the pattern of an IC chip relating to the invention in plan view,

Fig. 2 shows a logic circuit relating to the invention
(or frequency divider circuit),

3a shows an IIL inverter circuit relating to the invention,
30th

Fig. 3b shows the logic circuit of Fig. 3a,

Fig. 4 shows a logic circuit which the flip-flop circuit shown in Fig. 2 in greater detail
shows, "'

5 is a top view of a portion of the IC according to an embodiment of the invention;

6 is a schematic circuit diagram of the IC of FIGS. 5, 5

Figs. 7a-sectional views showing the manufacturing process of ^1S in Fig. IC shown 5,

Figs. 8 top views of sections of ICs according to further embodiments of the invention,

11 is a section along line BB ¹ of FIGS. 9 and 10,

12 shows a plan view of a section of an IC according to a further embodiment of the invention,

Fig. 13 is a section along line C-C of Fig. 12,

14 is a plan view schematically showing an IC according to another embodiment of the invention such as

that gives

15 shows a top view of a portion of an IC according to yet another embodiment of the invention.

The invention will now be described in detail in connection with concrete embodiments thereof.

Fig. 5 is a plan view showing a portion of an IC according to the invention and showing the portion in detail with the IIL elements, this section being made up of a fast IIL element section 2a and a slow IIL element section 2b, as shown in particular in FIG is.

In Fig. 5, 1 denotes a semiconductor substrate made of silicon, in which an annular semiconductor region 3 is formed. The fast IIL element section 2a and the slow IIL element section 2b are present in an island region 4 enclosed by this semiconductor region 3. These IIL element sections 2a and 2b are composed of an elongated injection area 5 which is selectively formed, a number of base areas Bw B-, ..., B which are formed along both sides of this injection area 5, and a number of exit areas (or . Collector areas) OUT ₁ , OUT "and OUT ₃ , which are selectively formed in these base areas Bw B ₂ , ... and B, respectively. In other words, a number (namely, m) of ILL inverter circuits as shown in Fig. 3a are constructed by the indicated ranges. For example, the PNP transistor Q .. in such an IIL inverter circuit shown in FIG. 3a is a transistor with such a lateral structure that its emitter is from the injection region 5, its base from the island region 4 and its collector from the base region B ₁ . Furthermore, the NPN transistor Q _{2 is} a transistor with an inverse structure such that its emitter is from the island region 4, its base is from the base region B ₁ and its collector is from the output _{regions OUT 1} , OUT ₂ and OUT ₃ .

"The points to be observed in the IC shown in FIG are that the above-mentioned fast IIL element section 2a and slow IIL element section 2b can be controlled by a single injection current source 7, and that the injection current for the slow IIL element section 2b by the resistance section R to the injection current for the fast one IIL element section 2a is kept different. In other words, according to the specific one shown in FIG IC according to the invention does not have separate injection power sources for the tight IIL element section 2a

and provided for the slow IIL element section 2b. The injection power source 7 is provided with an injection section 5a for the fast IIL element section 2a connected via a metal layer made of a highly conductive metal such as aluminum. Further the surface of the injection section 5a is coated with a metal layer 6a, which is also made of a highly conductive Metal such as aluminum is made, which means that the elements in the individual IIL element sections of the Let fast IIL element section 2a make flowing injection streams uniform.

A resistor section is located in the slow IIL element section 2b which determines the injection flow for this slow IIL element section 2b. This Resistance portion R makes use of a portion of the injection area 5 and is made simply by that a portion of the injection area 5 is made narrower and that this portion is prevented is coated with the metal layer. Further, the surface of an injection portion 5b is for the slow one IIL element section 2b coated with a metal layer 6b made of a highly conductive metal such as aluminum, whereby a standardization of the flowing into the individual IIL elements of the slow IIL element section 2b Injection currents can be achieved. Further, these metal layers 6a and 6b (i.e., the first wiring layers) are coated with an interlayer insulating film (though not shown) on which, for example, the Metal layers 6a and 6b intersecting second wiring layers La and Lb, as shown with thick lines Lines are indicated, are formed. In particular, an IC in which the injection area 5 is in a linear shape is formed and which with the IIL element section to be used together for the multiple IIL elements . Is designed as shown in Fig. 5

is required to have the above-described two-layer wiring structure have to facilitate the wiring arrangement and improve the integration density.

In the following, the reason will be explained with reference to FIG. 6, why with the device according to the invention the task at hand is solved and the intended goals are achieved.

FIG. 6 is an IIL circuit diagram showing the IC of FIG. 5 essentially as an equivalent circuit diagram. In Fig. 6, the same injection currents I. flow. (a) through the individual IIL elements (or IIL inverters) INV, INV ₁ , ..., ^INV -] 7 ^the fast IIL element section 2a, since the surface of the injection section 5a is coated with the metal layer 6a. On the other hand, the same injection currents I. .. (b) flow through the individual IIL elements INV ₁ Q, ..., INV of the slow HL-. .-. ■. - - ι ο m

Element portion 2b, since the surface of the injection portion 5b is coated with the metal layer 6b. However, because of the presence of the resistor portion R, the voltage at a point B becomes lower than that at a point A. As a result, the injection current I.. (B) becomes far lower than the injection current I,. (a). Furthermore, since many IIL elements are formed in the slow IIL element section 2b, even a slight voltage drop across the resistor section R can reduce the injection current 1.J _n -! (k) substantially reduce each of the IIL elements. In particular, it is sufficient if the resistance value of the resistor section R is 10 to 30Jd. lies.

For the reason described so far, it is possible that a sufficiently high injection current (e.g. I.. (A) = 20 to 30 μΑ) through the fast IIL element section 2a can flow so that rapid operation can be performed. On the other hand, it becomes possible that a low injection current (e.g. I. (b) = 5 up to 6 μΑ) through the slow IIL elementary section 2b can flow so that the current would take in this section

can decrease. On the other hand, as stated above, the fast IIL element section 2a and the slow IIL element section 2b can be controlled via a single power source 7, it is unnecessary to each have their own Injection power source for the individual IIL elementary sections to be provided. It is therefore possible to improve the circuitry performance and the integration density of the IC to improve considerably.

Next, referring to the TTign. 7a to 7f, the manufacturing method for the IC shown in FIG. 5 is described. In FIGS. 7a to 7f, the sections on the left represent the manufacturing steps for a vertical transistor in the linear element section. In contrast, the sections on the right represent the manufacturing steps for the IIL elements, in particular the IIL elements in the line AA ¹ of FIG. 5. The symbols or numbers in brackets correspond to those appearing in FIG.

(a) First, as shown in FIG. 7a, for

Formation of N regions 11 and 12, an N impurity such as antimony is selectively introduced into a P silicon substrate 10 having a resistivity of 20 to 50 JLm. Further, an N impurity having a relatively high diffusion coefficient, such as phosphorus, is selectively introduced into the N region 12 to increase the current gain of the inverse transistor Q ₂ in the IIL elements, thereby forming an N region. This N region 13 can be formed by ion implantation. Thereafter, an epitaxial N.sup.2 layer 14 is formed on the entire surface of the silicon substrate 10. This epitaxial layer 14 has a resistivity of 2.5 µm and a thickness of about 13 µm.

(b) As shown in Fig. 7b, the surface of the

epitaxial layer 14 with an insulating film, for example

as a silicon dioxide (SiO ₃ -) film 15, a thickness of 0.8 μπ coated. This SiO ₂ -FiIm 15 can easily be formed by thermal oxidation of the surface of the epitaxial layer 14. Furthermore, the SiO ₃ film 15 is selectively removed and, in order to form a P region 16 for separation purposes, a P impurity, such as boron, is introduced into the exposed part of the epitaxial layer 14. In addition, the SiO film 15 is selectively removed and an N impurity such as phosphorus is introduced into the exposed part of the epitaxial layer 14 to form an N region 17. This N region 17 is carried out by ion implantation similar to the aforementioned N region 13 in order to increase the current amplification factor of the inverse transistor Q ₂ .

-ic) As shown in Fig. 7c, the SiO ~ film is selectively removed to reduce the collector resistance of the transistor constituting the linear circuit, and an N-impurity (e.g., phosphorus) is introduced into the exposed part of the epitaxial layer 14 . By spreading and diffusing this N impurity, an N region 18 is formed so as to contact the N region 11. During this spreading and diffusion process, the N regions 11, 12 and 13 _r, the P region 16 and the N region 17 are also spread out, and the N region 13 and the -N region 17 with one another and the P ⁺ - Area 16 brought into contact with the P substrate 10. This contact between the P region 16 and the P substrate 10 forms an island region 19 which is electrically isolated from the linear circuit section.

(d) As shown in Fig. 7d, an SiO ₃ film 15 'formed on the surface of the N region 17 is selectively removed, and a P impurity (for example, boron) is introduced into the exposed part of the N region 17 to thus to form a P region 20 with a sheet resistance of 13 _n_ / D. This P ⁺ region 20 forms the in-

jection (or emitter) area of the lateral transistor Q ₁ in the IIL element. On the other hand, this P region 20 is formed simultaneously with the emitter and collector regions (not shown) of the lateral transistor in the linear element section.

(e) As shown in Fig. 7e, the SiO "films 15 and 15 'are selectively removed and a P-type impurity (for example, boron) is introduced into the exposed part of the epitaxial layer and the N-region 17 to thereby form P-regions 21, 22, 23 and 20 ″ of a sheet resistance of 200 iVC2. The P region 21 forms the base region of the vertical transistor in the linear element section. On the other hand, the P regions 22 and 23 form the collector region of the lateral transistor Q ₁ and the base region of the inverse

* Transistor Q ₉ , both in the IIL elements. As can be seen from the figure, the P region 20 'is wider than the P region 20 to such an extent that it, together with the

P regions 22 and 30 the base width of the lateral transistor 20

Q ₁ determined. The formation of this P-area 20 'is extremely important with regard to ensuring a predetermined base width. In detail, the P-region 20 'and the P-regions 22 and 23 are formed with a single etching mask. As a result, there is no base width spread. If the P region 20 ′ is not formed, the base width of the lateral transistor Q _{1 is} determined by the P region 20 and the P regions 22 and 23. In such a case, however, separate photo-etching masks have been used to form the P-region 20 and the P-regions 22 and 23. The result is that the spread of the base width due to errors in the provision of the masks or the like in register is considerably increased.

_{(f) As shown in Fig. 7f, the SiO 9} - formed on the surfaces of the P regions 21, 22 and 23

Films selectively removed and an N-impurity.

e.g. phosphorus) is introduced into the exposed part of the P regions 21, 22 and 23 and thus N ⁺ regions 24, 25, 26, 27 and 28 are formed. The N ⁺ region 24 forms the emitter region of the aforementioned vertical transistor. On the other hand, the N -regions 25, 26, 27 and 28 form the output regions (or collector regions) of the aforementioned inverse transistor Q-. Thereafter, electrodes 29 to 38 are formed for areas 24, 21, 18, 16, 25, 26, 20, 27 and 28, respectively. Thereafter, but not shown, the silicon substrate 10 is coated with an interlayer insulating film made of a material excellent in moisture resistance such as polyisoindroquinazolinedione (ie, one of the polyimide resins), and a second wiring layer is formed on this interlayer insulating film. The resistor section.R shown in FIG. 5 is present in a section of the P region 20 because, as can be seen from FIG. 7f, the electrode is not formed over the entire surface of the P region 20.

The IC of FIG. 5 is manufactured according to the steps described.

The method described can also be modified so that the resistor section R having Injection region 5 is not formed in step (d), but rather in step (e) together with P-regions 21, 22 and 23 will.

As can now be seen from the method described, the formation of the resistor section is required in particular R no special and added process step for this resistor section R, its design can rather be achieved simply in that the surface of the section of the injection area 20 from the metal layer is left uncoated.

The invention is not limited to the embodiment described, but includes modifications such as they are described below.

(1) The IC shown in Fig. 5 is constructed so that the fast IIL element section and the slow IIL element section are connected in cascade, but a modification is possible to the effect that the fast IIL element section 2a and the slow IIL element section 2b, as shown in FIG. 8, connected in parallel are. In this FIG. 8 there are sections which from Fig. 5, provided with identical symbols or reference numerals. The IC of FIG. 8 becomes abso-0 Manufactured in the same process as the IC of FIG.

(2) Figs. 9 and 10 are plan views of modified structures of the IIL element section. In detail Fig. 9 shows a modified structure of a resistor section R formed in an IC in which the fast IIL element section and the slow IIL element section, as shown in Fig. 5, are connected in cascade. On the other hand, Fig. 10 shows a modified one Structure of a resistance portion R formed in an IC in which the fast IIL element section and the slow IIL element section, as in FIG. 8 shown, are connected in parallel. In FIGS. 9 and 10 have portions corresponding to those in Fig. 5,. identical symbols or reference numerals as there.

The one in FIGS. ^{Resistance section R 1} shown in FIGS. 9 and 10 is produced simultaneously with the output areas (or collector areas) OUT ₁ and OUT ₂ . In detail, this resistance area R ^{1 is} selectively formed in the injection area 5 at the same time as the N ⁺ areas 24, 25, 26, 27 and 28 shown in FIG. 7f. CH., CH ₂ # CH _3, and CH- denote contact holes formed in the insulation film (ie, the SiO film) 15.

11 is a section along line BB ¹ of FIGS. 9 and 10. In this figure, the injection region is simultaneous with the base region of the vertical transistor

»W · ■« ν

- 1Θ -

Linear element section formed. Another possibility, however, consists in forming this injection region 5 at the same time as the emitter and collector regions of the lateral transistor of the linear element section. According to the embodiment just considered, the resistance section R ¹ and the injection area 5 are biased in terms of potential in opposite directions or biased, since they consist of an N area on the one hand and a P area on the other. As a result, the resistor portion R ^{1 can be} sufficiently used as a resistor.

Furthermore, a resistor with a low resistance value can be easily formed.

(3) Fig. 12 is a plan view showing a modified one Shows the structure of the other IIL element section. Fig.

13 is a section along line C-C of FIG. 12. In FIG. 12 are sections which correspond to those from FIG. 5, with identical symbols or reference numerals as provided there.

According to this embodiment, as can be seen from FIG. 12, the injection region 5 and the base regions B _{1 , B 1, B 1} and B are enclosed by an N region 100 of high foreign matter concentration formed at the same time as the output regions OUT 1 and OUT. except for the sections where the injection area 5 and the base areas B ₁ to B .. are opposite one another.

By providing this N region 100, charge carrier leakage across the injection region 5 and the base regions B ₁ to B can be reduced, which makes operation even faster and further reduces power consumption.

(4) As shown in Fig. 14, resistor sections Ra, Rb and Rc can have different resistance values are connected to respective injection sections 5a, 5b and 5c so that injection flows different from each other at the relevant injection areas 5a, 5b and

5c can be established. These resistance sections Ra, Rb and Rc can have different structures, such as they have been described above.

(5) The invention can also, as shown in Fig. 15, in an IC application that has independent injection areas 5a. and 5b for the IIL elements 2a and 2b is trained. In detail, the IIL elements 2a and 2b are connected to the single injection current source 7 via a metal layer 6, whereby it is the IIL element 2b which is set up for slow working and whose injection region 5b forms the resistance section R. This Resistor portion R can also take a variety of configurations as described above are.

(6) The resistor portion R described makes use of a semiconductor region formed in the semiconductor substrate is, but should not be limited to. This resistor section R can be a semiconductor region, for example polycrystalline silicon, which is formed on the surface of the insulating film over the semiconductor substrate is. The use of such polycrystalline silicon is effective for an IC having one of the linear element section contains different section for insulating layer field effect elements. In detail can the polycrystalline used for the resistor section R. Silicon is formed at the same time as the gate electrode of the portion of the insulating layer field effect elements will. The section of the insulating layer field effect elements is made up of an N-channel MISFET, complementary MISFETs or the like constructed.

As is apparent from the description so far, the present invention is effective for an IC having an IIL element section has, and moreover of particular effectiveness when the number of IIL elements in slow

35. IIL element section 2b considerably larger than the number

of the IIL elements in the fast IIL element section 2a is. This is because the power consumption in the slow IIL element section 2b with the large number of IIL elements due to the presence of the resistor from 5 Section R can be sufficiently decreased.

Ki / s

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Claims (8)

PATENT LAWYERS ■ ■ '.. "" .. ".: .. OOO CL Λ Ο STREHL SCHÜBEL-HOPF SCHULZ WIDENMAYERSTRASSE 17, D-8Q00 MUNICH 22 HITACHI, LTD. September 24, 1982 DEA-25 76 3 Semiconductor integrated circuit device and method for making the same PATENT CLAIMS Semiconductor integrated circuit device, characterized in that a semiconductor substrate (1), a first IIL element section (2a) formed in the semiconductor substrate for operation with a first injection stream and a second IIL element section (2b) formed in the semiconductor substrate for one Operation with a second injection flow different from the first injection flow are provided and that Injection areas (5) for the first and second IIL element sections are connected to a single injection power source (7), one with at least the Injection area for the second IIL element section connected device for establishing the second injection stream is provided. 2. Integrated semiconductor circuit device according to claim 1, characterized in that the second IIL element section (2b) for a slower one Operation as the first IIL element section (2a) is set up and that the second injection flow is smaller than the first injection stream. 3. Integrated semiconductor circuit device according to claim 1, characterized in that the device for establishing the second injection flow is constructed from a section (R) of the injection region (5) and this section of the injection area is not coated with a metal layer (6b). 4. Integrated semiconductor circuit device according to claim 1, characterized in that the means for establishing the second injection current is composed of a semiconductor layer formed on the surface of an insulating film over the semiconductor substrate.
25th 5. Semiconductor integrated circuit device characterized by a common semiconductor substrate (1), a linear element section (3) formed in the semiconductor substrate, one in the semiconductor substrate formed IIL element section (2), which has a first IIL element section (2a) for a Operation with a first injection stream and a second IIL element section (2b) for operation with a second injection flow that is different from the first injection flow contains, with a common injection power source (7) connected injection areas (5) for the first and second IIL element sections, and one with Means connected to the injection area for the second IIL element section for establishing the second injection flow. 6. Integrated semiconductor circuit device according to claim 5, characterized in that the second IIL element section (2b) for lower speed operation than the first IIL element section (2a) is set up and the second injection flow is smaller than the first injection flow. 7. Integrated semiconductor circuit device according to claim 5, characterized in that the device for establishing the second injection flow is constructed from a section of the injection region (5) and this section of the injection area is not coated with a metal layer (6b). 8. A method for manufacturing an integrated semiconductor circuit device, characterized by fabricating a semiconductor substrate having first and second semiconductor regions of a first Conduction type / which are separated from each other, the selective formation of an elongated third semiconductor region a second conductivity type opposite to the first conductivity type in the second semiconductor region, the selectively forming both a fourth semiconductor region of the second conductivity type in the first semiconductor region and also a number of fifth semiconductor regions of the second conductivity type in the first semiconductor region along the third semiconductor region, the selective formation of both a sixth semiconductor region of the first conductivity type in the fourth semiconductor region and a number of seventh semiconductor regions of the first conductivity type in number 0 fifth semiconductor region, and coating both the surface of a first portion of the third semiconductor region as well as the surface of a second section thereof, which is spaced from the first section a metal layer, wherein a transistor of a linear element section from the first semiconductor region, the fourth Semiconductor area and the sixth semiconductor area - 5 - is constructed, with a first IIL element from the second Semiconductor region, the first section of the third semiconductor region and a fifth and seventh semiconductor region, which are formed along the first section, and wherein a second IIL element is composed of the second semiconductor region, the second portion of the third semiconductor region, and a fifth and seventh Semiconductor regions formed along the second portion is constructed. 10