DE3210662A1 - COMPANER SYSTEM - Google Patents

Description

European patent representative "" Dlpl.-Ing. Günther Koch

European Patent Attorneys, “Dipl.-Phys. Dr Tino Haibach

· ~> 7 · (- Dipl.-Ing.Rainer Feldkamp

D-8000 Munich 2 Kaufingerstraße 8 Telephone (0 89) 2 60 80 78 Telex 5 29 513 wakai d

Date: Mar 23rd Z 1982

Our reference: 17 4θβ - Fk / Se

Applicant: DBX, Inc.

71 Chapel Street

Newton, Massachusetts 02195

United States

Title: Compander System

Priority: 247,830

United States
March 26, 1989 I.

The invention relates to signal companders and more particularly to an improved signal compander that is suitable for training as an integrated circuit.

As is known, compander systems are used to compress the dynamic range of an audio frequency signal prior to transmission or recording to a medium having a limited dynamic range as well as expanding or stretching the dynamic range of the transmitted or recorded signal on subsequent playback so that the signal has a larger dynamic range than otherwise would be possible due to the limitations of the transmission or recording medium.

A well-known compander system of this type (US-PS 3 789 14-3) uses two basic components, viz a "gain control module with a voltage controlled amplifier as well as a signal detector that is used to generate of the voltage control signal is used for the amplifier will. A well-known voltage controlled amplifier is described in U.S. Patent 3,714,462. The detector preferably includes circuitry for detection the current rms level of the input signal, and an example of such a detector is described in U.S. Patent 3,681,618.

The voltage controlled amplifier generally applies a controlled gain to the input signal, so that the dynamic range of the transmitted or

recorded signal is either compressed or stretched during playback. The amount of compression or the stretching depends on a selected compression or stretching factor. With the known compander system according to US-PS 3,789,143, the control signal is from a logarithmic function of the current rms value level of the input signal is derived to be an expansion or compression as a function of the instantaneous rms level of the input signal. However, it is understandable that other detection methods, such as a determination of the peak value or a Determination of the mean value can be used.

The invention is based on the object of providing a less complex compander system of the type mentioned at the beginning create, which is preferably readily producible in the form of an integrated circuit, and other improvements compared to known compander systems.

This object is achieved by the invention specified in the characterizing part of claim 1.

Advantageous refinements and developments of the invention result from the subclaims.

The compander system according to the invention has an improved one Gain control module and an improved signal detector for providing the gain control signal to the gain control module in such a way that the information signal is dependent on the gain setting the system is compressed or stretched.

The invention is illustrated below with reference to in the drawing illustrated embodiments explained in more detail.

In the drawing show:

lig. 1 is a block diagram of the basic components a compander system,

2 shows a block diagram of the essential components of a preferred embodiment of the compander system,

Pig. 3A and 3B are a circuit diagram of the preferred embodiment of the gain control module of the embodiment of the compander system according to lig. 2,

Figures 4A and 4B are a circuit diagram of a preferred embodiment of the Döfcektor of the embodiment of the Compander system according to Pig. 2.

In Pig. 1, there is shown a block diagram of a basic compander system that includes a gain control module 10 and a detector 12 includes. The gain control module adjusts the gain applied to the voltage input terminal 14 supplied input signal E. is impressed as a puncture of the control signal that from the detector 12 is supplied. Depending on the gain setting of the module 10 results in the impressed Gain either an amplification or a weakening of the input signal, so that the

Output signal E, at output terminal 16 results. For a compression of the detector in the form of a feedback circuit is provided (in which the detector, the output signal e. Am from gangs ansciiluß 16 determines) or it is a forward control circuit used (in which the detector 12, the input signal E _ia on Bingangsanschluß 14 determines) both forms are shown in FIG. For stretching or expansion, the feedforward control form is typically used. In both embodiments, the detector delivers the control signal as a function of the measurement signal.

In the embodiment of the compander system shown in FIG the gain control module 10 includes Input stage 18, the input of which is connected to the voltage input terminal 14, while the output is connected to the voltage controlled amplifier cell 20 is connected. The output of the amplifier cell 20 is connected to the output terminal 16 of the system and suitably biased by a bias generator 22 "

The detector 12 connected to the module 10 in a forward control circuit has a rectifier 24 for detection of the input signal at the voltage input terminal 14 and to rectify the input signal. The output of the rectifier 24 is with the logarithmic section 26 connected, which is an output signal as a function of the logarithm of the output signal of the rectifier 24 provides. A log filter 28 converts this logarithmic output signal of the Logarithmierabscnnittes 26 essentially in a DC voltage signal, the in turn the input of a buffer amplifier 30

is fed. The output of the amplifier 30 is connected to the control signal input of the voltage controlled amplifier cell 20 connected.

As can be seen from FIGS. JA and 3B, it closes the gain control module has an input stage 18 (Fig. a voltage controlled amplifier cell 20 (Fig.

a bias generator 22 (Fig. 3B) and a Power supply 32 (Fig. 3-A-).

The one shown in Fig. 3-A. is the power input terminal 14A shown identical to the voltage input terminal 14 according to FIGS. 1 and 2, but with the exception that this input is so is modified that it has the input current I. as a function of the input voltage E. receives in a well known manner. The input terminal 14A is connected to the input of the input stage 18 and the input of the voltage-controlled Amplifier cell 20 connected. The input stage 18 is detailed in the DE-OS ... (registration of the same Days, our file number 17 405). The input port 14A is connected to the input terminal of stage 18 formed by connection point 40. The connection point 40 is connected to the base of the buffer transistor 42. The emitter of this transistor is connected to the input 44 of a differential amplifier, which is generally designated 46, while the collector this transistor is connected to a current generator device, generally designated 48, which generates a current through transistor 42 to reduce the amount of bias current carried by the stage 18 is derived from the input terminal 14A.

In detail, this current generator device 48 closes Transistors 50, 52, 54, 56 and 58 on «. The basis of the Transistor 50 is via connection point 40 with the Base of transistor 42 connected while the bases of transistors 52 and 54 are connected together. Of the The emitter of transistor 54 is connected to the collector of the Connected to transistor 42, while the collector of transistor 54 to the base and collector of one as Diode switched transistor 58 is connected. The collector of transistor 52 is connected to the emitter of transistor 50, while its emitter is connected to the collector and the base of a diode-connected transistor 56 is connected. The emitter of transistor 58 and the collector of transistor 50 are connected together and to system ground, while the emitter of the transistor 52 and the collector and base of transistor 56 are connected to the collector of a transistor 60 are. The base of this transistor 60 is connected to the base and collector of a transistor 62, whose Emitter to the emitter of transistor 60 and to the upper supply voltage terminal 64 (shown in Fig. 3B) connected is.

The differential amplifier 46 has two differential elements formed by transistors 66 and 68. The base of the transistor 66 is connected to the input 44, while the collector of this transistor is connected to the .Stromspiegel via a resistor 70, the is indicated generally at 72. The emitter of transistor 66 is connected to system ground and via a capacitor 74 via a resistor 76 to a connection point 78 tied together. The base of transistor 68 is on

, -., -, 3210362

Connection point 80 is connected to system ground, while the collector of this transistor is connected to current mirror 72 is. The emitter of the transistor 68 is connected to the collector and the base of a diode Transistor 82 connected. The emitter of the transistor 82 is connected to the connection point 78 via a resistor 84- tied together. The current mirror 72 is through the transistors 86 and 88 are formed, the base electrodes of which are connected to each other and their emitters via respective resistors 90 and 92 are connected to the upper operating voltage connection 64. The collector of transistor 86 is with the resistor 86 and a capacitor 94- with connected to its base electrode. The collector of transistor 88 is direct with its base electrode and with connected to the collector of transistor 68. The output of differential amplifier 4-6 is at junction 96 between the collector of transistor 66 and the resistor 70 is supplied. The connection point 96 is connected to the base of a transistor 98, the collector of which is connected to the collector and base of transistor 62 and the base of transistor 60 is connected, while the emitter of transistor 98 is connected to the base of an in 3B is connected to transistor 100 shown in FIG. Of the Emitter of the transistor 98, the connection point 78 and the connection point 44- are in a suitable manner with the Power source 32 connected.

As in the DE-OS ... (our sign 17 405 of the same Filing date), transistor 42 and current generator means 48 reduce the input bias current, derived from the input current at input terminal 14A without the

321066

Gain bandwidth product of this stage is affected. In detail, the bipolar transistor 42 forms one Buffer stage between input terminal 14A and the rest Share stage 18. The current generator device 48 generates a current through the bipolar transistor 42, so that the magnitude of the bias current derived from the remainder of the stage 18 is reduced, without affecting the gain bandwidth product of the stage. Furthermore allows the use a bipolar transistor 42 an easy adaptation and implementation of the overall circuit in the form of an integrated Circuit as described in the aforementioned DE-OS. The use of the capacitor 94 and of resistor 70 result in a zero (a hull is defined as the value of the complex frequency at which the Transfer function of the circuit to JTuIl) in the Transfer characteristic of stage 18, so that the 90 ° phase shifts caused by the feedback loop the stage generated by the voltage controlled Amplifier cell 20 is formed, are negated and a stability of the circuit is achieved. Through the Connect diode 82 to the emitter of transistor 68 and match the impedance of the resistor 76 to the combined impedances of diode 82 and resistor 84 becomes the noise contribution from the power supply 32 at the exit of the connection point 96 is reduced. Finally, the insertion of the capacitor leads inserts a zero in the transfer characteristics of the amplifier and stage, whereby the pole (is a pole defined as the value of the complex frequency at which the transfer function of the circuit becomes infinite) is negated, which is caused by the parasitic base-emitter

Capacitance of the transistor 66 is introduced.

As can be seen in Figure 3B, it is the collector of the transistor 100 to the upper supply voltage connection 64 connected while the emitter of this transistor is connected to a connection point 112 via a resistor 110. This connection point forms a bias terminal for the voltage controlled amplifier cell 20.

The voltage-controlled amplifier cell 20 is described in more detail in DE-OS 31 08 617. The connection point 112 is via a resistor 114 to the collector a secondary logarithmic transistor 116 connected. The emitter of the secondary logarithmic transistor 116 is connected to the emitter of a primary logarithm transistor 118. The collector of the transistor 118 is connected to a connection point 120 which in turn connects to the input port 14A of the module is. The connection point 120 is also to the collector of a primary logarithm transistor 122 whose emitter is connected to the emitter of a secondary logarithm transistor 124. The collector of transistor 124 is connected to a connection point 128 via a resistor 126. The connection point 128 forms the second bias terminal of the voltage controlled amplifier cell 20, so that the Resistor 114, the secondary log transistor 116, the primary log transistors 118 and 122, the secondary logarithm transistor 124 and resistor 126 a circuit load for bias generator 22 form. The connection point 112 is still via a

Resistor 130 connected to the collector of a secondary antilog transistor 132, the emitter of which is connected to the emitter of an antilog transistor 134-. The collector of transistor 134- is connected to junction 136, which in turn is connected to current output terminal 16A of the module. The current output connection 16A thus supplies the current output signal I ₀₁ J. of the module 10. I ₀₁ *. can easily be converted to the voltage E ^ in a well known manner. The connection point 136 is further connected to the collector of a primary antilog transistor 138, the emitter of which is connected to the emitter of a secondary antilog transistor 140. The collector of the secondary antilog transistor 140 is connected to the junction point 128 through a resistor 14-2. Resistor 130, secondary antilog transistor 132, primary antilog transistors 134 and 138, secondary antilog transistor 140, and resistor 142 form another circuit load between junctions 112 and 128 for bias generator 22. The base of the primary logarithm Transistor 122 is connected to the base of primary antilog transistor 134 and to control signal terminal 144 which receives the control signal from the terminal of detector 12 described with reference to Figures 4A and 4B. The base electrodes of transistors 118 and 138 can be connected to respective terminals 146 and 148 for receiving direct currents between positive and negative input signals in order to ensure gain symmetry, as will be explained in more detail below. The base electrodes of each of the secondary transistors 116 and 132 are each cross-coupled to the collector of the other transistor, and in the same way

3210S62

Way, the base electrodes of the secondary transistors 124 are wad. 146 cross-coupled to the other collector.

As described in detail in DE-OS 31 08 617 is, each is a primary logarithm transistor 118 and each with a secondary logarithm transistor 116 and 124- connected to two composite log devices to form, each in a separate return path between the input and the output of the Stage 18 are arranged. The primary transistor 118 is a PfTP transistor, while the primary transistor 122 is is an NHT transistor. Each of transistors 118 and 122 is connected to a secondary transistor of the opposite conductivity type. Act accordingly they are called "composite logarithm transistors", each having a logarithm signal as a function of the logarithm of the corresponding one of the two polarities of the input signal at terminal 14A.

As will be explained in more detail, the Stetxersignal is at terminal 144 - a function of the logarithm of the instantaneous rms value of the input signal at the terminal 14A. The control signal becomes the logarithmic signals through the base electrodes of the primary transistors 122 and 134- added. Each of the primary antilog transistors 134 and 138 are of opposite conductivity types each with a secondary antilog transistor 132 and 14-0 of opposite conductivity type connected to two compound antilog devices each for to form a different polarity of the input signal. The transistors 132, 134-, 138 and 140 act as "antilog-

321

Transistors "to an antilog signal as a puncture of the Antilogarithm of the sum of the corresponding logarithm signal and the control signal. The logarithm transistors 116 and 118 and the antilog transistors and 134 · thus form a logarithm-antilogarithm transmission path for a polarity of the input signal, while the logarithmic transistors 122 and 124 and the Antilogarithm transistors 138 and 140 a second Form the logarithm-antilogarithm transmission path for the other polarity of the input signal.

As described in DE-OS 31 08 617, all RPN transistors are preferably with regard to their Tbe / Ic transmission properties adapted. In the same In this way, all ENP transistors are matched to one another. the secondary transistors form in the logarithm-antilogarithm transmission path arranged signal modification devices to reduce the distortions that result from the natural base and emitter resistances of the logarithm and antilogarithm transistors. A correction is made by comparing the input current and the output (antilog) current of springs Logarithm-antilogarithm path derived. In detail a correction signal is derived from the voltage differential that exists between the collector voltages of the cross-coupled secondary transistors of each log-antilog path is produced. The correction signal is used to reduce the distortion at the output terminal 16A due to the natural parasitic base and emitter resistances of the transistors in the amplifier cell 20 delivered. Some mismatch of the parasitic base and emitter resistances each

3210562

composite pair of transistors 116, 118; 122, 124 x; 132, 134- and 138, 140 can easily be compensated for by this that the respective resistors 114, 126, 130 and 142 are balanced accordingly.

The bias generator 22 is suitably on at junction points 112 and 128 to provide a bias signal through the circuit load that the Includes transistors 116, 118, 122 and 124, and by the circuit load that transistors 132, 134, 138 and 140 includes. The generator 22 is more detailed in DE-OS ... (our file number 17 403 from the same filing date) ". The generator 22 is designed to produce a bias voltage between connection points 112 and 128 of amplifier cell 20, this bias being so programmable by an input current from power source 32 to generator 22 is that the resulting bias current through the logarithm transistors and the resulting Bias current through the antilog transistors is equal to and proportional to the input current, independently on the temperature, so that these bias currents track the input current.

The generator 22 closes a first resistor 150 one, one of which is connected to connection point 112 and the other connection to connection point 154 connected is. A resistor 152 is with the resistor 150 at connection point 154 as well as with the connection point 128 connected. The connection point 112 is further connected to the collector of an NPN transistor 156, its emitter with the emitter of a HiP transistor

158 is connected. The NPH transistor 156 is matched in terms of its Vbe / Ic transfer characteristics to the ΈΈΕ transistors 116, 122, 132 "and I38, while the HTP transistor I58 is adapted in the same way to the PNT transistors 118, 124, 134 and 140 of the Amplifier cell 20. The base of transistor 158 is connected to junction 154, while its collector is connected to the base of transistor 150. The emitter of transistor 160 is connected to the base of transistor 162. The collectors of transistors 16 and 162 are connected to each other and to the base and collector of transistor 156 and thus to junction 112. The emitter of transistor 162 is connected to junction 128. The base of transistor 158 is connected to the anode of a diode 164, the cathode of which is connected to the base of transistor 160. The base of transistor 160 is connected to a constant current source formed by power supply 32 t will.

As described in DE-OS ... (our .Akenzeichen X] 403 from the same filing date), the current from source 32 to the junction of the collector of transistor 158 with the base of transistor 160 is the programming input current for the generator. The collector current of transistor I58 is (disregarding the base current of transistor 158) equal to the current through the base-emitter boundary layers of the two transistors 156 and 158 and thus depends on this current. The transistors 160 and 162 form a subsequent stage with a voltage gain of one and a very high current gain.

.3210332

In operation, the current from the power source 32 to the base of the transistor 160 remains constant "and thus sets the Determines the level of bias applied across junctions 112 and 128. The size of the Emitter of transistors 156 and 158 current flowing defines the temperature-dependent voltage across resistor 150. The collector current of transistor 158 is approximately equal to the emitter current of transistor 158 and equal to the input current to generator 22, see above that the fault current input to the base of transistor 160 is approximately equal to Hull. If there is a change in the Emitter current of transistors I56 and I58 would occur, this would result in compensation by transistors 160 and 162 to correct this error. In detail if the emitter currents through transistors 156 and 158 increase, the voltage across the resistor would 150 magnified. The collector current of the transistor 158 would then increase. Because the input current from the If power source 32 remains constant, there would be a fault current equal to the difference between the collector current of transistor 158 "and the input current, and the voltage level at the base of transistor 160 would be compared to the voltage level at the junction 112 sink. This would reduce the current through resistors 152 and 150, so that the voltage along the base-emitter junctions of transistors 156 and 158 would otherwise be decreased a reduction in the emitter currents of the transistors 156 and 158 leads until the collector current of transistor 158 equal to the input current of. the source 32 becomes and the Residual current in the base of transistor 160 would go to zero.

On the other hand, if the emitter currents of the transistors ■ and 158 were decreased so that the tension along the Resistor 150 drops and the collector current of the transistor 15 ° is reduced, a fault current would which is equal to the difference between the collector current of the Transistor 158 and the input current is to the base of transistor 160 is applied. This would increase the voltage level from the base compared to the Connection point 112 occur. This, on the other hand, would increase the current through resistors 152 and 15Ο and the voltage across the base-emitter junctions of transistors 156 and 158 would increase. this leads to to an increase in the emitter currents in transistors 156 and 158 until the collector current of the transistor 158 again equals the input current from source 32 and the fault current into the base of the transistor becomes zero.

Correspondingly, a current-dependent voltage is generated across the resistor I50, which is the sum of the voltage drops across the base-emitter junctions of transistors 156 and 158. The temperature voltage drop along each circuit load between connection points 112 and 128 of amplifier cell 20 changes as a function of the sum of the voltage across the base-emitter interfaces the two NPN and the two PNP transistors, which interfere with the NPET and PNP transistors, respectively 156 and 158 are paired.

Therefore it is used to adapt the voltage-current-temperature characteristic of the generator 22 to the voltage-current-temperature characteristic of each circuit load

between the connection points 112 void, 128 it is necessary to multiply the voltage generated across the resistor 150 by the scalar 2. This is accomplished by setting the resistance of resistor 152 equal to the resistance of resistor 150 so that the current generated through resistor 150 will be a function of the voltage generated by transistors 156 and 158 across it Resistance is generated, is passed through the resistor 152 (neglecting the base current of the transistor 158) in order to generate an equal voltage. The voltages across resistors 150 and 152 add to produce the bias signal across each circuit load between connection points 112 and 128 of amplifier cell 20. It will be understood that when the gain control module is subjected to a change in ambient temperature, the change in the base-emitter voltage drops of transistors 156 and I58 by an equal change in the base-emitter voltage drops of each pair of EETP and NPN transistors in FIG every circuit load is balanced.

According to Pig. 3-A- the current source 32 closes a transistor 170 a, whose collector connects to the base of the transistor 160 of the bias generator 22 is connected. The emitter of transistor 170 is across a resistor 172 connected to a connection point 174-. The transistor 170 is thus in with transistors 176 and 178 Cascade connected so that the base electrodes of these transistors are connected to one another. The collector of the Transistor 176 is connected to the emitter of a transistor 177. The base electrode of the transistor 177 is with

J Δ Ί UO ζ) 4

- ar-

System ground, while the collector of this transistor is connected to the emitter of transistor 98 ' is. The collector of transistor 178 is with the connection point 78 connected to level 18. The emitters of the Transistors 176 and 178 are direct to the junction point 174 · connected. The base electrodes of the transistors 170, 176 and 178 are through a resistor 180 to the base of a transistor 182 and the collector of a transistor 184 connected. The collector of transistor 182 is connected directly to junction 4-4- of stage 18. The emitter of transistor 182 is connected to the emitter of transistor 170. The base electrodes of transistors 170, 176 and 178 are across a resistor 186 connected to the base of transistor 184-. The base of transistor 184 · is suitably um two diode voltage drops are connected below the system earth, by virtue of the fact that this base electrode is connected to system ground via two diode-connected transistors 188 and 190. The connection point 174 is connected to the base of a transistor 192 and to a terminal 196 via a resistor 194-. The emitter of transistor 192 is also connected to terminal 196, while the collector of this transistor is connected to the connection point 128 of the amplifier cell 20 via a resistor 198. The connection 196 can be connected in a suitable manner to a voltage source 202 via an external resistor 200 will. The nature of the power supply 32 is such that a constant current is always at the collector of the Transistor 170 is supplied wii'd so that the bias generator 22 according to the teachings of DE-OS ... (our file number 17 4-03 from the same filing date) works.

In the pig. 4A and 4B, the detector 12 is shown in detail. In addition to the rectifier 24 (Figs. 4-A and 4B), the logarithm section 26 (Figs. 4A and 4B), the logarithmic filter 28 (Fig. 4B) and the buffer amplifier 30 (Fig. 4B), the detector includes current sources 3OO and 302 (partially shown in Figures 4A and 4B, respectively are shown) and a voltage source 304 (Fig. 4A) a.

According to FIG. 4A, the voltage input terminal 14 is connected to a resistor 312 via a capacitor 310, which in turn is connected to the power input terminal 14B (which receives the power input signal I.). Of the Power input terminal 14B is connected to the input of rectifier 24.

The rectifier 24 includes the operational amplifier stage 32Ο and the bias generator 324. The rectifier 24 is structured as described in detail in DE-OS (our file number 17 404 from the same filing date) is.

In detail, the power input terminal 14B is connected to the Input connection point 330 of the operational amplifier stage 320 connected. The connection point 330 is with the The base of a transistor 332 is connected, the collector of which is connected to system ground and the emitter of which is connected to the Collector of a transistor 334- is connected. The connection point 33O is still with the base of a transistor 336, the emitter of which is connected to a connection point 338 and its collector with the emitter of a Transistor 34-0 is connected. The transistor 340 is with

3 1 IU bb 4

its base electrode with the base electrode of the transistor 334- and with its collector with the emitter one Transistor 34-2 connected. The base electrode of transistor 34-2 is connected to the emitter of transistor 334 uad with the voltage source 304- connected while the collector of transistor 342 to the collector of a transistor 34-4 and the base of a transistor 34-6 is connected. The base electrode of transistor 344- is connected to the base and collector electrodes of a transistor 34-8, while its emitter is connected to the emitter of transistor 34-8 and connected to the positive supply voltage terminal 350 is. The collector of transistor 34-8 is connected through a capacitor 352 to the base of transistor 34-6. The collector of transistor 34-8 is i-ieiterhin with connected to the collector of a transistor 354-, the base electrode of which is connected to system earth at 355 ffl and its emitter is connected to the connection point 338 is. The transistor 34-6 has its collector connected to the positive supply voltage terminal 350 connected while its emitter is connected to the base of transistor 356 and directly to current source 302. The collector of the Transistor 356 is connected to the positive supply voltage terminal 350, while its emitter is connected to a Anode of a first diode 358 is connected, the cathode of which is connected to the anode of a second diode 360. the Diode 360, with its cathode representing the output of stage 320, is of the same type with rectifier cell 322 connected that this rectifier cell is arranged in a feedback circuit of the amplifier stage 320, such as this in DE-OS ... (our file number 17 4-04 of same filing date).

3210-32

The rectifier cell 322 comprises three transistors 380, 382 and 38A-. The transistor 380 is an NPN transistor, which is connected as a diode in that its base is connected to the collector via a resistor 386 to form input 388 of rectifier cell 322. The input 388 is with the input of the amplifier stage 320 connected at junction 330. The transistor 382 is also an NPN transistor whose collector is connected to the cathode of a diode 398, whose Anode is connected to the output 400 of the rectifier cell. The emitter of transistor 382 is with connected to the emitter of transistor 380, while the base of transistor 382 via a resistor 390 with System earth is connected. The base of the transistor 382 is also connected to a terminal 392, which in turn via a resistor 394 with a potentiometer 396 is connectable. This potentiometer supplies a changeable current to the base of transistor 382, a gain symmetry between the current paths ensure that through transistors 380 and 382 on the one hand and formed by the transistor 384 on the other hand as in the aforementioned DE-OS ... (our file number 17 4-04 from the same filing date) is described. Finally, transistor 384, which is an iTPN transistor, has its emitter connected to its input 388 connected to the rectifier cell while its The base electrode is connected to the cathode of the diode 360 of the operational amplifier stage 32O and its collector is connected to the output 400 of the rectifier cell. As described in the aforementioned DE-OS limits the loop transmission of operational amplifier stage 320 through each of the paths that make up the

Transistor 380 or 384, if there is an amplification of one, thereby eliminating stability problems associated with unlimited loop transmission in the Rectification of positive input signals by a Rectifiers as described in U.S. Patent 4,097,767.

The bias generator 324 provides a bias between the base of transistor 384 and each other connected emitters of transistors 380 and 382, as in DE-OS ... (our file number 17 4-04- from same filing date). The bias generator 324 forms a signal generator means for Generation of the prestress between points 410 and 412. The bias signal is across a first impedance load applied, the first resistor elements in the form of a resistor 440 includes. Resistance 440 is connected to a second resistive element, resistor 442, which is part of a second impedance load forms between the base of transistor 384 and the connected emitters of transistors 380 and 382 is turned on. As will be explained in more detail below, the fact that the resistors 440 and 442 can be formed with the same resistance value, the bias voltage also between the base of the transistor 384 and the interconnected emitters of transistors 380 and 382 are applied.

In detail, the signal generator device closes a first current source with the transistors 414 and 416 Supply of a reference current IB, a second current source with a transistor 418 for supplying a reference current

3210 ^ 2

IA, zv / ei reference transistors 420 and 422 "and a second Paax of reference transistors 424 and 426. The emitter of transistor 414 is to the emitter of transistor 416 and the emitter of transistor 418 as well as to system ground -tied together. The collector and base of transistor 414 are connected to current sources 302 and to the base electrodes of transistors 416 and 418 connected. The collector of transistor 416 is connected to the base of one Transistor 434, whose collector is connected to the output of the logarithm section 26 is connected and its emitter with the base and collector of a as Diode switched transistor 436 is connected. Of the The emitter of the transistor 436 is connected to a connection point 412. The collector of transistor 416 is also connected to the collector of transistor 420, the base of which is connected to a connection point 410 and its emitter is connected to the collector and the base of the transistor 422 connected as a diode is. The emitter of the transistor 422 is connected to the negative supply voltage terminal 450 and to a resistor 428 connected. The collector of the transistor is connected as a diode to the base and the collector of a Connected to transistor 432, its collector is connected to connection point 410. The connection point 410 is to the base and collector of the connected as a diode transistor 424, the emitter of which is connected to the base and collector of the diode connected Transistor 426 is connected. The emitter of transistor 426 is to the common connection point of resistors 428 and 430 are connected. The resistance is in turn connected to point 412.

OL IUUUi

The base of transistor 432 is connected to the base of a Transistor 438, the emitter of which is connected through a resistor 440 is connected to connection point 412. The collector of transistor 433 is connected to the base and connected to the collector of a diode-connected transistor 444, the emitter of which is connected to the resistor 442 which in turn is connected to the base of transistor 384 of rectifier cell 322. The collector and the base of transistor 444 are connected to the base of transistor 446, the emitter of which is connected to the interconnected emitters of transistors 380 and 382 is connected and its collector to the negative Supply voltage connection 450 of the current sources 302 connected is. As described in DE-OS ... (our file number 17 404 from the same filing date) are the Transistors 420, 422, 424 and 426 each NM transistors, with respect to their Vbe / Ic characteristics to the NEN transistors 380, 382 and 384 of the rectifier cell 322 are adapted. Similarly, transistors 432 and 438 are of the same conductivity type and wise their Vbe / Ic characteristics are matched to one another, and the transistors 444 and 446 are also the same Conductivity type and in terms of their Vbe / Ic characteristics customized.

The rectifier 24 works in a manner as described in detail in the aforementioned DE-OS. Generally when the input current at junction 14A is negative, the output is at the cathode of the diode 360 of level 320 positive. This results in negative feedback via the base-emitter path of transistor 384 of the Rectifier cell 322. This, on the other hand, leads to the fact that

3210862

a current from the output at terminal 400 of the rectifier through the collector-base path of the transistor 384 to the input terminal 330 of the operational amplifier stage 320 flows. Transistors 380 and 382 are essentially non-conductive because of their base-emitter junctions are biased in the reverse direction.

For positive input currents at terminal 14B, the output of operational amplifier stage 320 is negative, the base-emitter junction of transistor 380 is forward biased and a current flows through this boundary layer. Essentially the same mirrored one Current flows through the collector of transistor 382 in order in this way to supply an inverted signal at output 400 for this polarity of the input signal.

The base of transistor 384 and the interconnected Emitters of transistors 380 and 382 are through the Bias generator 324 is biased to meet the single speed requirements of amplifier 320 decrease for a given level of operational characteristics.

Vie this in DE-OS ... (our file number 17 4-04 of same filing date) is the preload generated between points 410 and 412, equal to the voltage drop across the base-emitter path of transistor 424 plus the voltage drop along the base-emitter path of transistor 426 minus the voltage drop across resistor 430. In general, when the reference current IB is through the

Transistors 420 and 422 is equal to η times the reference current IA through transistors 424 and 426, the Voltage across the resistor 428 such that when they are affected by the voltage across a reference diode string (such as across transistors 420 and 422) is subtracted, a decrease in current caused by an adapted strand by a factor of η. The voltage across the resistor 4JO is then such that when they are affected by the voltage across the reference diode string of transistors 424 and 426 is subtracted, a reduction in the current through the matched strand by a factor η to the kth power (where k is the ratio of the resistance value of the resistor 4JO to the resistance value of the Resistance 428 is). Because the voltage between points 410 and 412 is the voltage drop across the from the As a diode connected transistors 424 and 426 existing diode string with respect to the voltage drop along of resistor 430 is and because transistors 424 and 426 en matched or with transistors 420 and 422 these are paired, as in US-PS ... (US patent application 137 427 of April 4, 1980) and in DE-OS ... (our file number 17 404 from the same filing date) is the circulating stream that is sent to the Transistors 384 and 380 is supplied (the current that through the base and emitter of transistor 384 and the collector and the emitter of the transistor 380 revolves) by the factor η to the k-th power smaller than the Reference current through transistors 424 and 426. The bias voltage can therefore change with temperature in such a way that that the circulating current does not change with these temperature changes while the setting of the

3210GB 2

Current IA, ds.s ratio of IB to IA as well as the ratio of resistors 428 and 430 the maximum circulating Current flowing in the collector-emitter circuit of transistor 380 and the base-emitter junction of the Transistor 384 is generated, and the maximum error on Output 400 adjusts based on this circulating current.

The preload along points 410 and 412 is thus equal to the desired preload. The voltage generated across these points is applied across the first impedance load, which includes the base-emitter junctions of transistors 432 and 438 and resistor 440. The base-emitter junction of transistor 438 is forward biased so that it is conductive. The bias across resistor 440 therefore creates a current through resistor 440 and transistor 438, which in turn creates a current through resistor 442 and diode-connected transistor 444. The current through the emitter of transistor 446 is set to equal the current through transistor 432 (IA), so by matching transistor 444 to transistor 446 and matching transistor 432 to transistor 438, any mismatch between the voltage drops across each of transistors 432 and 438 due to a lack of equality of currents flowing through the collectors of these transistors is offset by an equal mismatch or lack of equality in the voltage drops between transistors 444 and 446 due to a doubling of the current Mismatch. The current through resistor 442 results in the generation of the

ΪΙ I Ubö4

Biasing along a second impedance load across the resistor 442 and the base-emitter junctions of transistors 444 and 446. That’s the tension across resistor 442 and transistors 444 and 446 equal the required bias voltage, which is with the temperature can change without affecting the circulating current in transistors 380 and 384 «

By applying the appropriate bias to the base of transistor 384 and the interconnected emitters of transistors 380 and 382 is the one on the output 400 transmitted circulating fault current due to the circulating current, that in the base-emitter circuit of transistor 384 and the collector-emitter circuit of transistor 380 flows, independent of temperature, and the maximum acceptable level of circulating current error at output 400 is given by the Ratio of the resistance values of resistors 428 and 430, by the bias current IA generated by the transistors 424 and 426 of the generator 324 is conducted, and determined by the ratio of the current IB to the current IA.

Therefore, the current output signal of the rectifier represents 24 at output 400 represents the full-wave rectification of an input current at connection 14B. Output 400 is with connected to the logarithmic section 26.

The logarithmic section 26 (according to Pig. 4A and 4B) includes an operational amplifier stage 451 and logarithmic elements 452 a. The operational amplifier stage 451 has an input 454, which is connected to the output 400 of rectifier cell 322 of rectifier 24

3210SC2

connected is. The input 4-54 · forms the connection between the base electrodes of the transistors 4-56 and 4-58. The collector of transistor 4-56 and the emitter of transistor 4-58 are connected to system ground. The emitter of transistor 4-56 is connected to the collector of transistor 4-58, the emitter of which is connected to voltage source 304 and current sources 300. The emitter of transistor 4-58 is also connected to the base of transistor 4-60 and to the anode of a diode. The collector of transistor 4-60 is connected to current sources 300 and the cathode of diode 4-61. The emitter of the transistor 4-60 is connected to the collector of a transistor 4-62, the base of which is connected to the base of the transistor 4-58 and the emitter of which is connected to the via a resistor 4-64 (S ¹ Xg. 4-B) Collector of transistor 4-58 is connected. The collector of transistor 4-60 is connected to system ground via a capacitor 4-68 and to the base of a transistor 4-66. The collector of transistor 4-66 is connected to current sources 300. The emitter of the transistor 4-66 is connected to the base of a transistor 4-70, the collector of which is connected to the current sources 3 ° 0 and the emitter of which is connected to the output of the logging elements 4-52.

The logarithmic elements 4-52 are due to the connection of two transistors 4-78 and 4-80 connected as a diode formed in a feedback loop between the output and the input of the operational amplifier stage 4-51, The outputs and inputs are formed by the emitter of the transistor 4-70 and the input 4-54-. in the In operation, the rectified current signal at the input 4-54- always flows into the rectifier 24, so that the

Transistors 480 and 482 of log elements 452 are always biased in the forward direction. Due to the nature of the operational amplifier stage 451 and the logarithmic elements 452 the rectified signal is converted into a signal that is a function of the square of the input signal or, more precisely, a function by two times the logarithm of the input signal. Hence the output is at terminal 476 of the operational amplifier stage 451 is a representation of the Log of the square of the current input signal at current input terminal 14B.

The output at the emitter of transistor 470 of the operational amplifier stage 451 is connected to the input of a log filter 28 (Fig. 4B). Log filters for use in the log range are in the U.S. Patent ... (U.S. Patent Application 97,901 filed November 28, 1979). The filter 28 includes at least one transistor 490 connected as a diode. The output of the logarithmic section 26 is with the base and the Collector of transistor 490 connected while the The emitter of the transistor forms the output of the filter. The output of the filter is suitably through the Current sources 302 biased and across an external capacitor 492 is connected to the external resistor 494, which in turn is connected to system ground.

As shown in the above-mentioned US patent is described, acts, because the output of Logarithmier-portion 26, a logarithmic signal is _s, the filter 28 as a low pass filter and the output of the filter is essentially a DC signal. This

3210302

DC voltage signal is fed to the input of the buffer amplifier 30 supplied.

The amplifier 30 has a transistor 5OO, whose Base is connected to the output of the filter 28. The emitter of transistor 500 is connected to the base and the Collector of a transistor 502 connected as a diode connected, the emitter of which is connected to the base and collector of a transistor 504- connected as a diode is. The emitter of transistor 504- is connected to a connection point 5Ο6 connected to the current sources 302 connected is. The collector of transistor 500 is connected to the collector and base of a transistor 508, its emitter through a resistor 510 to the positive Supply voltage terminal 350 is connected. the The base and collector of transistor 508 are still there connected to the base of a transistor 512, whose Emitter through a resistor 51 ^ to the power sources 300 is connected. The collector of transistor 512 is with the base of a transistor 516 and the collector of a transistor 518 connected. The transistor 516 is with its collector connected to the positive supply voltage terminal 350, while its emitter is connected to the Current sources 302 and the base of a transistor 520 is connected. The collector of transistor 520 is connected to the Collector and base of a transistor 522 connected, the collector and base of which continue to be connected to the current sources 300 are connected and its emitter is connected to the positive Supply voltage terminal 350 is connected. The emitter of transistor 520 is connected to the base of transistor 518 connected, the emitter of which is connected to the connection point 5Ο6 connected is. The base of transistor 518 and the

OL ι υ yy

Emitters of transistor 520 together form the output 524 of the detector 12. The output terminal 524 is suitable Way biased by the current sources J02 and connected to the terminal 144 of the amplifier cell 20 of the control module of Fig. 3 connected.

The current sources 300 and 302 and the voltage source 304 supply the required bias currents and Bias voltages to rectifier 24, log section 26, log filter 28 and buffer amplifier 30. As can be seen with specific reference to Figures 4A and 4B, the current sources 300 four PNP transistors 600, 602, 604 and 606, all with their emitters with the positive supply voltage connection 350 are connected. The collector of the transistor 600 is connected to the interconnected emitters of transistors 380 and 382 of rectifier cell 322 of the rectifier 24 connected. The base of the transistor 600 is with the base electrodes of the transistors 602 and 604 connected. The collector of transistor 602 is with the collector of transistor 460 and the base of the transistor 466 of the logarithmizing section 26 is connected. The collector and the base electrode of the transistor 604 are connected to the current sources 302. Finally, the base of transistor 606 is with the base electrode and the collector of transistor 522 of amplifier 30, while the collector of transistor 606 is connected to the base of the transistor 460 of the logarithmizing section 26.

As can be seen from FIG. 4A, the current sources 302 close a transistor connected as a diode

321 CB02

620 a, whose collector and base connections the output to form the connection 622 '. Terminal 622 'is over an external resistor 624 'connected to system ground. The emitter of the transistor 620 connected as a diode is connected to the base and collector of a diode-connected transistor 622, the emitter of which is connected to connected to the collector of a transistor 624. The emitter of transistor 624 is connected to the negative supply voltage terminal 450 connected. The base and the collector of transistor 622 which are two diode voltage drops above the negative supply voltage connected to the base of a transistor 626 and the base of a transistor 628. The emitter of the transistor 626 is tied to the base and collector of transistor 624 (a diode voltage drop above the negative Supply voltage at connection 450). Likewise, the emitter of transistor 628 is with the collector and the base of transistor 624 connected. The collector and the base of the transistor 624 are in turn with connected to the emitters of transistors 630, 632, 634, 636, 638 and 640 as well as to the base of a transistor 642, whose emitter is connected to the negative supply voltage terminal 450. The common base connection of the transistors 626 and 628 are connected to the base electrodes of transistors 630, 632, 634, 636, 638 and 640. The collector of transistor 630 is connected to the emitter of transistor 644, the base of which is connected to the base of a transistor 616 is connected. The emitter of transistor 616 is with the collector of the transistor tied together. The collector of transistor 626 is connected to junction 338 of operational amplifier stage 320 while the collector of transistor 628 is connected to

4 I U V- V

the base and collector of transistor 414 of the bias generator 324 is connected. The collector of transistor 644 is connected to the emitter of transistor 346 and the base of transistor 356 of amplifier stage 320 tied together. The collector of transistor 646 is connected to the emitter of transistor 466 and the base of the transistor 470 of the logarithmic section 26 connected. The collector of transistor 634 is connected to the collector and the Base of transistor 604 and the current sources 300 connected. The collector of transistor 636 is connected to the The output of the filter 28 is connected, while the collector of the transistor 638 is connected to the connection point 506 of the buffer amplifier 30 is connected. The collector of transistor 640 is connected to the base of transistor 520 and the Emitter of transistor 516 of buffer amplifier 30 connected, while the collector of transistor 642 is connected to output terminal 524 of the detector.

The voltage source 304 includes three diode-connected transistors 700, 702 and 704. The collector and the base of the transistor 700 are three diode voltage drops above the system ground and are connected to the emitter of the transistor 458 and the base of the transistor 460 of the logarithmic section 26. The emitter of transistor 700 is connected to the collector and base of transistor 702 to provide a source whose potential is two diode drops above system ground. The collector and the base of the transistor 7®2 are connected to the emitter of the transistor 334 and the base of the transistor 342 of the operational amplifier stage 32O. Finally, the emitter of transistor 702 is connected as a diode across the circuit

Transistor 704 connected to ground.

In operation, the system is suitably biased so that the necessary bias currents from the Gain control module source 32 and power sources 300 and 302 of the detector. When a Input voltage signal is applied to the input terminal 14, it is converted into a current which the Terminals 14A and 14B is supplied. The current signal at terminals 14A and 14B is simultaneously fed to the gain control module 10 and the detector 12 supplied.

The detector receives the signal at the connection point, whereupon the signal is rectified in the rectifier 24 will. A negative signal at input 330 results in a positive signal at the output of the amplifier stage 320. This leads to a bias of the transistor 384- in the forward direction and for flowing a current from the output 400 of the rectifier cell 322 through the collector-emitter circuit of transistor 384 of the rectifier cell 322. Accordingly, a current flows from the input terminal 454 of the logarithmic section? 6. The transistors 380 and 382 of rectifier cell 3-2 remain reverse biased and therefore non-conductive. Positive current signals at input 330 lead to a negative output signal of amplifier stage 320. This biases transistor 380 in the forward direction and reverse biasing transistor 384. The transistor 380 therefore conducts a current that leads to a mirrored current through the collector-emitter circuit of the transistor 382 leads. The emitter currents of the transistors 380 and 382 are fed to the

negative supply voltage connection 450 derived. Therefore flows in, as in the case of negative input signals Current from input terminal 454 of log section 26 to rectifier section 322. In this way a full wave rectification achieved «. The one at the input port 454 of the logarithmic section 26 delivered Current signal is converted into a logarithmic signal and multiplied by a factor of 2, namely by the feedback path of diode-connected transistors 480 and 482. This results in an output signal the logarithmic section, which is a representation of the logarithm of the square of the instantaneous input current at port 14B. The signal at the output of the logarithmic section 26 is passed through the low-pass filter 28 and then passed through the amplifier 30 to the To provide control signal at connection 524. The connection is connected to terminal 144 so that the control signal becomes the logarithmic signal in the sp breath controlled can be added to the amplifier cell 20 of the module.

The input signals at ports 14A and 14B are still passed through module 10, in FIG which a gain is impressed on the current signal, which is a function of the control signal. For negative Input signals at terminal 14A result in a feedback via the logarithmic transistors 116 and 118 of the voltage-controlled amplifier cell 20. The voltage signal across primary and secondary logarithm transistors 116 and 118 is a function of logarithm of the input signal because the transistor is in the feedback circuit of this stage 18. The control signal

32106G2

at terminal 144 arithmetic is added to the logarithm signal before the algebraic sum of the two Signals in antilog transistors 132 and 134 turn into one Antilogarithmic signal is converted as a function of the antilogarithm of the sum of the two signals. For positive input signals at terminal 14A, there is a return via logarithmic transistors 122 and 124 of the voltage controlled amplifier cell 20. The The logarithm signal provided by the logarithm transistors 122 and 124 is again a function of the logarithm of the input signal because the transistor is also in the feedback loop of stage 18. That Control signal at terminal 144 is added to the logarithmic signal before the algebraic sum of the two signals in antilog transistors 138 and 140 in an antilog signal is converted which is a function of the antilogarithm of the sum of the two signals.

The use of stage 18 and in particular transistor 42 and current generator device 48 results in that the stage a curled before voltage current of the Terminal 14A derives without affecting the gain-bandwidth product of the stage.

Furthermore, the use of the capacitor 94 and the use of the resistor? 'O result in a wave in the transfer characteristic of the amplifier 18 to the in the feedback loops through the voltage controlled amplifier cell 20 to negate the 90 ° phase shifts caused. By connecting diode 82 to the Emitter of transistor 68 and by matching the impedance of resistor 76 to the combined impedance of the

α ι υ ο υ 4

SO-

Diode 82 and resistor 84 is the Rausclibeitrag of the source 32 is reduced. Finally, the insertion leads a capacitor 84 a zero in the transfer characteristic of the stage, whereby the pole is negated, introduced by the parasitic base-emitter capacitance of transistor 66.

Using the bias generator 22 results in a Bias between connection points 112 and 128 of the voltage controlled amplifier cell 20. The bias is determined by the input current from source 32 ' and creates a bias current through the cell, which is independent of the temperature.

The use of the secondary transistors 116, 124, 132 and 140 as well as resistors 114, 126, 130 and 142 reduce distortion due to parasitic base and Emitter resistances of log and antilog transistors 118, 122, 134 and 138 of cell 20.

The use of the rectifier cell 322 of the detector 12 and in particular the use of a maximum limit of one for the loop gain in both return paths around the amplifier stage 320 improves the operating behavior of the detector. The bias generator also delivers 324 takes the majority of the generator current from the base of transistor 384- "and the common Emitters of the transistors 30 continue while at the same time the desired bias voltage is supplied between them will.

It will be understood that the above-described

32106G2

improved compander system as either a compressor or can be used as an expander for the signal supplied to input terminals 14A and 14-B will. The system can be easily manufactured in the form of an integrated circuit, with reduced Manufacturing costs result. If the module 10 and the detector 12 are in the form of separate integrated circuits are produced, both have essentially the same power dissipation. In particular, the The output of the detector 12 is a function of the rms value of the input signal and the operating temperature. The reinforcement of the detector is a function of the control signal and temperature. The embodiment described of the compander system is such that changes in the rms value output signal with temperature to changes the gain of the voltage controlled amplifier module are adapted to the temperature in such a way that the compression or expansion factor is independent of the temperature as long as the module and the detector operated at the same temperature.

Blank page

Claims (23)

---: - -.- ■ - :: - ■ - 3210652 Patent Attorneys "-. * - .. ^: ' ^: .. ^: Dip.l. ^: -lbg. Cu rt gelding European patent representative Dipl.-Ing. GüntherKoch European Patent Attorneys Dipl.-Phys. Dr Tino Haibach Dipl.-Ing. Rainer Feldkamp D-8000 Munich 2 Kaufingerstraße 8 Telephone (0 89) 2 60 80 78 Telex 5 29 513 wakai d Date: March 23, 1982 Our reference: 17 406 Patent claims (1st / compander system with a gain control module for - ' changing the gain impressed on an input signal as a function of a control signal and with a detector for generating the control signal as a function of the input signal, characterized in that the gain control module (10) has the following parts: (1) a first operational amplifier stage with an input connection, which is connected to receive the input signal, and with an output connection, (2) first logarithmic converter devices that are arranged in each of two return paths which form the input terminal of the amplifier stage connect to the output terminal to produce a logarithmic signal as a function of logarithm generate a corresponding representation of two representations of the input signal, (3) means for adding the control signal to each of the logarithmic signals, (4) antilogarithmic converter devices that are coupled to each logarithmic converter means and an anti-logarithmic signal as a function of the antilogarithm function of The sum of the corresponding logarithmic signal and the control signal provide ,, and (5) first bias generator means for generating a bias current through the logarithmic converter devices of both Return paths and through the anti-logarithmic converter devices, where the bias current is essentially dependent on the temperature; that the detector (12) comprises the following parts: (1) Operational rectifier devices for generating a rectified signal which is essentially represents a rectified form of the input signal, the rectifying means an input terminal for receiving the input signal and an output terminal having which supplies the rectified signal, wherein the rectifier means (a) a second operational amplifier stage with an input connection connected to the input connection of the rectifier devices and an output port, (b) first stroralextende bodies that on address the output of the second operational amplifier stage and a transmission path between the input and output terminals of the rectifying devices to essentially a representation of the input signal between the input and output terminals to forward the rectifier devices, (c) second current-conducting devices which are applied to the output of the second operational amplifier stage respond and a second transmission path between the input and output ports of the second operational amplifier stage to essentially the other representation of the input signal between route the input and output terminals of the second operational amplifier stage, and (d) include signal generator means responsive to the input signal when it is essentially routed via the second transmission path to an inverted To supply the signal of the other representation of the input signal, (2) second bias generator means connected to the output of the second operational amplifier stage are coupled and the first and second conductive devices and the signal generator devices bias so that the tracking speed requirements for one predetermined value of the operating characteristics of the second operational amplifier stage is reduced will, (3) second logarithmic converter devices which are connected to the output of the operational rectifier devices and a second logarithmic signal as a function of the logarithm of the rectified signal, and (4-) one with the output of the second logarithmic Low-pass filter coupled to converter devices including means for supplying the control signal essentially as a puncture of the DC voltage value of the second logarithmic signal. 2. compander system according to claim 1, characterized ■ characterized in that the first operational amplifier stage means for reducing of the input bias current derived from the input signal without the gain-bandwidth product the level is affected. 3. Compander system according to claim 2, characterized characterized in that the means for reducing the input bias current are bipolar Transistor devices connected to the input terminal the first operational amplifier stage are arranged and the input terminal opposite the remaining part the operational amplifier stage supply, and second signal generator means for generating a Current through the bipolar transistor devices 32106S2 such that the magnitude of the bias current drawn by the remainder of the operational amplifier stage is decreased. 4 ·. Compander system according to one of the preceding claims, characterized in that each of the first logarithmic converter means and the antilogarithmic converter devices coupled therewith a logarithm-antilogarithm transmission path and that the gain control module further comprises signal modification means in each logarithm-antilogarithm path to modify the input signal and the antilogarithmic Signal corresponding to a correction signal such that distortions of the antilogarithmic Signal are reduced. 5 · Compander system according to claim 4, characterized characterized in that the first logarithmic converter devices and the antilogarithmic Converter means each of the logarithm -Antilogarithm transmission paths in each case Include transistors of the same conductivity type, and that the transistors of a path have a conductivity type opposite to that of the other path. 6. Compander system according to claim 5 »thereby characterized in that the signal modification means are one with each transistor each the first logarithmic converter devices and each of the antilogarithmic converter devices each log-antilog transfer path include coupled transistor to form a transistor pair and that the transistors each Pair of opposite conductivity type. 7. Compander system according to claim 6, characterized characterized in that all transistors of each conductivity type in terms of their Vbe / Ic transfer characteristics are paired. 8. Compander system according to claim 7 »thereby characterized in that the emitters of each pair of transistors are connected together and that the signal modification means means for generating a correction signal by each of the Enclose transistor pairs therethrough such that the parasitic base and emitter resistances of the transistor pair are corrected. 9. compander system according to claim 8, characterized characterized in that the means for generating the correction signal means for Finding the difference between each input signal and the corresponding antilogarithm signal include each path. 10. Compander system according to claim 9 _}, characterized in that the means for determining the difference with the collector resistance elements and devices coupled to each transistor of each of the signal modification devices for measuring the voltage difference between the collectors of the transistors of the signal modification devices include in each of the paths. 11. Compander system according to claim 10, characterized characterized in that the measuring means have means for cross-coupling the base of each Transistor of the signal modification devices in each logarithm-antilogarithm transmission path with the collector of the other transistor of the signal modification devices in the same logarithmic-antilogarithm path lock in. 12. Compander system according to claim 11, characterized characterized in that each resistor element is adjustable to accommodate any mismatch correct the parasitic base and emitter resistances of the transistor pair. 13 · Compander system according to claim 5 »thereby characterized in that the means for adding the control signal are coupling means for adding the control signal to the base of the transistor of the first logarithm converter devices of a logarithm-antilogarithm transmission path and to the base of the transistor of the antilogarithm converter means of the other log-to-antilog converter means. 14. Compander system according to one of the preceding claims, characterized in that the first bias generator means are reference means to provide a first voltage as a function of temperature and scalar devices to multiply the first voltage to provide a bias along the log converter means both return paths and along the antilogarithmic converter devices in such a way include generating the bias current. 15 · Compander system according to claim 14, characterized in that characterized in that the reference means the base-emitter interface of at least include a transistor and that the scalar devices are the ratio of two resistors lock in. 16. Compander system according to one of the preceding claims, characterized in that that the first and second conductive devices each have a maximum loop transmission have a gain of unity. 17. Compander system according to one of the preceding claims, characterized ,, that the first current-conducting devices of the operational rectifier devices include a transistor whose collector and emitter are turned on so that a current from the output terminal 3210562 of the operational rectifier devices to the input terminal of the operational rectifier devices is directed that the second current-conducting devices of the operational rectifier devices include a second transistor whose base-emitter junction is connected such that a current from the input terminal of the operational rectifying devices is passed to the output terminal of the second operational amplifier stage, and that the Signal generator devices of the operational rectifier devices include a third transistor, whose collector and emitter are switched on in such a way that the third transistor in a current flowing through the base-emitter junction of the second transistor carries a current from the output terminal the operational rectifier devices to the output terminal of the first operational amplifier stage directs. 18. Compander system according to claim 17, characterized by means for achieving a gain symmetry between the second and third transistors on the one hand and the first transistor on the other hand. 19 · Compander system according to claim 1, characterized in that the second bias generator devices of the operational rectifier means means for generating a circulating current through the first and second Include rectifying devices in such a way that that the current error occurring at the output terminal of the operational rectifier devices is generated as a function of the circulating current, is temperature-independent. 20. Compander system according to claim 19, characterized in that the devices for generating the circulating current, the means for selecting the maximum acceptable level of the Include current error and that this means to select the maximum level by the ratio are formed by two resistors. 21. Compander system according to one of the preceding claims, characterized in that that the second bias generator means of the operational rectifier means have a first Impedance load with a first resistive element, a second impedance load associated with the first and second power transmission means is coupled and includes second resistive elements that are connected to are connected to the first resistance element, and means for generating a voltage across the include first impedance load such that a current is generated in the first resistance element, that a current in the second resistance element as a function of the current in the first resistance element is generated and that a bias voltage is generated along the second impedance load, which is with the temperature changes in such a way that the preload flow in the first and second conductive Facilities is independent of temperature. 22. Compander system according to one of the preceding claims, characterized in that the second logarithmic signal is a function of the logarithm of the square of the current value of the input signal. 23. Compander system according to claim 22, characterized characterized in that the second logarithmic converter means comprise a third operational amplifier stage having an input terminal for receiving the rectified signal and an output terminal for providing the second logarithmic signal and two diode elements, which are connected between the input and output connections of the third operational amplifier stage. 2 pt. Compander system according to one of the preceding claims, characterized in that the low-pass filter includes at least one diode element which is connected between the input and the output of the filter.