DE3205840A1 - Measurement value conditioner - Google Patents

Abstract

A measurement value conditioner (2) for processing periodic digital samples of two measured alternating voltages of the same frequency shifted by the phase angle phi . The samples of the first alternating voltage are stored in a random access memory (8) with the aid of a selector (6) at addresses which are equal to the binary counts of a counter (3). In each case one multiplier (10, 14) digitally multiplies the samples of the two alternating voltages by particular stored values called up from the random access memory (8), an accumulator (4, 5) generating the addresses of the stored values called up by digitally integrating the output signal of the associated multiplier (10, 14) and subsequently adding it with the aid of an N-bit adder (15) to the currently valid binary count of the counter (3) so that the stored values called up are equal to the values of the first alternating voltage shifted by a certain phase angle ( pi /2, phi + pi /2) compared with the sampling instances. A subtraction element (16) forms the difference ( phi ) between these two phase angles. The measurement value conditioner (2) can be used in electricity meters. The second alternating voltage is then proportional to the consumed power. <IMAGE>

Description

Measured value conditioner

Messwert-Aufberei ter Field of application and purpose The invention relates on a measured value conditioner for further processing of periodic, digital, with the aid of a first clock signal generated sample values of two measured um the phase angle # of shifted alternating voltages of the same frequency. The phase angle ep has a value between - # / 2 and + 3 # / 2, for example.

The second alternating voltage u2 = U2.cos (wt + #) is e.g. one of the dem Consumption current i = I.cos generated by the first alternating voltage u1 = U1.cos wt (wt + cp) proportional alternating voltage.

Used in an electricity meter to determine the amount consumed Energy or power the second alternating voltage u2 with U1.cos ut, U1.cos (t + TT / 2) or U1.cos (wt + ep) is multiplied, the product obtained in this way is proportional the real power U1.I.cosqz, the reactive power U1.I.sin # or the apparent power U1.I, assuming that the second term in each of the following additions is eliminated with the help of an integrator.

The following applies: [U1.cos #t]. [U2.cos (wt + = (U1. U2 / 2) .cos # + (U1.U2 / 2) .cos (2 #t + #) = (U1.U2 / 2) .cos # = (q / 2) .U1.I.cos #. [U1.cos (#t + # / 2)]. [U2.cos (# t + #) = (U1.U2 / 2) cos (# / 2- #) + (U1.U2 / 2) .cos (2 # t + # + # / 2) = (U1.U2 / 2) sin # = (q / 2). U1.I .sin #. [U1.cos (#t + #)]. U2.cos (#t + #)] = (U1.U2 / 2) .cos 0 ° + (U1.U2 / 2) .cos (2 # t + 2 #) = (U1.U2 / 2) = (q / 2) .U1.I.

The constant q denotes the proportional constant u2 / i. The values of the first alternating voltage shifted by the phase angle n / 2 or w u1 are generated with the help of a measured value processor.

State of the art In DE-OS 25 50 282 a power and work measurement method with A / D converters, but the processing of the measured values is only analogous with Realized with the help of a conventional RC element.

OBJECT AND SOLUTION The invention is based on the object of known Measurement inaccuracies of measuring devices designed in analog technology, e.g. the Measure a reactive or an apparent energy consumption, through use of a measured value processor in digital technology and to minimize the measurement inaccuracies limit the analog to digital converters and previous circuits. The determination of the phase-shifted voltage values required for this must also be carried out at correctly performed with non-synchronous sampling of the AC voltage to be measured.

According to the invention, the stated object is achieved by the characteristics of claim 1 specified features solved.

The apparent energy, which has been determined indirectly until today, can as a result, the generation of the Phase shift is then lossless and caused by limited resolution Errors are arbitrarily small.

Description An embodiment of the invention is shown in the drawing and is described in more detail below.

The figures show: FIG. 1 a block diagram of a measured value processor for the digital determination of phase-shifted voltage values, FIG. 2 is a block diagram an accumulator, FIG. 3 is a block diagram of a subtraction element and FIG. 4 is a circuit diagram of an electronic selector.

The same reference numbers denote the same in all figures of the drawing Parts. In the drawing there are N-Bit bus connections with a small cross line, (N + M) -bit bus connections with two small dashes, K-bit bus connections with three small horizontal lines and M-Bit bus connections with four small horizontal lines marked.

Description of FIG. 1 A first clock input 1 of a measured value processor 2 feeds the clock inputs of a counter 3 and a first accumulator 4 in a single-pole manner and a second accumulator 5. A selector 6 is shown in Fig. 1 for simplicity sake shown as an electromechanical selector and has a first N-pole Switching arm 6a, a second N-pole switching arm 6b and a control part 6c.

In practice, however, an electronic voter is used, such as that shown in FIG. The selector 6 has 4 positions A, B, C and D. The positions of the first N-pole switching arm associated with these 4 positions 6a are with an index 1 and those of the second N-pole switching arm 6b with marked with an index 2.

A second clock input 7 of the measured value processor 2 is single-pole to a control input of the selector 6, and a control output this Selector 6 is also unipolar on a read / write input of a read / write memory 8 led. All remaining connections in Fig. 1 are bus connections, namely, unless otherwise specified, N-bit bus connections.

The first N-pole switching arm 6a connects the data input / output 6 of the read / write memory 8 in position A1 with a voltage input 9, a first input of a first multiplier 10 and a first output 11 of the Measured value conditioner 2, in position B1 with a second output 12 of the measured value conditioner 2, in position C1 with a third output 13 of the measured value conditioner 2 and a second input of the first multiplier 10 and in position D1 with one first input of a second multiplier 14. The second N-pole switching arm 6b switches on a first N-bit input of an N-bit adder 15 in position A2 the N-bit value 0, in position B2 to the N-bit output of a subtraction element 16, in position C2 to the N-bit output of the first accumulator 4 and to one N-bit minus input of subtraction element 16, and in position D2 to the N-bit Output of the second accumulator 5 and an N-bit plus input of the subtraction element 16. A current input 17 feeds a second input of the second multiplier 14, and the output of this second multiplier 14 using an (N + M) bit Bus connection an (N + M) -bit input of the second accumulator 5. The output of the first multiplier 10 is via an (N + M) -bit bus connection with a (N + M) -bit input of the first accumulator 4 connected. The N-bit output of the N-bit The adder 15 is fed to the N-bit address input of the read / write memory 8.

The counter 3 is a K-bit counter. Its K-bit output is above a K-bit bus connection at the K least significant inputs of a second N-bit input of adder 15.

Functional description of the circuit of Fig. 1 One of a first AC voltage u1 = U1.cos Wt on a Consumption electricity generated by the load is converted into a proportional second alternating voltage u2 = U2.cos (tot + q). The phase difference between the two alternating voltages u1 and u2 is accordingly cp.

Both AC voltages u1 and u2 are time-series at the same time sampled in the discrete-time sampling instants t. with the help of a common first clock signal CL1, which is also the first clock input 1 of the measured value conditioner 2 is supplied, where j = 0, 1, 2, ..., k-1. The first clock signal consists of square-wave Clock pulses of the period T. The 0 inequalities k.T <T <(k + 1) where, where T = 2rr / el) the common period of the two alternating voltages represents u1 and u2. k denotes the highest number of periods To that exist in a period T are included. k is an integer. The following applies: 2K 1 <k <2K The first Sampling instant t per period T is arbitrary and 0 changes relatively continuously to the phase zero value of the sampled AC voltages u1 and u2, if their period T is not exactly a multiple of the period T of the first clock signal 0 CL1.

The analog sampled values of the two alternating voltages u1 and U2 are with the help of an analog / digital converter each into digital samples consisting of N-bit converted. Those of the first alternating voltage u1 reach the time series Voltage input 9 and those of the second alternating voltage U2 also in time series the current input 17. A second clock signal CL2, this time of the period T / 4, is also rectangular 0 and feeds the second clock input 7. The first clock signal CL1 of the period T is derived synchronously from the second clock signal CL2 0 by its Frequency is divided by 4 with the help of e.g. two flip flops.

All circuits mentioned so far in the functional description of FIG are known per se. They are therefore not described in more detail and also not in shown in the drawing.

The counter 3 counts those appearing at the first clock input 1 in binary Clock pulses of the first clock signal CL1. The counter starts after 2 +1 clock pulses 3 again to count from zero, so that within the various periods T of two alternating voltages u1 and u2, the respective scans are the same continuous Own number. These consecutive numbers result after their multiplication with the period T of the first 0 clock signal CL1 the phase angle of the associated, during a period T of samples. The reference phase angle is included the phase angle of the first sample per period T. The consecutive, through the Counter 3 determined numbers serve the read / write memory 8 as an address and its address input via the N-bit adder 15 to the second N-pin Switching arm 6b in position A2 supplied in series after its K-bit up were supplemented with (N-K) bits with a value of zero. At the same time, the associated N-bit of the digital samples of the first AC voltage u1 as well Time series from the voltage input 9 via the first N-pole switching arm 6a in Position A1 the data input / output of the read / write memory 8. Since the control output of selector 6 set the read / write input of read / write memory 8 to "write" switches while the selector 6 is in position A, the digital Samples of the first alternating voltage u1 at their associated addresses in the read / write memory 8 saved. The control output switches for positions B, C and D of selector 6 of the selector 6 the read / write input of the read / write memory 8 to "read".

After the start is thus every time the selector 6 is in position A is, one of the digital samples is stored in the read / write memory 8. the Values read from the read / write memory 8 during the first periods T be when the Voter 6 is in one of the positions B, C or D, are partially meaningless, since the memory cells are at least partially are still empty. However, these reads receive a certain amount of time after the start all their meaning. Since the selector 6 from the second clock signal CL2 of the period To / 4 is controlled via the second clock input 7, the selector 6 runs through during the Period T successively and evenly the 0 positions A, B, C and D, followed by again - in the next period T - to start over with position A.

0 In position C of the selector 6 form the first multiplier 10, the first accumulator 4, the selector 6 and the read / write memory 8 one closed, digital first phase-locked loop. The same applies to position D of the selector 6 for the second multiplier 14, the second accumulator 5, the Selector 6 and the read / write memory 8, which in this case have a closed, result in digital second phase-locked loop.

Strictly speaking, it is not the phase differences in the two control loops two signals are controlled directly, but rather the cosine values of these phase differences are regulated to zero.

The two accumulators 4 and 5 work as digital integrators. Since in the steady state the actual value of a control loop is equal to the setpoint is, and this is zero in the present case, is in the steady state the actual value of the cosine of the phase difference is also zero, i.e. the phase difference same does / 2.

In the first control loop, the first multiplier 10 multiplies the digital value U1 .cos wt. Digital by the digital value U1. cos (wt + 8ç), so that as a function of the time at the output of the first multiplier 10, the digital (N + M) -bit output value appears.

In the second control loop, the second multiplier 14 multiplies the digital value U2.cos (wt. + Ç) digitally by the digital value U 1.cos (#tj + # + ##), so that as a function of time at the output of the second multiplier 14 the digital (N + M) -bit output value appears.

As already mentioned, it is in the steady state in both cases Aw = 1T / 2.

Since the two accumulators 4 and 5 work as digital integrators, if the last term of the respective sum is omitted due to the averaging, so that at the output of the two accumulators only the integral of the respective first Terms shows up.

Since in the steady state cos Qsp = cos # / 2 = 0 and the integral is a constant of zero, appears at the N-bit output of the first accumulator 4 the constant phase ## = TT / 2 and at the N-bit output of the second accumulator 5 the also constant phase # + cp = + 1T / 2. Then with the help of the N-bit adder 15 to the two constant digital phase values rr / 2 or 9 + n / 2 the digital value utj is added.

The output of counter 3 supplies this digital value wt. In the position C of the selector 6 thus becomes the digital output value wt. + # / 2 of the address input of the read / write memory 8 and the stored at this address digital sample U1.cos (wt. + # / 2) to the second input of the first multiplier 10 forwarded. In the same way, the selector is in position D 6 with the digital output value (Wtj + + TT / 2) of the N-bit adder 15 of the stored digital sample value U1.cos (tj + w + n # / 2) retrieved from the read / write memory 8 and fed to the first input of the second multiplier 14.

The subtraction element 16 forms the digital difference w between the output value (? + # / 2) of the second accumulator 5 and the output value # / 2 of the first accumulator 4. In position B of the selector 6, this digital value calls v the phase, after adding the digital value of wt. in the N-bit adder 15 and used as an address, the stored sample from the read / write memory 8 U1.cos (wt. + Cp) and forwards it to the second output 12 of the measured value processor 2 to.

The digital sample is also present at its first output 11 U1 .cos wt. And at its third output the digital sample value U1.cos (wt. + # / 2).

Description of FIG. 2 The two accumulators 4 and 5 are identical constructed and their common block diagram is shown in FIG.

They each consist of an (N + M) -bit adder 18 and an (N + M) -bit Memory 19.

A clock input 20 of the accumulator is unipolar on the clock input of the (N + M) -bit memory 19. All remaining connections of Fig. 2 are Bus connections, namely, if nothing else is stated, N-bit bus connections.

The (N + M) -bit input 21 of each accumulator 4 resp.

5 is at a first using an (N + M) -bit bus connection (N + M) -bit input of the (N + M) -bit adder 18 switched.

The N uppermost bits of the output of this (N + M) -bit adder 18 feed the N top bit inputs of the (N + M) -bit memory 19 and the M bottom bits of this output via an M-bit bus connection, the M lowest bit inputs of this (N + M) -bit memory 19. The top N bits of the output of the (N + M) -bit memory 19 are on the one hand on the top N bit inputs of a second (N + M) -bit input of the (N + M) -bit adder 18 and on the other hand feed the N-bit output 22 of the accumulator 4 or 5. The M lowest bits of the output of the (N + M) -bit memory 19, on the other hand, are only accessible to the lowest M bit inputs with the help of an M-bit bus connection of the second (N + M) -bit input of the (N + M) -bit adder 18 is fed back.

Dashed line in the blocks showing the (N + M) -bit adder 18 and represent the (N + M) -bit memory 19, symbolically separates the top N of the M lowest bits.

Functional description of the circuit according to FIG. 2 The (N + M) output bits one of the two multipliers 10 resp.

14 of Fig. 1 feed via the (N + M) -bit input 21 of the associated Accumulator the (N + M) -bit first input of the (N + M) -bit adder 18. To this (N + M) -bit input value, the (N + M) -bit adder 18 adds the (N + M) -bit content of the (N + M) -bit memory 19. The sum value obtained in this way is in turn again with the aid of the first clock signal CL1, e.g.

at the time of its positive edge, stored in the (N + M) -bit memory 19, so that in this the accumulated (N + M) -bit values of all so far one after the other from associated multiplier 10 or 14 supplied data are stored. With In other words, the input values present at the (N + M) -bit input 21 of the accumulator are integrated. The top N bits of the Form integration value the digital value of phase Qg (first accumulator 4) or (+ (second accumulator 5), where, as already mentioned, in the settled State of the control loops Aw = lot / 2.

The use of (N + M) -bit values in the first part of the accumulator 4 or 5 is used to increase the accuracy, which can be made as large as desired by choosing a high M value. After that, only the N uppermost bit of the (N + M) -bit arithmetic values of the accumulator 4 or 5 processed further and evaluated. These top N bits represent a binary number x. By use of the (N + M) -bit multiplier 10 or 14 of FIG. 1, the (N + M) -bit adder 18 and the (N + M) -bit memory 19 is the binary number x of the M binary digits, i.e. H. a binary number y, rounded and thus falsified (N + M) -bit calculation value of the accumulator 4 or 5.

In other words, after the N uppermost bit, the (N + bit arithmetic value a comma is set and all digits after the comma are used for rounding off omitted. However, this falsification is, and that is one of the great advantages this circuit, at least partially corrected from time to time, since the error is accumulated in the M lowest digits of the (N + M) -bit memory 19 and, as soon as this accumulation exceeds the value 2M, as overflowing the M lowest Bit positions in the (N + M) -bit adder 18 are added to the lowest bit of the N uppermost bits. The N-bit binary number is not used in the second part of the accumulator 4 or 5 x, but the corrected average N-bit binary number (x + y / 2M) The remaining residual error e is then: - 1 / 2M + c 1 <+ 1 / 2M + 1 description of FIG. 3 The block diagram of the subtraction element 16 is shown in FIG. The subtraction element 16 consists of a proper common subtractor 23, an N-bit period adder 24, a first N-bit AND gate 25, a second N-bit AND gate 26, an N-bit OR gate 27 and an inverter 28.

A single-pole top bit output line of the actual subtraction element 23 is directly to a first input of the second N-bit AND gate 26 as well as via the inverter 28 is fed to a first input of the first N-bit AND gate 25. Both N-bit AND gates 25 and 26 each consist of N identical AND gates, all of them have two entrances. All first inputs of these N AND gates of an N-bit AND gate 25 and 26 are unipolar with each other and with the first input of the respective N-bit AND gates 25 and 26, respectively. All of the remaining connections of Fig. 2 are N-bit Bus connections.

An N-bit minus input 29 of the subtracter 16 is on a first N-bit input and an N-bit plus input 30 to a second N-bit input of the actual subtraction element 23 switched. The (N-2) lowest bits of the N-bit minus output 29, supplemented at the bottom by two bits with a value of zero, feed a first N-bit input of the period adder 24, while the N-bit output of the actual subtraction element 23 with a second N-bit input of the period adder 24, and is connected to a second input of the first N-bit AND gate 25. The N-bit output of the period adder 24 is in turn connected to the second input of the second N-bit AND gate 26.

The output of the first N-bit AND gate 25 feeds a first N-bit Input and the output of the second N-bit AND gate 26 have a second N-bit input of the N-bit OR gate 27. This N-bit OR gate 27 consists of N independent OR gates that all have two inputs. The output of the N-bit OR gate 27 is connected directly to the output 31 of the subtraction element 16.

Functional description of the circuit according to FIG. 3 The same applies as before mentioned: -IT / 2 <g <+ 3LT / 2.

The actual subtractor 23 subtracts the minus input at the N-bit 29 pending digital phases value lT / 2 of the pending at the N-bit plus input 30 digital phases worth + + rr / 2). If the result is positive, the subtraction is the top output bit of the actual subtraction element 23 is a logical "O", all AND gates of the first N-bit AND gate 25 are enabled and switch the N-bit output of the actual subtraction element 23 via the N-bit OR gate 27 to the output 31 of the subtraction element 16. At the same time, the second N-bit AND gate 26 blocked by the logical "O" value of the top bit. Is against If the result 9 is negative, its uppermost bit value is equal to logic "1" and returns this time the second N-bit AND gate 26 is free, while the first N-bit AND gate is free 25 blocks.

Since the first N-bit input of the period adder 24 is four times The digital value of the phase value 1/2 is present, i.e.

4 x lT / 2 = 2tT, all negative phase values ç are in the positive direction shifted by a period T so that at the output 31 of the subtraction element 16 equivalent positive phase angles appear. The phase values g 'at the output 31 are therefore all positive and 0 <('<21a, where a phase value (p' corresponds to the corresponding Phase value cp is equivalent.

Description of Fig. 4 In Fig. 4 is an electronic selector 6 for the case N = 4. "Low power Schottky" components are advantageously used of the 74 LS series ... e.g. from Texas Instruments, Dallas, Texas, USA. They are all to be fed with a supply voltage + VCC = + 5V related to ground: + VCC is on pin 16 and the ground on pin 8 for 16-pin "Dual in line" - Components, or + Vcc is on pin 14 and the ground on pin 7 for 14-pin "dual in line" components.

The inputs / outputs of the selector 6 are Am, n, Bm, n, Cm, n, Dm, n, and E. with m = 1 or 2, here with n = 1, 2, 3 or 4. The m, n first index marks m the first or the second N-pole switching arm 6a or 6b, and the second index n is the current bit number within the N-bit connections. The inputs / outputs E n denote the switch arm connections, which in FIG. 1 m, n with the read / write memory 8 are to be connected.

The control part 6c consists of a 4-bit counter 33, e.g. of the 74LS type 161 and a "Quad-Nor" gate 34, e.g. of the type 74LS02. The first N-pole switch arm 6a consists, for example, of a first demultiplexer 35 and a second in the case of N = 4 Demultiplexer 36, both e.g. of the 74LS155 type, a "Quad-And" gate 37, e.g. Type 74LS08, a first "Hex-Inverter" 38, a second "Hex-Inverter" 39 and a third "Hex-Inverter" 40, all three e.g. of the 74LS04 type. The second N-pin For the case N = 4, switching arm 6b consists, for example, of a first multiplexer 41 and a second multiplexer 42, both e.g.

of type 74LS153. All "And" and "Nor" gates have two inputs.

The clock input of the selector 6 is connected to the clock input of the 4-bit counter 33 connected. Its “Load” input L, “Count enable P” input P, “Count enable T "input T and" Clear "input C are all connected to logic" 1. "This logic The "1" value can e.g.

of type 74LS04, whose input is connected to ground.

The QA or the Og output of the 4-bit counter 33 feeds all SA inputs all multiplexers and demultiplexers and a first input of a first "Nor" gate 43 of the "Quad Nor gate 34" or all SB inputs of all multiplexers and demultiplexers and the second input of the first "Nor" gate 43. The SA input corresponds to in the two demultiplexers 36 and 37 dem "Select A" - and at the two multiplexers 42 and 43 to the "Address A" input. The SB input corresponds to the "Select B" input of the demultiplexers 36 and 37 and the "Adress B" input of the Multiplexers 42 and 43.

The output of the first "Nor" gate 43 is on a control output of the selector 6 and to the respective first input of all "And" gates of the "Quad And "gates 37 are switched. The two" strobe "inputs 1G and 2G of all demultiplexers 35 and 36 and all multiplexers 41 and 42 are connected to ground.

Connected to each other, in each case in the specified order, are: the outputs 1Y1, 1Y2, 1Y3, 2Y1, 2Y2 and 2Y3 of the first demultiplexer 35 via one inverter each of the first "hex inverter" 38, 1Y1, 1Y2, 1Y3, 2Y1, 2Y2 and 2Y3 of the second demultiplexer 36 each via an inverter of the second "hex inverter" 39 with the outputs B1> 1, C1,1, C1 1,2 1 2 '1,2' B1,3 'C1> 3, B1> 3> 4 C1 and D D1,2, C1,2, D1,2, D1,3, C1,3, D1,3, D1,4, C1,4 and D1,4 of the selector 6.

- The inputs A, 1, A1,2, A1,3 and A1,4 of the selector 6 - The inputs A1,1, A1,2, A1,3 and A1,4 of the selector 6 with the respective second input of the associated "And" gate of the "Quad-And" gate 37.

- The output of the "And" gate associated with input A1, 1 of selector 6 to the output E1,1 of the selector 6 and the input 1C of the first demultiplexer 35.

- The output of the "And" gate associated with input A1,2 of selector 6 with the output E1,2 of the selector 6 and via a first inverter of the third "hex inverter" 40 to the input 2C of the first demultiplexer 35.

The output of the "And" gate associated with input A1,3 of selector 6 with the output E13 of the selector 6 and the input 1C of the second demultiplexer 36.

The output of the "And" gate associated with input A1,4 of selector 6 with the output E1 4 of the selector 6 and via a second inverter of the third "hex inverter" 40 to the input 2C of the second demultiplexer 36.

- The inputs 1C0, 1C1, 1C2, 1C3, 2C0, 2C1, 2C2 and 2C3 of the first Multiplexer 41 and the inputs 1C0, 1C1, 1C2, 1C3, 2C0, 2C1, 2C2 and 2C3 of the second multiplexer 42 with the inputs A2,1, B2,1 C2,1, D2,1, A2,2, B2,2, C2,2, D2,2, A2,3, B2,3, C2,3, D2,3, A2,4, B2,4, C2,4 and D2,4 of the selector 6.

The outputs 1Y and 2Y of the first multiplexer 41 and the outputs 1Y and 2Y of the second multiplexer 42 with the outputs E2> 1> E2,1, E2,2, E2> 3 and E2 4 of voter 6.

Functional description of FIG. 4 The 4-bit counter 33 counts the binary Clock pulses of the first clock signal CL1 of the period T. However, only those two 0 lowest bit outputs QA and QB are taken into account, so that one after the other the binary count values 00, 01, 10, 11 and then again 00, 01 etc. can be evaluated. These four binary counts correspond to the four positions A, B, C and D of the selector 6 and are in the demultiplexers 35 and 36 and in the multiplexers 41 and 42 decoded. You then release "And" gates there in a known manner, like this that the inputs of these circuits at the right moment to the outputs of these the same circuits are switched through in an N-bit manner. The only exception are the inputs AlA1,1, A1,2, A1,3 and A1,4 of the selector 6. These inputs are used at binary count 00, which is decoded by the first "Nor" gate 43, using of "Quad-And" gate 37 to the associated outputs E1> 1, E1 E1,3 and E1,4 des Selector 6 switched through. This exception is due to the fact that in Position A sends the signals in the opposite direction through the first N-pole Switching arm 6a flow as in positions B, C and D. The output signal of the first "Nor" gate 43 is logical "1" for position A of selector 6 and for all remaining positions are the same as logical "0". This output of the "Nor" gate 43 is used to switch the read / write memory 8 of FIG. 1 from "write" (Position A of the selector 6) to "read" (positions B, C and D of the selector 6).

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Claims (6)

PATENT CLAIMS Measured value conditioner for further processing of periodic, digital sampling values generated with the aid of a first clock signal (CL1) two measured alternating voltages of the same, shifted by the phase angle 9 Frequency, characterized in that the measured value conditioner occurs one after the other first the digital samples of a first alternating voltage (u1) of the two alternating voltages (u1, u2) stored in a read / write memory (8) under addresses that are the same are the binary counts of a counter (3), the counter (3) being the clock pulses of the first clock signal (CL1) counts in binary, and that then a multiplier (10 or 14) the digital samples of any of the two alternating voltages (ul, u2) with specific memory values called up from the read / write memory (8) digitally multiplied, with an accumulator (4 or 5) the addresses of the retrieved Generates memory values by taking the output signal of the multiplier (10 resp. 14) digitally integrated and then to the currently applicable binary count of the Counter (3) added so that the recalled memory values are equal to the values which around a certain constant phase angle does / 2 or (w + rr / 2) compared to the Sampling moments (t.) Shifted first alternating voltage (u1). 2. Measured value conditioner according to claim 1, characterized in that that after the storage of the digital samples of the first alternating voltage (u1) one after the other - first a first multiplier (10) takes the digital samples the first alternating voltage (u1) with certain from the read / write memory (8) retrieved memory values are multiplied digitally, the addresses of which are a first accumulator (4) supplies, and then a second multiplier (14), the digital samples the second alternating voltage (u2) with certain others from the read / write memory (8) the retrieved memory values are digitally multiplied, the addresses of which are a second Accumulator (5) generated so that the successively generated constant phase angle alternately by rr / 2 and (cp + Tr / 2) compared to the sampling instants (tj) are shifted. 3. measured value conditioner according to claim 2, characterized in that In addition, a subtraction element (16) shows the difference between an output signal of the second accumulator (5) and an output signal of the first accumulator (4) forms as an address for certain additional ones from the read / write memory (8) memory values to be retrieved shifted in time, which are equal to the values of the um the constant phase angle (p with respect to the sampling moments (t.) shifted first alternating voltage (u1). 4. measured value conditioner according to claim 3, characterized in that the successive storage of the digital samples of the first alternating voltage (u1) and retrieval of the memory values that are equal to the Values of the constant phase angles tor / 2, (9 + TT / 2) and g compared to the Sampling moments (t.) Shifted first AC voltage with the help of a selector (6) takes place, which is controlled by a second clock signal (CL2), the frequency of which is four times the frequency of the first clock signal, and that the selector (6) during of a period (T) of the first clock signal successively 0 and four positions of the same length (A, B, C, D). 5. measured value conditioner according to one of claims 1 to 4, characterized characterized in that one (N + M) -bit adder (18) and per accumulator (4, 5) an (N + M) -bit memory (19) is available for further processing in the accumulator (4, 5) only uses the top N bits of this (N + M) -bit memory (19) and that an N-bit adder (15) the binary count values of the counter (3) to the content of the top N Bits of the (N + M) -bit memory (19) added. 6. measured value conditioner according to one of claims 1 to 5, characterized marked that converting a negative Phase value q) into an equivalent positive value is done with the help of a period adder (24), a first N-bit AND gate (25), a second N-bit AND gate (26), an N-bit OR gate (27) and an inverter (28).