DE3205458C2 - Method for producing an integrated semiconductor circuit arrangement with an I → 2 → L circuit arrangement and one of the plurality of high-blocking transistors - Google Patents

Abstract

The invention relates to a method for producing an integrated circuit which consists of an I ↑ 2L circuit part and high-blocking transistors. According to the invention, only a uniformly thick epitaxial layer is applied to a base body, which is partially removed again in the areas where the I ↑ 2L circuit parts are arranged. In the surface areas provided for the high blocking transistors, however, the epitaxial layer remains in its original thickness. In this way, the electrical properties of the high-blocking transistors and the I ↑ 2L circuit parts can be optimally adjusted with just one epitaxial layer.

Description

characterized in that between the process steps b) and c) over the entire area Oberflächer.-zune (5) generated in the epitaxial layer (4) which has an opposite conductivity type compared to the epitaxial layer (4) and Contains impurities with a doping corresponding to the base zone of the high blocking transistors.

2. The method according to claim 1, characterized in that the injector zone (s) (10) and the base zone (s) (11) of the I ² L circuit (s) simultaneously with one between the base zone (5a) and emitter zone (12) lying, required for the high-blocking transistors, heavily doped base conductive zone (9) can be generated by diffusion or implantation.

3. The method according to claim 1 or 2, characterized in that the epitaxial layer (4) is 14 μm thick, that the thickness of the surface zone (5) is 3-4 μm, and that of the epitaxial layer (4) not for the high-blocking transistors provided areas a 7 μm thick partial layer (4c) is removed.

The invention relates to a method according to the preamble of claim 1, as disclosed in DD-PS 1 47 890 is known.

When producing I ² L shades, there is often a desire to produce npn transistors with a high reverse voltage in ^{addition to the I 2 L circuit parts.} The collector-emitter reverse voltage should be greater than 60 volts, for example. To achieve high blocking voltages in transistors, thick, lightly doped epitaxial layers are required for the collector area, but these are not very suitable ^{for the I 2 L circuit parts.} Thick, lightly doped epitaxial layers, into which the I ² L inverters are introduced, result in a low and large upward current gain in the vertical transistors of the I ^{2 L circuit}

Switching times. For the vertical transistors of the PL circuit, high current gain values are generally required in step-up operation, which results in a high sheet resistance of the active base zone. This leads to a deterioration in the reverse voltage of the npn transistors if these are produced with the same technological work steps as the I ² L circuit parts. An improved manufacturing method with which both 1 ² L circuit parts and high-blocking npn transistors are manufactured therefore requires different thicknesses of the epitaxial layers for the I ² L regions and the regions of the high-voltage-resistant transistors. A suitable process must be used to produce I ² L vertical transistors which have a high current gain, while the high-voltage-resistant npn transistors should have a lower current gain.

From DD-PS 1 47 890 a process is known in which an epitaxial layer is applied to the flat Si substrate, within which an I ² L stage and a low-resistance output stage are arranged, the epitaxial layer in the areas of the I ² L-stages has a thickness that is preferably 0.4 ... 0.8 μm less than in the area of the output stages.

From DE-OS 28 35 632 a further method is known in which on a base body to the for epitaxial layers are applied selectively in the areas provided for high-voltage-resistant transistors. A second epitaxial layer is then applied to the entire surface side of the base body. The PL circuit parts are then placed in the thinner epitaxial layer brought in. However, this known method has the disadvantage that when applying the second epitaxial layer from the highly doped buried zones in the base body diffuse out and into the selectively applied areas of the first epitaxial layer. Through this the blocking behavior of the high-voltage-resistant npn transistors deteriorates significantly.

DE-OS 24 55 347 discloses a method for producing a monolithically integrated solid-state circuit with at least one bipolar PL circuit part and at least one bipolar analog circuit part known. In this process, an η-conductive epitaxial layer is applied to a p-conductive base body A certain thickness is applied. In the further course of the process, this is applied epitaxially Layer removed to different extents by an etching process in the area of the PL circuit parts stronger than in the area of analog circuit parts. In the p-doped base body, before Application of the epitaxial layer introduced buried zones.

For the further development of the transistor configurations, both in the I ² L and in the analog circuit part, further known masking, doping and etching processes are used.

From “IEEE Trans, on Electr. Devices ", Volume ED-25, No. 3, March 1978, pages 351-357, is another method known, in which initially only the buried zones are introduced into the base body, which are for the high blocking transistors are provided. A first epitaxial layer is then placed on the base body applied, in which further buried on the surface areas provided for the PL circuit parts Zones are introduced. A second epitaxial layer is then placed on the first epitaxial layer applied, which, however, in turn by outdiffusion

processes from the second buried zones is doped in an undesirable manner. Even with this procedure therefore, npn transistors are obtained whose blocking behavior is not optimal.

The invention is thus based on the object of ^{specifying a method for producing an integrated semiconductor circuit arrangement from an I 2} L circuit part and from one or more bipolar transistors, which enables particularly high blocking voltages of these transistors and simplifies the production process.

In a method of the type mentioned at the outset, this object is achieved according to the invention by the characterizing features Features of claim 1 solved.

The inventive method has the significant advantage that the base-collector junction of the High-voltage transistors is flat, so that these transistors have particularly high reverse voltages.

The invention will be explained in more detail using an exemplary embodiment. They show 1 to 4 different manufacturing stages of the semiconductor arrangement.

1 shows a lightly doped, p-conducting semiconductor base body 1, which ^{is intended to accommodate an integrated circuit made up of I 2} L circuit parts and high-blocking transistors. For the sake of simplicity, only one transistor and one PL circuit unit are shown in the figures. The surface of the semiconductor body is covered in the usual planar technology with an insulating layer 3, which consists for example of silicon dioxide, which is provided with diffusion windows for the diffusion of the highly doped η + -conducting buried zones 2a and 2b. After the buried zones 2a and 2b, which have an impurity concentration on the surface of, for example, 10 ²⁰ atoms / cm ³ , the diffusion mask 3 is removed again from the semiconductor surface.

Thereafter, according to FIG. 2, a uniformly thick monocrystalline epitaxial layer 4 covering the entire surface is applied to the base body, which is η-conductive, has an impurity concentration of approx. 2 - 10 ¹⁵ atoms / cm ³ and, in a preferred embodiment, a layer thickness of approx. 14 μm Has. Thereafter, a p-conductive surface zone 5 is diffused over the whole area into this epitaxial layer 4, the concentration of impurities of which corresponds to that of the base zone of the high-blocking transistors. The depth of penetration of the surface zone 5 is approx. 3—4 μίτΐ in the final stage. Since during the production of the epitaxial layer 4 there is a slight expansion of the buried zones into the epitaxial layer, the distance between the buried Znne 2a and the base zone layer 5 is approximately 8 μm. With this order of magnitude of the active collector layer of the highly blocking transistors, in connection with the doping of zones 4 and 5, transistor blocking voltages of more than 60 volts are achieved.

The surface areas of the semiconductor circuit arrangement according to FIG. 2, which are provided for the high blocking transistors, are covered with an etching mask so that the semiconductor circuit arrangement can be removed in the remaining surface area by etching. In this etching process, according to FIG. 3 mesa-shaped island areas made up of a collector zone 4a and a base zone 5a for the high-blocking transistors. The edges of these mesa-shaped island areas are preferably bevelled if the base material is a 100 material and isotropic etching is carried out in a known manner. At the surface areas provided for the I ² L circuit, the epitaxial layer 4 is removed to such an extent that the surface zone 5 diffused, for example, with boron, is completely removed from these surface areas. In the case of an approximately 14 .mu.m thick epitaxial layer 4, the thickness of the removed layer 4c is, for example, 7 .mu.m. Taking into account the out-diffusion of the buried zone 2b into the epitaxial layer,

ίο an epitaxial layer 46 with a thickness of approx. 5 μm remains for the production of the I ^{2 L circuit parts.}

Then, with the help of the usual planar technology, silicon dioxide or silicon nitride masks are used to diffuse into the thinner part of the epitaxial layer 4b separation diffusion zones 6 which extend to the semiconductor base body 1 and are p ⁺ -doped. In a further masking and diffusion process, the n ⁺ -conducting buried zones 2a and 2b are provided with η + -conducting connection zones 7 and 8, respectively. The n + zone 7 forms, in a known manner, an n ⁺ ring around the I ² L inverter, while the n + .- Lriende zone 8 represents the collector connection zone for the high-feeding transistor. This η + -conducting zone 8 can also be designed in the shape of a ring, so that the active KoI-Iektorzone 4a is completely enclosed. This results in a very low switch-on resistance.

^{Finally, according to FIG. 4, the ρ r} -conducting base zone 11 for the 1 ² L inverters and the p + -conducting injector zone 10 is introduced into the thinner part 46 of the epitaxial layer again with the aid of the known diffusion and masking technique or a known implantation technique. Simultaneously with the production of this p + -conducting zone, a so-called base zone 9 can also be introduced into the base zone 5a for the high-blocking transistor, the higher doping of which enables better contacting of the base zone of the transistor and which also prevents short-circuit channels arising from charge carrier inversion on the surface. Thereafter, in a final diffusion or implantation process, the n + -conducting collector zones 13 and 14 for the vertical ^{transistors of the I 2} L circuit part are produced simultaneously with the emitter zone 12 for the high-blocking transistor. The high-blocking transistor is finally provided with an emitter contact 22, a base contact 21 and a collector contact 23 on the n + -conducting zone 8. For the I ² L circuit part, the contacts 16 on the n + -conducting ring 7 are used as the emitter connection, the contact 19 as the base connection, the contact 20 as the injector connection to zone 10 and the contacts 17 and 18 as collector connections to the zones 13 and 14 intended. The interconnects connecting the components run according to the circuitry lines in a manner not shown over an insulating layer 15 located on the semiconductor surface, which has arisen in the course of the various diffusion and masking processes. In the case of a semiconductor arrangement made of silicon, this insulating layer preferably consists of silicon dioxide or SiIi-

b0 zium nitride.

The method according to the invention has the advantage that only a single epitaxial layer is produced must and that different by a diffusion over the entire area without a mask and a single additional etching process thick epitaxial layer areas for the high blocking transistors on the one hand and for the I-L circuit parts on the other hand, and different power con-

reinforcement values can be set. Another advantage can be seen in the fact that the collector-base pn junction of the high-voltage-resistant transistors is flat, which enables particularly high blocking voltages. This flat pn junction comes about as a result of the diffusion over the entire surface of the surface zone 5, for example by way of boron doping, according to FIG. 2. Since in the method according to the invention the thickness of the epitaxial layer in the area of the IL-Schalitingstcile can be set so that it ^{corresponds to the layer thickness in the previously customary I 2} L technology, the tried and tested standard I-'L processes can also be applied to the Method according to the invention are transferred without modification.

For this purpose 2 sheets of drawings

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Claims (1)

Patent claims: 1. A method for producing a semiconductor integrated circuit arrangement having a ^ circuit arrangement and one or more bipolar high blocking transistors in which a) zones (2a, 2b) buried in a semiconductor base body (1) are introduced, b) the semiconductor base body (1) is covered with an epitaxial layer (4) which is applied in a uniform thickness to the entire surface side of the semiconductor base body (1) containing the buried zones (2a, 2b), c) the epitaxial layer (4) with the exception of the one provided for the high blocking transistors Areas removed to a residual thickness suitable for the ^ circuit arrangement will, d) in the 50 resulting thinner part {4b) of the epitaxial layer (4) the semiconductor zones (10, 11, 13, 14) necessary for the PL circuit arrangement and in the thicker part (4a) of the epitaxial layer (4) for the high blocking properties Transistors required zones (9, 12) are introduced,