DE3169024D1 - Exclusive or circuit and its application to a parity-checking circuit - Google Patents

Exclusive or circuit and its application to a parity-checking circuit

Info

Publication number
DE3169024D1
DE3169024D1 DE8181430020T DE3169024T DE3169024D1 DE 3169024 D1 DE3169024 D1 DE 3169024D1 DE 8181430020 T DE8181430020 T DE 8181430020T DE 3169024 T DE3169024 T DE 3169024T DE 3169024 D1 DE3169024 D1 DE 3169024D1
Authority
DE
Germany
Prior art keywords
circuit
parity
exclusive
application
checking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181430020T
Other languages
English (en)
Inventor
Herve Beranger
Armand Brunin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compagnie IBM France SAS
International Business Machines Corp
Original Assignee
Compagnie IBM France SAS
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compagnie IBM France SAS, International Business Machines Corp filed Critical Compagnie IBM France SAS
Application granted granted Critical
Publication of DE3169024D1 publication Critical patent/DE3169024D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/212—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using bipolar transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE8181430020T 1981-06-25 1981-06-25 Exclusive or circuit and its application to a parity-checking circuit Expired DE3169024D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP81430020A EP0068059B1 (de) 1981-06-25 1981-06-25 Exklusiv-Oder-Schaltung und ihre Anwendung in einer Paritätenauswertungsschaltung

Publications (1)

Publication Number Publication Date
DE3169024D1 true DE3169024D1 (en) 1985-03-28

Family

ID=8188592

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181430020T Expired DE3169024D1 (en) 1981-06-25 1981-06-25 Exclusive or circuit and its application to a parity-checking circuit

Country Status (4)

Country Link
US (1) US4430737A (de)
EP (1) EP0068059B1 (de)
JP (1) JPS583426A (de)
DE (1) DE3169024D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4749887A (en) * 1987-06-22 1988-06-07 Ncr Corporation 3-input Exclusive-OR gate circuit
US4888499A (en) * 1988-10-19 1989-12-19 Ncr Corporation Three input exclusive OR-NOR gate circuit
DE69111251T2 (de) * 1990-12-21 1995-12-21 Minnesota Mining & Mfg Zweistreifen-xor-strichcode und optischer leser.
US6760880B1 (en) 1998-09-10 2004-07-06 Ceva D.S.P. Ltd. Scalar product and parity check
US6493847B1 (en) * 1999-06-15 2002-12-10 Applied Micro Circuits Corporation Sonet B2 parity byte calculation method and apparatus
KR100604873B1 (ko) 2004-06-24 2006-07-31 삼성전자주식회사 레지스터 비트값 오류를 인식하여 리프레쉬하는 비트리프레쉬 회로, 이를 구비한 집적회로 장치 및 그 방법
TWI511116B (zh) 2006-10-17 2015-12-01 Semiconductor Energy Lab 脈衝輸出電路、移位暫存器及顯示裝置
US8239745B2 (en) * 2009-06-02 2012-08-07 Freescale Semiconductor, Inc. Parity data encoder for serial communication
US9171842B2 (en) 2012-07-30 2015-10-27 Semiconductor Energy Laboratory Co., Ltd. Sequential circuit and semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5149B2 (de) * 1972-09-05 1976-01-05
FR2296969A1 (fr) * 1974-12-31 1976-07-30 Ibm France Nouvelle organisation logique pour effectuer le test de parite d'un octet binaire et dispositif en resultant
US4069428A (en) * 1976-09-02 1978-01-17 International Business Machines Corporation Transistor-transistor-logic circuit

Also Published As

Publication number Publication date
US4430737A (en) 1984-02-07
EP0068059A1 (de) 1983-01-05
EP0068059B1 (de) 1985-02-20
JPS583426A (ja) 1983-01-10
JPH0129329B2 (de) 1989-06-09

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee