DE3149926A1 - Programmable comparison circuit - Google Patents

Abstract

A system for identifying selected combinations of digital signals from a group of N combinations of such digital signals is described. The system contains an addressable memory with N 1-bit word storage spaces. Each storage space has an address in accordance with one of the N combinations of digital signals and stores these 1-word storage space bits of a first value only in storage spaces which are addressable by corresponding combinations of the selected combinations of the digital words. Bits of the other value are stored in remaining word storage locations of the memory. If the memory is addressed by any of the selected combinations of digital signals which should be identified, it supplies an output signal which indicates this identification.

Description

Programmable comparison circuit

The invention relates to a comparison system and relates in particular on a programmable comparison system to identify any preselected Combination of a group of N digital signal combinations.

With different systems, one sometimes has to have a selected one Identify a word from a group of digitized words. For example must certain commands in a data processing system during the execution of certain commands Functions, such as diagnoses, can be identified in the system. In this example commands given must be recognized to stop the processor, sc that the States of various registers and other logical elements for investigation purposes can be queried.

In known techniques for performing such signal identification (comparative) functions used on a combination of Exclusive NOR gate circuits (XNOR) and AND gates. As an example of such prior art, consider assumed that certain of the eight possible combinations of digital signals, which result for a three-bit input word must be identified. These three Bits of such an input word representing signals become respective first input connections fed by three XNOR gates. A three-bit reference word (whose bit signals are identical with the signals of the input word to be identified) becomes the other Signal input connections of the XNOR gates. The outputs of the three XNOR gates are connected to the three inputs of the AND gates. If there is coincidence between the three bits of the input word and the three bits of the reference word are present, then deliver the three XNOR gates binary ones as output signals signals, and it this also creates a binary one at the output terminal of the AND gate, which is coincidence which shows input signals.

When a predetermined group of the eight possible input signals is identified should be, such as the binary words that contain the decimal values of, for example, 1, 2 or 3, then you can have three OR gates between the outputs of the three Insert XNOR gates and the three input connections of the AND gate. The last two digits Bits of the 3-bit control signals can then (as binary ones) first input connections are fed from two of the three OR gates, the other input terminals with are connected to the output connections of those XNOR gates that have the two '# last digits Bits of the 3-bit input signal are assigned.

Such control signals ensure that binary ones on two of the three input connections of the AND gates are given, regardless of the output signals come from the two corresponding XNOR gates. The most significant bit of the 3-bit control signal is set to a 0 so that if the most significant bit of the expected Input signal is also a 0, at the output of the associated XNOR gate one binary one appears, which is given to the third input terminal of the AND gate will. The AND gate only delivers a binary one at its output if that expected input signal has a value equal to 0, 1, 2, 3. Because of the inherent Properties of the state of the art, as can be seen from the following, the combinations of identifiable groups of words are limited.

It is obvious that when using the known Systt-ms for a large number of bits, such as 36 bits, 36 XNOR gates, 36 OR gates and a number of AND gates and various interlocking circuits are used will.

The invention described here not only performs the functions of prior art described above, but also a number of additional Functions with only a small fraction of those in the prior art required logic circuits and it has no restrictions on the number of Combinations of identifiable groups of words.

The system according to the invention comprises addressable memories with N-word spaces, which can be individually addressed by one of the groups of N digital signal combinations.

In the memory there is a signal of a first value, for example one 1, only stored in those word positions that are preceded by a corresponding of the selected word combinations are addressable. Reacts with this arrangement the memory is responsive to the application of any of the selected combinations of digital signals by generating an output signal that the storage of a signal of such first value at the addressed memory location, which in turn is a display indicates that the desired identification of the digital signal combination (and for addressing the memory) is in the selected combinations.

In the accompanying drawings, FIG. 1 shows a known structure, FIG. 2 shows a functional diagram of the system according to the invention, FIGS. 3, 4, 5 and 6 modifications of the diagram according to FIG. 2 in terms of different types and areas of word identifications and FIG. 7 a block diagram of the invention in one System with a data processor.

Let us first refer to the known structure shown in FIG received, assuming that the reference signal source 10 is set to supply a binary word 010 to indicate the occurrence of a Identify the same binary word 010 that is received from an input signal source 12 is supplied on output lines 13. If between the reference signal and the If the input signal coincides, then the signal levels are at the two inputs each of the three XNOR gates 14, 15 and 16 are the same. In detail are the input signals both zeros at the two inputs of the XNOR gate 14, the input signals to the both inputs of the XNOR gate 15 both ones and the input signals at the two Inputs of the XNOR gate 16 both zeros. This is the output of the three XNOR gates 14, 13 and 16 are all binary ones, which represent the three OR gates 17, 18 and 19 and get to the AND gate 20, which is then connected to its output line 21 generates a binary one. Such a binary one shows coincidence between the Reference signal from source 10 and the input signal from source 12. It lies obvious that when the input signals for any of the three XNOR gates 14, 15 and 16 were unequal, the output signals of the relevant XNOR gate would be one would be binary zero so that AND gate 20 would have a binary zero at its output would deliver. In the previous example it was assumed that the output signal of the irrelevant signal source 25 is a binary word 000, as it is in column A next to the control signal source 25 is indicated. As will be described below, these irrelevant signals ensure that the content of certain bit positions are irrelevant in the digital input signals, so they can be ones or zeros be, and thus form a group of input signals, which by commonality its remaining bit positions is defined because the signal source 12 has a 3-bit output signal delivers, you can get eight different address combinations of binary ones and Have zeros. Of these eight combinations, it is assumed that the AND gate 20 as Output signal a bi- should deliver a nary one to addresses, whose equivalent decimal values range from 0 to 3. This can be done, though the control signal source 25 supplies a binary number 011, as shown in column B next to the control signal source 25 is indicated.

This is how binary ones get to and through OR gates 18 and 19 regardless of the signal level supplied by the XNOR gates 15 and 16 will. It is clear that only the binary values equal to 0 to 3 will be an output from the AND gate 20 as long as the output values are at the most significant bit positions the reference signal source 10 and the control signal source 25 remain binary zeros.

The output signal at the most significant bit position of the OR gate 17 is only a 1 when the input signal source 12 has an output signal from Supplies 0 to 3, i.e. if the output values are at the most significant bit positions of the Input signal source 12 and reference signal source 10 are both binary zeros. If the input signal source 12 supplies a decimal value from 4 to 7, then this results at its most significant bit position a 1, and the XNOR gate 14 supplies a binary one Zero to the OR gate 17. Since the corresponding output signal from the control signal source 25 to the OR gate 17 is also a binary zero, is also the output signal of the OR gate 17 is a binary zero, so that the AND gate 20 generates a binary zero.

It can be seen in FIG. 1 that each bit position is an XNOR gate, an OR gate and a summing AND gate and means for locking or storing the pull-out signal as well as irrelevant signals. When the signals from the input signal source should consist of 36 bits, then you would need 36 XNOR gates, 36 OR gates and one Series of AND gates, so a considerable amount of logic circuits.

Refer now to Figure 2, which is a block diagram showing which illustrates an embodiment of the invention. The large block 30 includes the memory controller 33, the memory addresses 32, the read / write logic circuit of the memory 34 and the output circuit 36. The input signals, accordingly the input signal source 12 from Figure 1 are the decoder 31 of the memory logic circuit 30 is supplied via three input lines 35.

The input signal from lines 35, referred to here as signal S is, arrives in one of the eight memory cells 33 corresponding to that in the vertical Address given in column 32. Accordingly, a supplied on line 35 arrives binary input signal 010 in the memory cell with the address 010. The content of RAM address location 010 is a binary one like the vertical column 33 shows, and this indicates that the input signal 010 is the desired input signal is which one is to be identified.

It is understood that any input signal other than the binary number 010 reaches that memory cell which contains a binary zero, and thus indicates that the desired signal is not identified.

The memory cells in the vertical column 33 are practically eight Words of 1 bit each. Such eight words can be programmed through appropriate programming of the logic circuit 36, which may be part of the data processor. In detail, eight 1-bit words can be stored in the eight memory cells 33 via the Line 40 designated input data arrive. The input data line 40 can practically consist of eight lines, the eight "-bit words into the memory cells 33 enter in parallel under the control of a read / write control line 37, which in turn is controlled by the logic circuit 46.

With the special data word that is shown in FIG. 2 in the eight memory cells 33 is included, the circuit works so that only the binary input word with the value zero is identified, whereupon a binary one to output line 36 reaches memory logic circuit 30.

Assume now that some signal identifies S 101 shall be. Such an arrangement is shown in Figure 3, where only those memory cells contain binary ones whose addresses contain 101, 110, 111, respectively, all of which ~ 101 are.

The remaining five memory cells contain binary zeros.

It is clear that only the binary signals 101, 110 and 111 are binary ones generate at the output of the memory logic circuit. Any worth that are 101 lead to a binary output signal 0. The arrangement according to FIG 3 an output signal only when S is ~ 101.

Figure 4 shows a scheme of eight 1-bit words in the eight memory cells 33 are stored and for which the signal range from 011 ~ 5 ~ 110 is a binary Output of the memory logic circuit 30 causes. Specially generate in figure 4 the binary input signals 011, 100, 101 and 110 a binary output signal 1. All other input signals reach the memory cells which contain a binary zero.

According to FIG. 5, the function S = 1x1 should be carried out, with x represents a bit position in which it does not matter whether a binary one or zero. All input signal addresses, their highest and lowest Bits are binary ones, get to a word location in the eight memory cells 33, which contains a binary one. Therefore, according to Figure 5, the contents of the word memory locations with the addresses 101 and 111 each binary ones.

All other RAM addresses contain binary zeros. If that- according to one of the addresses 101 or 111, but only these two addresses, become accessible, then the memory delivers a binary one and thus fulfills the desired signal comparison function, where S = 1x1.

Figure 6 shows another example of selection and identification of input signals, whereby the content of certain bit positions is irrelevant. Intended to for example, the comparison function S = XOX can be carried out, where X is a 3it position represents in which the logical signal level is not relevant, then only all the few signals need to be detected for which the middle position contains a zero.

Thus, according to FIG. 6, the binary pattern is made up of the binary ones and zeros, which are contained in the eight memory cells are selected to have such a function perform.

SpeciEll contain the memory cells with the addresses 000, 001, 100 and 101 all binary ones. All of the leaded RAM addresses are included in their middle bit position and accordingly are in the allocated memory cell Zeros stored. This executes the function S = XOX.

FIG. 7 shows a logic system implementing the invention. A central computer (CPU) 50 supplies addresses on an address line 56. These Addresses are used in a common memory 54 and also in the memory logic circuit according to the invention 30 for eight 1-bit words, as shown in FIG. In figure 7, the same reference numerals are used as in FIG. 2 for corresponding parts.

Appropriate data words, each consisting of the eight 1-bit words in memory 30 exist, its logic circuit from the central computer CPU 50 via input line 40 and switch 51 under appropriate timing fed as well as a read / write sign on the die for entering such data words from Computer CPU 50 in the Spelchertogikschaltun <j 30 required clock and control circuit is known in the prior art and need not be described in detail here will.

If desired, the 8-bit data word of the memory logic.

circuit 30 supplied from an external data input source 33 which are connected to the memory logic circuit 30 via the switch 51 can. The shoulder 51 exclusively performs either of the memory logic circuit 30 Data word from the computer 50 or from the external source 53 to. The input source 53 for external data can be formed, for example, by eight toggle switches # i, which are manually adjustable to any desired data word in the memory logic circuit Enter 30.

When the circuit is operating, the memory logic circuit 30 delivers their output a binary one on the output line 36 if a positive comparison was carried out, as has been explained in connection with FIG. One such a binary one can be fed back to the computer 50 via the line 36, so that this interrupts the operation of the system, which for example for diagnostic procedures is required. The output signal of the comparison circuit of the memory logic sound 30 can also be used for other purposes, for example for actuating peripheral devices Facilities. In particular, memory logic circuit 30 may include one or more peripheral devices may be placed on any of a desired group received signals reacts and becomes active or inactive. In such an application would be the memory value or data word stored in memory logic circuit 30 is included, preferably entered using an external data input source, such as the data input source 53, although the input is also from the computer 50 could take place in the manner illustrated in FIG. Empty page

Claims (2)

Programmable comparison circuit Claims system for identification any of selected combinations (101, 110, 111 as in Figure 3) from a Group of N combinations (000 to 111) of di <; italsignalen, g e k e n n z an addressable memory (memory logic circuit 30) with N-word memory locations (000 to 111), which can be individually addressed by a corresponding combination from the group of N-digital signal combinations and in which a signal of a first value ("1") is only available at those word memory locations is saved by corresponding combinations of the selected combinations of digital words are addressable in such a way that the memory on any one of the selected combinations of the digital signals produces an output signal generated, which shows the first value and thus such an identification. 2. System according to claim 1, g e k e n n z e i c h n e t d u r c h a Means (line 36) for inputting the first value signal to only those Word locations of the memory, which correspond to the selected combinations of the digital signals correspond.