DE3128127A1 - COUNTER WITH NON-VOLATILE STORAGE - Google Patents

Description

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K. Wilmsmeyer 9 '- J * Fl 1082

Go / Be July 15, 1981

Counter with non-volatile storage

With the help of non-volatile readable electrically programmable Semiconductor memory elements such as MNOS transistors or floating gate transistors, it is possible to electrically change information from time to time to store that they are retained even if the supply voltage fails. Examples of memory cells with such electrically programmable semiconductor components can be found in the German Auslegeschriften 24 42 131, 24 42 132 and 24 42 134.

One of the simplest examples of a non-volatile storage counter is a mechanical counter like the is used, for example, as an operating hours counter or odometer. It is used as a memory for an n-digit Address digital word.

If such a mechanical counter in the form of a binary _T counter is designed as an electronic equivalent, which must have at least k cells if it is to be able to count from 0 to 2 -1, a problem arises which is based on the fact that each of the Memory cells would have to contain at least one non-volatile, electrically programmable memory element if the counter reading is to be retained over periods of time without operating voltage.

The non-volatile readable semiconductor memory elements, such as MNOS field effect transistors as well as field effect transistors with floating gate electrode, namely have the property that their storage capacity

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with the number of reprogramming decreases, what is called degradation referred to as. Therefore, only a limited number of programming cycles is permitted. In an electronic Counters with non-volatile storage must contain the new information with each further counting by reprogramming get saved. The problem is that in the limited number of write-erase cycles one at the same time Counting limit for the highest number that exists with an electronic counter with non-volatile storage can be achieved if a binary counter of conventional construction with electrically programmable semiconductor memory elements is used.

In the case of simple binary counters with electrically programmable semiconductor memory cells, with regard to the aforementioned Degradation of the programmable memory elements has the following two disadvantages:

a) The number of reprogramming is higher than the number of counting steps, because a carry an item of information must change its information at least two levels; total is the number of reprogramming is about twice as large as that of the counting steps.

b) The last bit (LSB) gets the most, namely

reprogrammed with each counting step and thereby determines the largest number to be saved (n-digit digital word), which is therefore at most twice as high (a cycle consists of two Reprogramming: writing and erasing) like the maximum time of possible Schrelb erase cycles of a memory transistor.

The object of the invention is to provide an electronic counter with non-volatile storage using of electrically programmable semiconductor memory elements

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of the type mentioned at the beginning, with which counter a large counter reading is possible without losing the storage time.

To solve this problem is in the invention of the

_ Basic idea assumed that a matrix memory for a ο

a certain number of low-order bits is used, its memory cells with non-volatile electrically programmable Memory elements of the type mentioned are programmed one after the other, so that all memory cells ^ O this matrix memory are evenly loaded. A binary counter also, with non-volatile, electrically programmable memory elements, then records how often the overall matrix is has been reprogrammed. The number of counting steps is increased by

a) only one for almost all counting steps

Memory cell is reprogrammed and

b) almost all memory cells are subjected to the same number of write-erase cycles.

In theory, if ζ is the number of write-erase cycles a memory transistor can tolerate when recording of N memory transistors in a counter, with non-volatile storage according to the invention except for 2. ζ. W counted even if 2 -1> 2z .N, which is certainly the case with sufficiently large N. It should be noted that with arrangements where only part of the cycle, such as only writing, is done individually for each memory transistor can, the maximum number of counting steps is smaller. The invention strives to this largest possible number possible to get close.

The above task is performed with a counter with non-volatile storage of an n-digit digital word

K. Wilmsmeyer 9 -b- ^p l 1082

according to the invention by the in the characterizing part of the patent

demanding specified training solved. , - ·

The invention is explained below with reference to the drawing,

1 shows the block diagram of the counter according to FIG

of the invention and FIG. 2 thereof shows the detail of a memory matrix

shows dynamic memory cells which each contain a non-volatile programmable memory element in the form of an MNOS field effect transistor and are each connected to a bit shift register cell of the counter according to the invention. b

In order to bring the number of maximum possible counting steps to the largest possible value, the counter according to the invention is divided into two parts. The main part is formed by the matrix M according to FIG. 2 from 2 non-volatile, electrically programmable memory elements, each of which contains at least one memory transistor of the type mentioned at the beginning. The 2 ^m memory elements of the memory matrix M are selected bit by bit via a word shift register WSR and a bit shift register BSR so that the 2 ^m memory elements of the memory matrix M are reprogrammed one after the other with each counting step.

In synchronism with the counting process in the memory matrix M, a counting process runs in the binary counter Bz, in which only one volatile storage is possible because it only contains non-programmable circuit elements and therefore not the is subject to degradation mentioned at the beginning. The binary counter Bz contains m + n bistable memory cells, of which η Memory cells calculated from the most significant bit MSB, each with a non-volatile memory cell of a main memory Hs

K. Wilmsmeyer 9 Fl 1082

are coupled. The main memory Hs contains like the; memory matrix reprogrammable memory elements.

If the 2 memory element of the memory matrix M has been rewritten, the m + 1 th bit of the binary counter «Bz receives the logical one with the next counting pulse. As shown in FIG. 1, this counting pulse is applied to a φ -clocked sequence control A and generates an erase signal at the second output A2, so that an erase pulse is generated in the erase pulse stage Er connected to the second output A2, and the entire memory matrix M is reprogrammed will.

The sequence controller A is designed so that a first erase signal occurs at the second output A2 even when a signal So is input into the sequence controller A at the start of counting. A second erase signal then occurs at the second output A2 after every 2 ^m counting pulses, but this only erases the memory cells of the memory matrix M.

In addition to the clock signal φ and the start-of-count signal So, the supply voltage U and, at Co, the counting pulses are applied to the sequence control A.

The sequence control is designed so that at the start of counting or after failure of the supply voltage at the first output Al a reset signal occurs, which generates reset pulses via the reset-read stage Rs, which the binary counter Bz, reset the bit shift register BSR and the word shift register WSR. Subsequently, according to the given program Generates read pulses of a read cycle in the reset / read stage Rs, with the help of which the information in the main memory Hs and are written into the binary counter Bz in the memory matrix M.

K. Wilmumeyer 9 - ^ - Fl 1082

At the start of counting, the memory transistors are both! in the memory matrix M as well as in the main memory Hs by an erase cycle, for example to low threshold voltage (U _DD ) values, which should represent logical zeros. A reset and read cycle then runs, as it does in the event of a power failure after the supply voltage has been switched on or switched on. The binary counter Bz thus contains the binary sequence 000 ... 0, while both the bit shift register BSR and the word shift register WSR have been brought to 100 ... 0.

The content of the Main memory Hs described in the bit positions m + 1 to η. Furthermore, the content of the first word of the memory matrix M transferred to the bit shift register BSR. With the help of the clock, the entire contained in the bit shift register BSR Information shifted once in the ring and registered by the binary counter Bz. The information consists of how whose type of counting still to be described emerges from an either completely or only partially with ones " occupied word. After a word filled with ones has been pushed into the ring, the next word in the memory matrix becomes M read, shifted in the ring and written into the binary counter Bz. After a word with at least one zero will be no longer moved to the next word, but with the counter reading reached in the binary counter Bz according to the in the memory matrix M existing counter reading transferred to normal counting operation.

The sequence control A is also designed in such a way that a write signal is sent to the third output A3 for each counting pulse occurs, in which the gate lines GL of the memory matrix M and the input of the binary counter Bz via the bus Bl after is supplied with a write pulse for each counting pulse.

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K. Wilmsmeyer 9 ^ e *. Fl 1082

Thus, each counting pulse is registered both in the binary counter Bz and in the memory matrix M. In the storage matrix M takes another memory cell corresponding to that of the word shift register WSR and the bit shift register BSR selects the state of the previous memory cell. The new status of the bit shift register BSR is written into the word identified by a single one in the word shift register WSR. Is the bit shift register BSR full, the one in the word shift register WSR is shifted one place and the bit shift register BSR standardized (100 .... 0). Are all storage elements of the Memory matrix M written, both the main memory Hs and the memory matrix M are erased and those in the binary counter Information containing Bz is written into the main memory Hs. After that, both the bit shift register BSR and the word shift register WSR normalized, d. H. brought to (100 ..., O).

In the example explained above, it was assumed that the non-volatile storage takes place in memory cells, which can be written bit by bit and deleted word by word. Since in the memory matrix M certainly without further ado 1000 or 2000 memory transistors can be integrated, the largest number that can be stored increases compared to that of the Binary counter of the type mentioned above with memory transi-

3 interfere with each level by a factor of 10.

Depending on whether the non-volatile electrically programmable Memory elements with one or two transistor cells '30 are designed with either bit-by-bit or line-by-line erasure, the overall circuit and the program sequence of the binary counter Bz can be easily changed.

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In the simplest case, the storage elements of the storage matrix M each consist of a storage transistor, for example an MNOS field effect transistor. 2 shows the detail of a circuit of such a memory matrix with four memory cells, each of which contains an MNOS field effect transistor TIl, Tl2, T21, T22. The gate electrodes of the MNOS field effect transistors TI1, T12, T21, T22 are connected in rows _{to the word lines WL1 1 WL2.} The source electrodes of each column are connected to the set input of a flip-flop cell FF1, FF2, FF3 of the bit shift register BSR, while the drain electrode receives _{the supply voltage U DD.}

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Claims (1)

K. Wilmsmeyer 9 Fl 1082 Go / July 15, 1981 Claim Counter with non-volatile storage of an n-digit digital word, marked, a) by a memory ^{matrix (M) of 2 m} non-volatile, electrically programmable memory elements, which can be selected bit by bit via a word shift register (WSR) and a bit shift register (BSR). b) by a binary counter (Bz) with m + η bistable memory cells, of which η memory cells from Most significant bit (MSB) calculated with one non-volatile memory cell of a main memory (Hs) are coupled, c) by a clocked sequence control (A) with - a first output (Al), at which, when counting, beginning or after failure of the supply voltage a reset signal occurs, whereby the Binary counter (Bz), the bit shift register (BSR) and the word shift register (WSR) reset be, and on the subsequent reading pulse of a read cycle with which the information in the main memory (Hs) and in the memory matrix (M) are written into the binary counter (Bz), - a second output (A2), at which a first clear signal occurs at the start of counting, which Erases memory cells of the main memory (Hs) and the memory ^{matrix (M) and at which a second erase signal is generated after every 2 m} counting pulses, which the memory cells of the Memory matrix (M) clears, • · · »J K. Wilmsmeyer 9 -? - Fl 1082 - the input of the binary counter (Bz) with a counting pulse and at each counting step the gate lines (GL) of the memory matrix . (M) supplied with a write pulse.