DE3111991A1 - Equipment connection multi-master bus structure - Google Patents

Abstract

The invention relates to an equipment connection multi-master bus structure in an arrangement with a microprocessor, a number of peripheral controllers and a main memory. One bus allocator is allocated to both the microprocessor and to each peripheral controller. Thus, the peripheral controllers also obtain the master status with respect to access to the equipment connection multi-master bus. The solution of priority problems is the responsibility of the bus allocators. A number of such arrangements can be combined via a system multi-master bus to form a multiprocessor system. <IMAGE>

Description

Device connection multi-master bus structure.

The invention relates to a bus structure according to the preamble of claim 1.

By the literature "Elektronid", 1979, issue 20, page 73 bis 77, a multi-microcomputer system is known in which the data exchange between the individual computers or the memories assigned to them by a control device for direct memory access (DMA control) is mediated. The programming the DMA controller, d. H. the indication of the transmission direction and the specification the data to be transferred is only done by a so-called dialog computer. If required, he can use one of several function computers with equal rights Exchange data.

The dialog computer is therefore in relation to the access to the system bus always given priority while the function computer was accessing the bus are subordinate. However, such a master-slave structure has the disadvantage that the privileged processor is largely occupied with organizational tasks and the examination of such systems is made more difficult. This deficiency can be caused by the provision of a special bus computer can be mitigated, but not completely eliminated because the problems that arise are only partially relocated.

A multiprocessor system in which each processor according to the gain access to the common system bus of their own accord is by the "SAB 8086 Family User's Manual", October 1979, pages A-111 bis A-130 from Intel Corporation, Santa Clara, California, USA, hereinafter referred to as 8086 Manual, known.

In this microprocessor system, each microprocessor is next to one Bus control and other auxiliary equipment a certain part of the working memory and a bus arbiter. The bus assigner leads in connection With the bus control, the processor is connected to the system bus. Of the Processor is not influenced by the bus allocator and gives, for example Commands look as if he had the system bus at his sole disposal. if If the processor has not occupied the system bus, the bus assigner takes care of the shutdown the bus control, the data transmitter and the address buffer from the system bus by having for example, the outputs of the relevant line drivers in the high-impedance State shifted.

The system bus of the well-known multiprocessor system is called the multi-master bus referred to because all processors are in themselves equal and one that has been started Transfer cycle cannot be interrupted by a bus request from another processor is. The processors are therefore masters in relation to the system bus. But there are several Processors can request access to the system at the same time, every processor will assigned a priority. The bus assigners are designed to work with each other solve the priority case at hand.

First of all, it is assumed that at a certain point in time the system multi-master bus is not occupied, then receives from all bus assigners, who request the bus, the bus assigner or the master assigned to it with the highest priority access to the bus. After the transfer cycle is complete, the bus on request the bus master with the now relatively highest priority for you Cycle allocated. This also applies if the bus master who just still owns the bus had made a new request and had a higher priority than the others Bus applicants owns.

With regard to the way in which the priority problems are resolved, it is with the known bus allocator possible, a parallel, serial or rotatingCes scheme to be realized (see 8086 Manual, Section AP-51).

For the cooperation of the processors each with a group of peripheral elements, such as input and output devices, magnetic tape devices, etc. takes place usually using a direct memory access (DMA) controller , compare 8086 manual pages B-92 to B-105). A DMA controller can have up to four Supply channels. Access requests of the channels are sorted according to their priority treated. The priority assignment depends on the order in which the lines for the request signals connected to the relevant inputs of the DMA controller are. Instead of channels, additional DMA controls can be connected.

Every transfer operation via a DMA controller, especially theirs Initiation and termination also occupy the processor with which the DMA control is carried out directly or indirectly connected. The processor cannot during this time otherwise become active.

The invention is based on the object of a multi-master bus structure indicate in which a processor, in particular a microprocessor and several peripheral Control devices, for example DMA controllers, act as bus masters and get access to a main memory or assigned main memory part can.

According to the invention, this object is achieved with a device connection multi-master bus structure resolved at the the control devices and the microprocessor each a bus allocator is assigned to control bus access based on requests and according to the priorities assigned to the controllers and the processor. This relieves the processor of administrative tasks considerably.

Preferably the invention is implemented within a. Multiprocessor system used in which a common multi-master system bus for several processors provided and each processor a bus allocator to control the system bus access is allocated.

In the following the invention is illustrated with reference to one in the drawing Embodiment described in more detail.

It shows: FIG. 1 a block diagram of the device connection multi-master structure according to the invention, 2 shows the connection of a peripheral designed for direct memory access Control nn the device connection bus, Fig. 3 the correspondingly modified connection some connection points of a commercially available bus allocation module.

Fig. 1 shows a simplified schematic representation of a Arrangement with a microprocessor 1 (CPU), which has both a system multi-master bus 2 (SMM-BUS) with further microprocessors as well as via a device connection multi-master bus 3 (DMM-BUS) cooperates with peripheral (device) controls 4 to 6.

With the microprocessor 1 are for connection to the system (multi-master) Bus two in a manner known per se via a local bus 7 for status signals and a local bus 8 for addresses and data a bus allocator 9 (art) one Bus control 10 (Contr), an address buffer 11 (A-L) and a combined send Receive module 12 (Trans) connected. The microprocessor can 1 in the working memory 13 (#) or to a part thereof. A decoder or Read-only memory 14 (PROM) allows, in the case of one, to address the entire main memory If the address range is insufficient, dynamic allocation of the addressable Part of the main memory 13. Finally, the clock 15 should be mentioned, the clock for the microprocessor 1, the bus allocator 9 and the bus control 10 delivers and processes incoming ready messages asynchronously. A closer look on the part of the arrangement according to FIG. 1 treated so far is superfluous. For this reference is made to the 8086 manual, especially section AP-51. ' For connection of the microprocessor 1 to the device connection bus 3 are again the same connection elements provided as for connection to the system bus 2. With the local buses 7 and 8 are also a bus allocator 16, a bus controller 17, and an address buffer 18 and a send / receive module 19 are connected.

The already mentioned connections of the peripheral controls 4, 5 and 6 with the device connection bus 3 are only indicated symbolically in FIG. Indeed these connections are handled via several auxiliary facilities, as is still the case is described in more detail. According to the invention, each of the peripheral controls 4 to 6 are assigned their own bus assigners 20, 21 and 22. The inputs and outputs for the priority controls of all bus assigners 16, 20, 21 and 22 for the access control to the device connection bus 3 are connected in series. The input of the bus assigner 22 is grounded. This gives the peripheral controller 6 the highest priority for Bus access. Details can be found in the 8086 manual, pages A-113 to A-115 remove.

Units such as registers, Timers, interrupt controllers and the like can only be connected can access the bus when no bus master requests bus access. Such Units for which the unit 23 is shown as a representative in FIG. 1 have the Slave status.

In Fig. 2 is the connection of a peripheral controller as an example for direct memory access (DMA control, 8086 Manual, pages B-92 to B-105) the device connection bus 3 is shown. The DMA controller 25, which is one of the control devices 4 to 6 in Fig. 1 is connected to the bus 3 via a plurality of sub-buses. These are the bus 26 for the address bits A0 to A3, the bus 27 for the address bits A4 to A7, the bus 28 for the address bits A8 to A15 and the bus 29 for the data bits DBO to DW. Since the DMA controller addresses the address bits A8 to A15 and the data bits DBO to DB7 or DB8 to DB15 output or via the same connections. takes up is to Splitting or merging of the two partial buses 28 and 29 from the DMA controller 25 address separator 30 controlled via control lines (not shown) is provided. All sub-buses with the exception of bus 27 are for two-way transmission intended.

With the DMA controller 25, the assigned bus allocator 31 is over two lines for a bus request signal HRQ and a Qittungssignal HLDA connected.

Four device controllers 32 to 35 are managed by the DMA controller 25. That corresponds to the maximum number. The device controls 32 to 35 give over four lines DREQO to DREQ3 requests to the DMA controller 25 and received A further four lines DACKO to DACK3 acknowledge signals when a request is made was successful. It is known by the order the connection of the device controls 32 to 35 to the individual lines DREQO to DREQ3 the priority with which the requirements of the device controls 32 to 35 on the DMA control to be served.

The device controls 32 to 35 handle their data traffic with the Device connection bus 3 in both directions via a common data bus 36, which is split into two branches by the send / receive modules 37 and 38. The connections for the release signals of the send / receive modules 37 and 38 and for the signals for controlling the transmission direction are shown in FIG. 2 for reasons not shown for the sake of clarity.

Lines for further tax campaigns are also not shown, which are important for the operation of the DMA control, but the relevant Documents can be taken as their function by the assignment of a d # microprocessor 1 (Fig. 1) relieving bus allocator is not changed. Here is mainly on the signals MORE, i, IOR and IOW for controlling memory accesses and data traffic to point out.

The connection of the peripheral control devices 4, 5 and 6 assigned bus allocator 20, 21 and 22 (see FIG. 1) differs slightly different from the connection of the other bus allocators, which was carried out in a known manner 16 and 7. In FIG. 3, only those connection points of one of the bus allocators 20 are to 22 that are affected by the changes. That of the connected Bus request signal HRQ sent out by DMA control is due after inversion the inverter 40 at the input for the status signal 5. The input for the status signal 51 is held at a potential corresponding to the binary "1". As in Fig. 3 is indicated by the connections shown in dashed lines, can be connected to the input a binary “1t” or a binary “O” can be applied for the status signal S2 first case there the bus assigner automatically disconnects the bus, if a transfer cycle is over. In the second case, this only happens when a request is made another bus master is present.

The signal AEN serves as an acknowledgment signal after inversion by the inverter 41 HLDA for a successful bus request by the DMA controller. (Compare Fig. 2).

3 Figures 3 claims

Claims (3)

Patent claims O device connection multi-master bus structure for production of connections between a processor, in particular a microprocessor, a plurality of peripheral control devices and a working memory module, d u r c h it is noted that the microprocessor (1) and the control devices (4, 5, 6) one bus allocator (16, 20, 21, 22) each for classifying the access requests to a device connection multi-master bus (3) corresponding to the control devices (4, 5, 6) or the microprocessor (1) assigned priorities, as well as auxiliary equipment are assigned for the bus connection. 2. Device connection multi-master bus structure according to claim 1, d a d u r c h g e k e n n n z e i c h n e t that at least one control device for direct Memory access is formed. 3. Gera tenaschluß multi-master bus structure according to claim 1 or 2, d u r c h e k e n n n z e i c h n e t, that for several microprocessors one common system multi-master bus (2) is provided that each microprocessor another bus allocator and other auxiliary equipment for connection to the System multi-master bus (2) are allocated and that the bus allocator has access the microprocessors to the common system multi-master bus (2) according to the regulate the priorities assigned to one another by the microprocessors.