DE3009530C2 - - Google Patents

Description

The invention relates to a functional unit such as a processor or I / O unit for a digital data processing system with a memory, a common bus and at least one another functional unit, according to the preamble of Claim 1.

A digital data processing system generally has three Basic elements on: a memory, an input / output unit and a processor. The memory stores information in addressable Locations. This information assigns both data also commands to process the data. By the processor the information is transferred between it and the memory; the processor either evaluates the incoming information as data or commands and processes the data according to the Command. The input / output unit also stands with the memory in connection to transmit input information to the system and to receive information processed by him.

Since years the demand for computing power and speed  has risen, is already proposed and it is also known to have multiple processors in one processing system to use. In such multiprocessor processing systems each processor should normally have one partial or full access to the same storage and have input / output units. Hence facilities be provided to prevent the processors have access to the same unit at the same time. For this are various arrangements known.

In a first order priority values are assigned to the processors, whereby then processors with a higher priority than processors with a low priority access to the memory and Input / output units is permitted. This makes it inevitable orbital time for programs slowing down Rotate low priority units.

In a second arrangement, a computer circuit is included a host computer system provided to switch between a number to decide subordinate or subprocessors. These Decision can be made by factors such as the length of time that a Auxiliary processor access to the memory or the input / output unit the time since the last access, u. Ä. fixed be. However, if the master system fails, that is prevents the slave processors from accessing to the storage or input / output units, up to the main system is repaired. It can also in the Main system come to a bottleneck when it comes to the master system access to the storage or input / output units must decide too quickly, so that the Slave processors are slowing down.

In a third arrangement, there is a two-way arrangement Control unit between the processors and the memory and Input / output units provided to allow access between the Processors and the storage and input / output units Taxes. This reciprocal control unit prevents however, not that the processors work themselves while  they are waiting for access to the storage and input / output units to have. Otherwise this arrangement results the same difficulties as those mentioned above Master-slave processing system.

As the demands on computer performance continued to increase there must be more and more tax information between the different Go through units and parts of the system. For this is also a number of control lines between the Units and parts required, reducing both the cost for the control line itself as well as for the additional ones electronic circuits that are required to rise evaluate information on the lines and information to accommodate on the lines.

In another known data processing system with Functional units of the type mentioned at the beginning (US-PS 40 00 485) is a function with an operation with locking effect initiated in that a test and set bus command in particular is transferred to a common memory. At This known device must be accessed every time about the memory is desired, a query operation is performed after which an adjustment operation must be performed if access is not prevented. Therefore it would be not only desirable to reduce processing time can, but also an efficient use of the bus Enable bandwidth.

It is an object of the invention, in particular with a shared memory enabling communication links To improve functional unit so that with as little as possible circuitry effort a simultaneous access to the common bus without carrying out previous test and setting operations can be avoided. This task will according to the invention by the subject matter of the claim solved.  

By distributing the access regulating circuit two advantages are achieved in particular. First, they have to Functional units not just any external facility like for example querying a main processor or a memory, to see if access is possible. This will shorten the time it takes to make a decision is required for access. Second, the functional unit itself about information, causing the data fetch process is reduced to a single operation.

For example, if multiple processors are provided, a lock command issued by a processor by everyone other processors received. This command prevents the other processors a lock command of the same type can be transmitted before a release command takes effect. Each processor can issue such a release command.

Another advantage of the invention is that it does not a plurality of lines between the functional units required but with the help of a controlled line can be displayed that the information transmission lines are in use.

Based on the drawing, the invention is intended to be more specific, for example are explained. It shows

Figure 1 is a block diagram of a digital data processing system with functional units according to the invention.

Figs. 2A to 2C schematically types of data that are used in connection with a particular embodiment of the invention;

Fig. 3 lines and corresponding signals for establishing a connection in the digital data processing system in Fig. 1;

Fig. 4 is a diagram showing the order of a read transaction that can occur between the units shown in Fig. 3;

Fig. 5 is a diagram showing orders of operations for a read transaction that may occur between the units shown in Fig. 3;

Fig. 6 is a circuit diagram of part of the master unit shown in Fig. 3 and

Fig. 7 is a schematic circuit of part of a slave unit shown in Fig. 3.

As shown in FIG. 1, for example, the basic elements of a data processing system, in particular a multiprocessor system, have a first central processor 10 , a second central processor 10 A , storage units 11 and input / output (I / O) units 12 . A bus 14 connects the central processors 10 and 10 A , the memory units 11 and the I / O units 12 . In a multiprocessor system, more than two central processors can also be connected to the bus 14 . They would then be connected to bus 14 in a manner similar to processors 10 and 10 A.

The central processor 10 has a control panel 15 , a bus interface and other conventional circuitry that is normally housed in the central processor. Be the central processor 10 and other A central processors which can be connected to the bus 14, as may the processor 10 is formed; however, it is necessary that the central processors can be coupled to a bus 14 . An interface circuit 16 receives all data from the memory and performs all transactions for the other circuits in the central processor 10 .

The control panel 15 serves as an interface for the operator. From here, the operator can check and store data, stop the operation of the central processor 10 or step through a series of program commands. An operator can initialize the system through an initial input (bootstrap process) and can perform various diagnostic tests on the entire data processing system. The central processor 10 A generally has a control panel (not shown).

In Fig. 1, the memory unit 11 to a memory control unit 20 which is connected to a number of storage panels 21.

Various types of I / O units 12 are shown. An I / O bus adapter 22 connects several input / output devices 23 , such as teleprinters or cathode ray tubes, to the bus 14 (US Pat. No. 37 10 324).

The two other I / O units 12 shown in FIG. 1 create a secondary storage device for the data processing system. They have a secondary storage bus adapter 24 and a number of disk drives or drives 25 . Furthermore, a second secondary memory bus adapter 26 and a belt drive 27 are shown. The connection of the secondary storage bus adapter 24 and 26 and their respective disk drives 25 and the belt drive 27 are known per se (US-PS 39 99 163).

The bus connects the different ones Units or parts of a data processing system. Before an information transfer between different pairs of units connected to the multiple line are described, it may be useful first to find some definitions of expressions or introduce terms that have already been used and that will be used in the future.

"Information" is intelligence that is used for control and creates the basis for data processing. It includes data and address as well as command and status information. The term "data" includes information which is the subject or result of processing. Information transfers between the units in the data processing system shown in FIG. 1 take place via the bus 14 and include transfers of discrete information data words. Each data word has a characteristic length on bus 14 . Other units can process information data words of different lengths. The simplest information data word is the byte. In a particular embodiment of the data processing system shown in Figure 1, the byte has eight binary digits (or bits). In Fig. 2A, eight contiguous bytes are shown. The next larger data word length is a "word" as shown in Figure 2B. A word has two contiguous bytes. Two contiguous words form a "long word", as shown in Fig. 2C.

The bus 14 can transmit all information in parallel as a long word. In the two contiguous long words shown in Figure 2A, byte 0 is the least significant byte location of each long word. Word 0 and long word 0 are the least significant word and long word positions in Figures 2B and 2C, respectively. In the following description it is assumed that corresponding alignments are obtained in the data processing system; however, there is no condition or requirement that any of these orientations be maintained.

If two units have to exchange information via the bus 14 , at least two transactions via the bus, ie two "bus transactions", are necessary. During a first bus transaction, a unit requests information exchange and transmits command and address information to bus 14 . The other element, determined by the address information, speaks and prepares for the exchange of information. This ends a first bus transaction. During the second bus transaction, the information to be exchanged runs via bus 14 .

Each unit that is connected to bus 14 is called a link (nexus). The special system shown in Fig. 1 has 6 links. A link is defined in the form of its function during an information exchange. During such an exchange, the link which transmits command and address information to the bus 14 is referred to in FIG. 3 as the "master link" 30 A. The unit which responds to this command and address information is referred to as "slave or secondary linkage" 30 B. Thus, when a central processor needs to retrieve data from memory controller 20 , the central processor becomes a master or master link and transmits a read or a read lock command and a memory address during a first bus transaction. The memory control unit 20 becomes a subordinate link when it receives and accepts the command and address information from the bus 14 .

A link is also defined as a sending or receiving link unit. A sending link unit drives the signal lines, while the receiving link unit scans and checks the signal lines during each bus transaction. In the following example, the central processor is a sending link during the first bus transaction and a receiving link during the second bus transaction. Similarly, memory control unit 20 is a receiving link unit during the first bus transaction and a sending link unit during the second bus transaction. Similar transactions occur when information is exchanged between any other linking units. However, the memory control units normally only function as slave link units, while central processors normally function as master or main link units.

In the illustrated embodiment of the invention, bus 14 carries a number of signals to and from the various units which are connected to it via corresponding lines. These lines and signals can be listed in three general classes:

• 1. A decision signal via the decision line 31 of the bus;
• 2. An information transfer over the data / address lines 32 and 33 of the bus and
• 3. A control signal via control lines 34 through 38 of the bus.

Lines 31 to 38 form bus 14 . The data address or information transfer bus has information lines 32 and function lines 33 . Commands are issued via function lines 33 .

The control lines and signals have a status line 34 , a holding line 35 , a waiting line 36 , a DBBZ line 37 and a clock line 38 . The status information indicates whether the addressed memory location has the requested information and whether the information is valid. The hold signal, when inserted on hold line 35 , prevents any gates from controlling the data / address bus. Hold signals can be used, for example, to control the speed at which write transactions occur in certain memories.

The wait signal asserted and enforced on the wait line 36 includes interrupt transactions. The blocking signal DBBZ or the data / address bus busy signal indicates when it is asserted on the blocking signal line 37 and enforced when a link via the data address bus is requesting information or transmits.

A number of commands can be sent via the function lines 33 , in particular read, read lock, write and write lock commands. When a link unit issues a read command, it asks to read the contents of a memory location whose address is transmitted over the transmission lines 32 . A read lock command indicates that the commanding link unit requests to read the addressed memory location and prevents other link units with their own read lock commands from accessing the bus until a write enable command is given to the function line. The read lock command does not prevent another master link unit from issuing a read or write command. The read lock command is primarily used to prevent other processors or link units from accessing a memory in which there may be invalid information, or possibly reading invalid information. This is possible if the processor that originally issued the read lock command has access to the memory and can modify information in the memory at the same time that another processor tries to read it from the same memory. To prevent this, the first processor issues a read lock command to ensure that other link units are prevented from accessing the memory.

As stated above, two bus transactions are required for each read and write transaction. In Figs. 4 and 5 examples of a read and a write transaction are shown for the reproduced embodiment. In Figs. 4 and 5, the positive are shown (to be claimed) signals to simplify the description or claimed to be correct when they have a high level. Grounded stress circuits and signals (ie, asserted or correct when they are low) usually complement this logic. The transformation between positive and grounded logic, which is based on the so-called Morgan theorem, is known per se.

FIG. 4 is an example of a read transaction between two link units shown in FIG. 3. The clock pulses characterize and limit the various cycles on the bus, with a new cycle beginning on the leading edge of each positive pulse. If the master link unit wants to use the bus to read from a subordinate link unit, for example a memory, the master unit asserts its priority signal on the decision line 31 . If its priority is the highest, and if the hold and DBBZ lines are all at the unused level, the master receives control of bus 14 by asserting the DBBZ signal, as shown at time B in FIG. 4 . The master unit claims the DBBZ line for one cycle and simultaneously transmits address and control information on the data / address line 32 and 33 . The master unit then shifts the blocking signal DBBZ to an unused level.

The addressed slave unit claims the DBBZ line from time C to time D , as shown. No other link unit can then gain control of the bus as long as the slave unit uses the DBBZ line. When the slave is ready to transmit information to the master, the slave shifts the DBBZ signal to an unused level and, as shown from time D to time E , transmits the information on the data / address line and gives at the same time return status information on status line 34 .

Since the DBBZ line is no longer used after time D , another main unit can try to maintain control of the multiple line during the cycle starting at time D. During this cycle, it can then assert its priority signal and claim the DBBZ line during the cycle beginning at time E to transfer address and control and to start a new transaction. This allows the transactions to overlap in one cycle, reducing transaction time. In other words, more accesses to a memory can be attempted during a given period of time than if the transactions on the bus do not overlap. This overlap is shown in part by the status signal in FIG. 4. The left most significant status signal, which was emitted during the cycle immediately following time B , can originate, for example, from a previous transaction.

This then makes both the main unit and the subordinate Unit a DBBZ signal on the same line applicable, reducing the number of lines required on the bus is reduced. The practice was to provide a number of busy lines that indicate that the  Bus is in use. By reducing the number of the busy lines can be the total number of lines in the bus and, consequently, the circuitry used to Driving this line is required to be downsized.

In Fig. 5 a waiting transaction is shown as an example. A master unit wishing to have a wait transaction asserts its priority signal through decision line 31 . If the hold and DBBZ lines are both at a non-asserted level and the priority of the main unit is the highest, it receives control of the DBBZ line and claims the DBBZ line. It then simultaneously transmits address and control information to the data / address line for one cycle. The addressed subordinate unit uses the DBBZ line and receives the signals on the data / address line. At the beginning of the last cycle, the slave shifts the DBBZ signal to an unused level and transmits status information on status line 34 . The last cycle then begins at time D. Since the DBBZ line is low, another master can assert its priority signal, and if the hold and wait lines are not used, it can gain control of the bus by claiming the DBBZ line at time E.

In Figs. 6 and 7 show examples of the master or slave circuits are shown which move the DBBZ line between asserted and non-claimed levels. A command signal device 50 shown in FIG. 6, which is provided in each functional unit, prevents another functional unit with a read inhibit command from gaining access to the DBBZ line 37 if a functional unit has previously issued a read inhibit command that was issued by a write-release command has not been released.

The command signal device 50 has a command decoder 51 , which actuates the command signal device in accordance with a read or write command, a read lock command READ LOCK or a write release command WRITE UNLOCK. When a read inhibit command is issued, decoder 51 outputs a high input to a NAND gate 52 and a high input to an AND gate 53 . As described below, when the second input of NAND gate 52 is low, the output of NAND gate 52 becomes high, and when the latch signal is low (not asserted) when the decision line of the main unit is high (indicating) is that this main unit has priority) and if the DBBZ line is continuously low (not used), the output of the AND gate 53 is high. At the next clock pulse from a clock generator 54 , the set output of a D flip-flop 55 goes high, as a result of which the DBBZ line 37 is shifted to a high (claimed) level. An inverter 54 A then makes the output of the AND gate 53 low. At the next clock pulse, flip-flop 55 is reset, causing the DBBZ line to shift to an unused level. As a result, the main unit takes up the DBBZ line for one cycle for the time between the first two clock pulses.

The command signal device 50 has an AND gate 56 and a D flip-flop 57 , which identifies the first cycle of a master bus transaction. Before the flip-flop 55 takes up the DBBZ line, the reset output of the flip-flop 57 , like the one input of an AND gate 56, goes high. When the flip-flop 55 is DBBZ claims the line of the second input of the AND gate 56 high, and its output is also high. At the next clock pulse, the flip-flop 57 is set, its reset output goes low and the AND gate 56 thereby goes low. The AND gate 56 is consequently high only during the first cycle, which is otherwise called the address cycle.

The command signal device 50 has a JK flip-flop 58 which recognizes the transaction on the bus as a transaction which was initiated by the relevant functional unit as a master unit. When the output of the AND gate 53 goes high on the next clock pulse, the set output of the JK flip-flop 58 also goes high (and its reset output goes low). The fact that the set and reset outputs of flip-flop 58 go high and low indicates the transaction initiated by this master unit.

The command signal device 50 also has a second JK flip-flop 59 , which detects when a read lock command on the function lines and when a command has been issued. The flip-flop 59 also recognizes when the previous read lock command has been issued by this special master unit. If this master unit has issued the read lock command, it is not prevented that another read lock command is issued. With the flip-flop 59 , this is achieved in the following way. If a read disable command is placed on the function lines 33 during an address cycle, inverters 60 A decode the command on the function lines and step up the function inputs on the AND gate 60 . This causes the output of the AND gate 56 to go high. When the read lock command is no longer issued by the command signal device 50 , the reset output of the flip-flop 58 goes high. As a result, the output of the AND gate 60 goes high and at the next clock pulse the set input of the JK flip-flop 59 goes high. When the set output is high and a read inhibit command is decoded by decoder 51 , NAND gate 52 is driven low and command signal device 50 cannot use the DBBZ line. The set output of the JK flip-flop 59 remains high until the K input is driven high with a clock pulse. This is the case if a write enable command is issued on the function lines during an address cycle. The inverter 61 A decodes this command and sets the functional inputs of the AND gate 61 . During the address cycle, the output of the AND gate 56 goes high, which sets the output of the AND gate 61 high. As a result, the flip-flop 59 is reset and its set output low. The flip-flop remains reset until it is set again by a read lock command. If the set output is low and when a read lock command is decoded by the decoder 51, the NAND gate 52 is high, so that the command signal 50 may take the DBBZ line.

On the other hand, when the command signal device 50 issues the read lock command, the reset output of the flip-flop and the output of the AND gate 60 go low. The flip-flop 59 thus remains reset and its set output goes low. The NAND gate 52 passes a read inhibit command when the output of the flip-flop 59 is low, which can only occur if the previous read inhibit command has been issued by the command signal device 50 or if this command has been invalidated by the write enable command.

FIG. 7 shows an embodiment of a slave circuit 70 for driving the DBBZ line. When the master unit outputs address information on the data / address line, an address decoder 71 decodes the address and designates this link unit as the addressed slave unit. The decoder 71 is connected to an input of an AND gate 72 , the output of which is connected to the J input of a JK flip-flop 73 which drives the DBBZ line 37 . The DBBZ line 37 is in turn connected to an AND gate 76 and the D input of a flip-flop 77 . The reset output of flip-flop 77 is connected to the other input of AND gate 76 . The output of the AND gate 76 is connected to the second input of the AND gate 72 . The flip-flop 77 identifies the first (address) cycle of the transaction on the bus in a similar manner as was done with the AND gate 56 in the command signal device 50 . The address cycle is used for one cycle, after which it is shifted to an unused level. When the address cycle is claimed, flip-flop 73 drives DBBZ line 37 . During the subsequent clock cycles, the address cycle and AND gate 72 go low, but flip-flop 73 remains on (or claimed) until, as explained below, the information can be dispatched.

A command decoder 78 in the slave link unit detects when the data is ready to be transmitted over the data / address line; the data ready H line then goes high, causing the flip-flop 73 to reset and the DBBZ line 37 to go low. As a result, the output of the AND gate 76 is controlled low, which in turn controls the output of the AND gate 72 low. The flip-flops 73 and 77 are both controlled by the clock 54 .

According to FIG. 6, a read lock command is not issued by the command decoder 51 in a write transaction. The read lock command line becomes low (not claimed) so that the link unit can write whether there is a read lock command on the function lines or not. The memory request H line is claimed for a read transaction, thereby driving the AND gate 53 high and setting the flip-flop 55 that drives the DBBZ line 37 . The slave unit claims the DBBZ line in a write transaction in a similar manner to a read transaction. The slave unit drives the DBBZ line 37 until it receives a command indicating that the next cycle is the last cycle. The command decoder 78 of the slave unit then drives the data ready line H high, whereby the flip-flop 73 is reset. Status information is then transmitted from the slave unit to the master unit via the status line.

Claims (1)

Functional unit ( 10, 10 A , 12 ) such as processor ( 10, 10 A ) or I / O unit ( 12 ) for a digital data processing system with a memory ( 11 ), a common bus ( 14 ) and with at least one further functional unit ( 10, 10 A , 12 ), which memory ( 11 ) and which functional units ( 10, 10 A , 12 ) are connected to the common bus ( 14 ), the lines ( 31 to 38 ) for the transmission of data and command signals between the functional units ( 10, 10 A , 11 ) and the memory ( 11 ), each functional unit ( 10, 10 A , 12 ) having a command signal device ( 50 , Fig. 6), characterized in that

• - That the command signal device ( 50 , Fig. 6) on read lock commands (READ LOCK) and write-release commands (WRITE UNLOCK), which are generated by the functional units ( 10, 10 A , 12 ) and by the functional units ( 10, 10 A , 12 ) are received, so responsive, so
• - That it generates a blocking signal ( DBBZ ) on the blocking signal line ( 37 ) of the common bus ( 14 ) when a functional unit ( 10, 10 A , 12 ) as a master functional unit ( 10, 10 A , 12 ) access to the common bus ( 14 ) and has issued a read lock command (READ LOCK) on the function lines ( 33 ) of the common bus ( 14 ) and
• - That the blocking signal ( DBBZ ) acts on the command signal devices ( 50, Fig. 6) of the other functional units ( 10, 10 A , 12 ) in such a way that they are prevented as long as a master functional unit ( 10, 10 A , 12 ) to gain access to the common bus ( 14 ) and to issue a read lock command (READ LOCK) until the blocking signal ( DBBZ ) is released by issuing a write release command (WRITE UNLOCK).