DE3071038D1 - Clock derivation circuit for double frequency encoded serial digital data - Google Patents

Clock derivation circuit for double frequency encoded serial digital data

Info

Publication number
DE3071038D1
DE3071038D1 DE8080902255T DE3071038T DE3071038D1 DE 3071038 D1 DE3071038 D1 DE 3071038D1 DE 8080902255 T DE8080902255 T DE 8080902255T DE 3071038 T DE3071038 T DE 3071038T DE 3071038 D1 DE3071038 D1 DE 3071038D1
Authority
DE
Germany
Prior art keywords
digital data
double frequency
serial digital
frequency encoded
derivation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080902255T
Other languages
English (en)
Inventor
Thomas Ralph Woodward
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Application granted granted Critical
Publication of DE3071038D1 publication Critical patent/DE3071038D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
DE8080902255T 1979-10-19 1980-10-14 Clock derivation circuit for double frequency encoded serial digital data Expired DE3071038D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/086,268 US4313206A (en) 1979-10-19 1979-10-19 Clock derivation circuit for double frequency encoded serial digital data
PCT/US1980/001360 WO1981001225A1 (en) 1979-10-19 1980-10-14 Clock derivation circuit for double frequency encoded serial digital data

Publications (1)

Publication Number Publication Date
DE3071038D1 true DE3071038D1 (en) 1985-10-03

Family

ID=22197420

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080902255T Expired DE3071038D1 (en) 1979-10-19 1980-10-14 Clock derivation circuit for double frequency encoded serial digital data

Country Status (5)

Country Link
US (1) US4313206A (de)
EP (1) EP0044311B1 (de)
JP (1) JPH0157854B2 (de)
DE (1) DE3071038D1 (de)
WO (1) WO1981001225A1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320525A (en) * 1979-10-29 1982-03-16 Burroughs Corporation Self synchronizing clock derivation circuit for double frequency encoded digital data
US4355398A (en) * 1980-12-17 1982-10-19 Ncr Corporation Real time clock recovery circuit
US4379265A (en) * 1981-05-26 1983-04-05 Burroughs Corporation Dual clocking time delay generation circuit
DE3311677A1 (de) * 1983-03-30 1984-10-04 Siemens AG, 1000 Berlin und 8000 München Vorrichtung zur rueckgewinnung eines taktes aus einer signalfolge
US4567604A (en) * 1983-08-29 1986-01-28 At&T Teletype Corporation Biphase signal receiver
JPS60145745A (ja) * 1984-01-09 1985-08-01 Nec Corp バイフェーズ符号クロック抽出回路
NL8401629A (nl) * 1984-05-22 1985-12-16 Philips Nv Elektrische schakeling met een faseregelkring.
US4805197A (en) * 1986-12-18 1989-02-14 Lecroy Corporation Method and apparatus for recovering clock information from a received digital signal and for synchronizing that signal
US4864588A (en) * 1987-02-11 1989-09-05 Hillier Technologies Limited Partnership Remote control system, components and methods
US4851995A (en) * 1987-06-19 1989-07-25 International Business Machines Corporation Programmable variable-cycle clock circuit for skew-tolerant array processor architecture
US4809301A (en) * 1987-11-25 1989-02-28 The United States Of America As Represented By The Secretary Of The Air Force Detection apparatus for bi-phase signals
US4868569A (en) * 1987-12-15 1989-09-19 Schlumberger Well Services Biphase digital look-ahead demodulating method and apparatus
GB8804811D0 (en) * 1988-03-01 1988-03-30 Shaye Communications Ltd Waveform encoder/decoder
JPH02107035A (ja) * 1988-10-17 1990-04-19 Omron Tateisi Electron Co 符号化パルスのタイミング再生方式
US5023891A (en) * 1989-07-25 1991-06-11 Sf2 Corporation Method and circuit for decoding a Manchester code signal
US4992790A (en) * 1989-09-19 1991-02-12 Schlumberger Technology Corporation Digital phase-locked loop biphase demodulating method and apparatus
US5162791A (en) * 1989-10-02 1992-11-10 Codenoll Technology Corporation Collision detection using code rule violations of the manchester code
US5524109A (en) * 1991-06-20 1996-06-04 Bay Networks, Incorporated Token ring concentrator having retiming function
DE10121855A1 (de) * 2001-05-04 2003-02-13 Atmel Germany Gmbh Verfahren zur Übertragung von Daten
TWI257482B (en) * 2004-12-15 2006-07-01 Spirox Corp Method and apparatus for measuring jitter of signal

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3271750A (en) * 1962-12-13 1966-09-06 Ibm Binary data detecting system
US3271742A (en) * 1963-11-06 1966-09-06 Ibm Demodulation system
US3405391A (en) * 1964-12-21 1968-10-08 Ibm Double frequency detection system
US3480869A (en) * 1966-12-27 1969-11-25 Bell Telephone Labor Inc Timing recovery circuit for use in frequency-modulated,differentially coherent phase modulation (fm-dpm) communication system
US3611158A (en) * 1969-11-12 1971-10-05 Collins Radio Co Signal pulse trigger-gating edge jitter rejection circuit
US4010323A (en) * 1975-10-29 1977-03-01 Bell Telephone Laboratories, Incorporated Digital timing recovery
US4019149A (en) * 1976-01-16 1977-04-19 Bell Telephone Laboratories, Incorporated Correlative data demodulator
US4185273A (en) * 1977-07-27 1980-01-22 The United States Of America As Represented By The Secretary Of The Navy Data rate adaptive control device for Manchester code decoders
US4234897A (en) * 1978-10-05 1980-11-18 Ampex Corporation DC Free encoding for data transmission

Also Published As

Publication number Publication date
EP0044311B1 (de) 1985-08-28
WO1981001225A1 (en) 1981-04-30
EP0044311A4 (de) 1982-04-29
JPH0157854B2 (de) 1989-12-07
JPS56501469A (de) 1981-10-08
US4313206A (en) 1982-01-26
EP0044311A1 (de) 1982-01-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee