DE3003009C2 - Logical circuit for the implementation of logic functions - Google Patents

Description

The invention relates to a logic circuit according to the preamble of claim 1.

In circuit technology, it is possible to perform any given switching function through suitable interconnection of basic switching elements. You always come up with a finite amount of Gates which, due to their internal electrical properties, are capable of the function of a base to realize the switching functions. Bases are e.g. B. (AND, OR, NOT), (EXOR, AND), (NAND) or (NOR). Realizations of this kind are, however, logical unless they relate to a basic function multi-stage, that means that a signal from the input to to the output of the circuit several gates, which are internally composed of several electronic switching stages must go through.

With such realizations dynamic hazards, wrong reactions of the output to change one or more input values, occur as it

from Giloi-Liebig, "Logical Design of Digital Systems", Springer-Verlag, Berlin, 1973, is known

This disadvantage can be avoided by switching elements that are able to handle as many as possible different functions logically single-stage without significantly increased switching effort, that is as a single gate. The selection of the functions can be done by additional programmable Inputs, which is unfavorable with regard to the implementation of the module in integrated technology, by burning out bridges in PLAs, as described by Timm, "In the spotlight on ROMs, PROMs and PLAs", Electronics special issue microprocessors, pages 17 to 27, Franzis-Verlag, Munich, 1977, or by special assignment of the logical inputs with Switching variables or possibly constants happen.

The latter is by far the cheapest alternative as it is flexible in terms of changes in the circuit design and is favorable in terms of the ratio of the number of function variables to the total number of inputs.

The circuit should be compatible with TTL gates, i.e. input signals in positive logic (logic "0" corresponds to OW = UBO, logic "1" corresponds to 3.5-7 V = + i / ß ^ and output signals of the same kind hand over.

Is known a logic combination circuit according to the preamble of claim 1 with a Number of binary signal inputs and at least one binary signal output (DE-OS 19 12 438) in the case of Switching elements signal paths connected to the inputs are summarized to at least a first node that depends on the binary input signals can assume more than two stable potential states while next to it at least one further node is formed by combining other signal paths, which assume at least two stable potential states as a function of the binary input signals can, and in addition, the nodes are connected to switching elements that respond to the potential difference respond between the nodes and / or a fixed reference potential and binary output signals deliver.

It is a logic combination circuit to which binary input signals are fed and which also provides binary output signals, but has the advantage of being used within the circuit of a number system with a base greater than 2.

In such a circuit arrangement, the processing of the signals is within the logic Circuit not tied to the limitations of the binary number system when using it each connecting line and each switching element within the logic circuit only one of two possible signal potentials can be transmitted. The elements of the logic combination circuit are thereby used to a higher degree than is the case with a purely binary logic operation.

The well-known logic combination circuit leads to the existence of multi-valued signals between the Output of the input stage (s) and the input of the processing stage (s), said connections being direct are connected. However, it has a first junction of input signal paths that is more than is two-valued, and in addition at least one further node of input signal paths, the is also more than two-valued and not identical to the first node. The nodes are with Switching elements connected to the potential difference between the nodes and / or a address fixed reference potential and generate binary output values.

With such a logical combination circuit, different switching functions can only go through a case-by-case interconnection of basic components, there called »current switches«, can be implemented, however, this changes the circuits for various switching functions.

Another known logic circuit (US-PS 36 02 733) is a circuit of the so-called tri-state logic, in which an output line has the following three states can: "coupled and logically true", "coupled and logically false", "decoupled". The state "Uncoupled" is achieved by the fact that the output

_> (i is made high-impedance so that it appears to other circuits whose inputs are connected to the line to which the output and possibly outputs of other circuits provided with this device are also connected, as if the circuit in question was

2) does not exist at all. This is advantageous in bus systems. The whole point is that such circuits are connected without hesitation with regard to their outputs without disturbing each other, which is not possible with normal circuits.

ίο Another known circuit (US-PS 40 05 315) relates to a processing amplifier in the form of a binary-ternary converter. The way it works is that the ternary input value calculates its equivalent in two-digit binary place value coding

r> will.

Another known circuit (US Pat. No. 4,163,907), the hybrid of gates and discrete ones, also works Components is assembled.

In another known circuit (US-PS

to 38 32 576), in order to save signal inputs, a three-valued input signal is split in such a way that in one case a bipolar, in the other case an IG field effect transistor, in the third case none of both is switched. It can do so with one

• r> input line two different autonomous circuits operate. The circuit therefore only takes a distribution of the incoming on the input line Signals before, but not a defined processing. In particular, the one output line is not

"ii> the logical complement of the other line.

In another known logic combination circuit (DE-OS 27 55 297) only two three-valued inputs linked to two complementary binary logical outputs.

j "> The invention is based on the problem of logical train single-stage universal switching elements in such a way that the selection of the functions is based on the assignment of the functional inputs happens and that a single switching element as many different switching functions as possible

expectations can logically realize one-step.

This object is achieved by the characterizing part of claim 1.

In order to use the invention 74 different switching functions., 1 of up to four variables logically in one step

tv> can use the four inputs differently Variables, negated variables or constants are assigned by the lines, their status in each case is described by the variable or constant,

be connected to one or more inputs of the invention, so that depending on the Assignment of the inputs with switching variables, which are represented by electrical potentials, the named 74 different switching functions of up to four switching variables, among them all 16 of two variables, can be obtained logically in one step.

Particularly advantageous developments of the invention are characterized in claims 2 to 5. An RS flip-flop can be implemented by feeding back the inverse output to one of the inputs by connecting the inverted output (Q) to the input (F1) and a line corresponding to the constant »1« to the input (£ 4) that input (£ 2) is the SET input and input (£ 3) is the RESET input.

In order to be able to realize even more different switching functions with the invention, two further npn transistors and two resistors with the value of the resistor (R 7) are added to the input stage in such a way that one of the two further transistors is connected like the transistor (7 * 1) and the other like transistor (7 * 3), with which the circuit has six inputs and logically realizes around 250 different switching functions in one step, including all of two variables and 106 of three variables.

In order to be able to implement even further switching functions with the invention, the logic circuit according to claim 4 in the manner described above by two inputs with two further transistors and two more resistors are expanded, taking the entire resistances of the input stage may not exceed a tolerance of 2%.

In claim 5 is a particularly simple and advantageous series stabilization for decoupling the Input stage marked by tolerant voltage sources in the circuit.

The advantages that can be achieved with the invention are, in particular, that instead of a large number of different logic switching elements in several logic levels and one with different costs Interconnection of the switching elements with one another a uniform, single, logically single-stage universal Switching element can be used for many different functions, with only one change the input assignment is required. The special input assignments can be found on boards or calculated according to a mathematical method.

An embodiment of the invention is explained in more detail below with reference to the drawing shows

F i g. 1 shows a circuit diagram of a logic circuit according to a preferred embodiment of the invention,

F i g. 2 examples of the notation of the switching functions of the logic circuit using natural numbers,

F i g. 3 the assignments for the realization of all two-digit Switching functions using the embodiment of Fig. 1,

Fig. 4 the assignments for the realization of some three-digit switching functions using the embodiment from F i g. 1 and

Fig. 5 the assignments for the realization of some four-digit switching functions using the embodiment of FIG. 1.

The in F i g. 1 logic circuit shown consists of an input stage 1 with four inputs Ei, E2, E3, £ 4 and a processing amplifier 2 with two outputs Q and Q. The processing amplifier 2 is connected to the input stage 1 by a line A and is not by a The voltage source shown is supplied with the voltages + UB, UBO and - UB , with the voltages + UB and - UB each having the same amount with respect to the symmetrical ground UBO; it is therefore a symmetrical voltage

I «supply.

The input stage 1 has four npn transistors Ti, Tl, TZ, T4 of the type BC 109, which are connected in pairs with respect to the supply voltage + UB, UBO, -UB in such a way that two transistors Ti, T2 of the input stage 1 with their Collectors are connected to the positive pole + UB of the voltage source via a collector current limiting resistor RH and their emitters are connected to line A via the same resistors R 7, R 8

2 »are connected, while the other transistors 7 * 3, 7'4 of the input stage 1 each have the same resistors R 9, R 10 with their collectors on the line A and their emitter via an emitter current limiting resistor R 12 directly to the negative pole - UB of the voltage source are connected, so that they realize the logical link by means of difference formation as a function of positive input signals at their base connections, provided that the voltage source represents a symmetrical voltage supply, and

so feed the processing amplifier 2 via line A.

The transistors Ti, T2 are connected to the inputs Ei, £ 2 via base series resistors Al, R2 , while the transistors 7 * 3, 7 * 4 base voltage divider current limiters with resistors R 3, R 5 or R 4, R 6 are connected upstream. The resistors Al, R2, R3, R 4 have a resistance of 4700 ohms and the resistors R 5, R 6 have a resistance of 2200 ohms, while the resistors Ä7, RS, R9, RiO have one

-to resistance value of 10 000 ohms and resistors R 11, R 12 have such a value of 470 ohms.

The processing amplifier 2 essentially consists of five diodes D 1, D 2, D 3, D 4, D 5 of type 1 N 914 as well as two npn transistors T 5, TS of type BC 109 and two pnp transistors T6, Tl Type BC 179. The line A, which forms the input of the processing amplifier 2, is connected directly to the base connection of the pnp transistor 7 * 6 and via the decoupling diode Di to the base of the npn transistor TS , the base connections of the transistors T5, 7 * 6 via resistors R 13, R 14 with a resistance value of 20,000 Ohm brw. ! 00 000 Ohm with the positive Pn! + UB of the voltage source are respectively connected to the balanced mass UBO and the emitter of the transistor T5, as well as the collector of the transistor TS having the symmetrical ground LiBO The collector of the transistor T5 is connected via a load resistor RiS having a resistance value of 1000 ohms the positive pole + UB of the voltage source and via the diode D 2 to the base of pnp-transistor 7, which is connected as a reinforcing inverter and the emitter of the output Q constitutes the npn transistor 7 * 5 is also connected via a further diode D 3 connected to the base of the npn transistor 7 * 8 also held as an inverter, the collector connection of which forms the output Q , while the emitter of the transistor 7 * 6 via the diodes D 4, D 5 also to the base connections of the as

Inverter-connected transistors T7, TS is connected, with a resistor RX7 of 22,000 ohms arranged between the base of the transistor 7 * 7 and the negative pole - UB of the voltage source and a series resistor R 18 of> 10,000 ohms connected upstream of the transistor TS is. Both transistors T7 and Γ8 are connected to the positive pole + UB of the voltage source through load resistances R 19 and R 20 of 470 ohms each, once at the emitter at transistor 7 and at the collector at transistor 8. \ u

Between the input stage 1 and the processing amplifier 2 there is a series stabilization 3, which is used to decouple the input stage 1 from tolerant voltage sources in the circuit. It consists of two Zener diodes Zl, Z 2 with a reverse voltage π of 3.3 volts each, of which one Zener diode Zl with the cathode with the positive pole + UB of the voltage source via the collector current limiting resistor RW of the transistors 7 * 1, T2 of the input stage 1, which are connected to the voltage + UB , and the anode is connected to the symmetrical ground UBO , while the other Zener diode Z2 is connected to the cathode with the symmetrical ground UBO and with the anode via the emitter current limiting resistor R 12 of the transistors Γ3, 7 "4 of the input stage 1, which are connected to the negative pole - UB of the voltage source, is connected to the negative pole - UB .

The logic circuit described above works as follows, whereby the following can apply as an example for the voltages: + UB = + 5V, i / S0 = 0V, - UB = -5V. Furthermore, + UB corresponds to the logical “!” Potential, UBO to the logical “0” potential, which means that if + UB is selected accordingly, compatibility with the usual logic circuits is established. J5

In this embodiment, the stabilizers R 11, Z1 and Z2, R 12 are used for the precise adjustment of the input stage 1 in the event of voltage fluctuations.

The function of input stage 1 can be characterized as follows: Two different signals can appear at the inputs El, £ 2, £ 3 and £ 4, namely a voltage close to UBO, which represents a logical "0", and a voltage close to + UB, which logically represents "1".

If a voltage close to UBO occurs at input £ 1, transistor Ti does not switch through, so that if no other transistor 7 "2, Γ3 or Γ4 switches through, no current can flow via line or point A. If input E occurs 1, however, a voltage close to -1- UB , then the transistor 7 * 1 switches through and the line A is placed close to + UB via the resistor R 7 .

A «^ #» I ^^ rv η «« η ^ %% ♦ ^^ 4 ^^ ^% f 1 ^ O finf ΤΛΙ * M r VtIl T β I ^^ V ^ ^^ t ^ ΤΡηΙΆΑηΑη r-tliailSg αϊ LTWIll-l UVI IIUIMIJIVI μ bltlllUbllvll ^ lVkllUI- the voltages at the input £ 2.

If there is a voltage close to UBO at input £ 3, it is influenced by the strong base voltage divider current limiter Ri, R5 in such a way that transistor T3 does not turn on and thus no current flows via line or point A if all other transistors of the input stage 1 also lock, however, a voltage close to + UB is present at the input £ 3, to the transistor Ti turns on, so that through the resistor R9, the line or point a to a potential near - is placed UB. The transistor T4 works analogously with the corresponding voltages at input £ 4.

The cases in which several transistors of input stage 1 switch through at the same time.

If the transistors 7 "1 and T2 are turned on , but the transistors T3 and Γ4 are not, then there is a positive voltage across the resistors Rl and R 8 at point A. If the transistors 7 ~ 3 and T4 are turned on , transistor Ti and transistor 7" 2 but not, point A is connected to the negative pole - UB of the voltage source via the resistors R 10 and /? 9.

If the transistors TX and Γ3 and the transistors 7 ~ 2 and TA do not switch, the resistors R 7 and R 9 form a 1:! Voltage divider for the voltage between + UB and - UB, so that point A has the potential accordingly UBO is brought because, by definition, UBO lies exactly in the middle between + L / Bund - UB (symmetrical power supply)

The same happens when transistors TX and 7 "4 conduct and transistors Γ2 and Γ3 do not conduct or transistors T2 and Γ3 conduct but transistor Π and transistor Γ4 do not conduct or transistors T2 and 7" 4 conduct, transistor TX and transistor Ti but not.

If the transistors 7 "I, T2 and Ti are now conducting, while the transistor Γ4 is not conducting, the resistors R7 parallel to the resistor RS in series with the resistor R 9 form a 1: 2 voltage divider, so that at point A a voltage divider is positive compared to UBO The circuit is analogous if the transistors TX, T2 and Γ4 conduct, but the transistor Ti does not conduct.

Guide, however, the transistors Ti, Ti and Γ4, the resistors R XO form parallel to the resistor / 9 in series with the resistor R7 a 2:? -Spannungsteiler, so that at the point A an oppositely UBO negative voltage is produced, provided that transistor T2 does not directs. The same happens when transistors T2, Ti and Γ4 conduct, but transistor TX does not.

If all the transistors of the input stage 1 conduct, the resistors R 7 parallel to the resistor RS in series with the resistor R 9 parallel to the resistor R 10 again form a 1: 1 voltage divider, so that UBO is present at point A.

Based on FIG. 1 should now also be the mode of operation of the processing amplifier 2 will be explained. There are the following functional demands on him posed:

1.If there is a signal on line A, which represents the input of processing amplifier 2 and at the same time the output of input stage 1 and was also referred to as point A in this context, a signal that differs only slightly from UBQ (L'50 ± 0 , 3 V), output Q should assume a potential close to UBO (corresponding to logic “0”) and output Q a potential close to + UB (corresponding to logic “1”);

2. If there is a potential positive to UB 0 + 0.3 V on line A , output Q should adopt a protocol close to + UB , while output Q should have a potential close to UBO ;

3. If line A has a negative potential of 0-03 V compared to UB , outputs Q and Q should have potentials as under 2.. From a mathematical point of view, the processing amplifier 2 carries out a normalization of the type <? = Sign A if only exact equality with UB 0 is permitted under 1. instead of the slight distinction to be made due to component tolerances.

ίο

In the first case, the transistor T5 is switched through via the base resistor R 13, since no significant voltage drop occurs at the base of the transistor T5 via the diode D 1 and the resistor R 14. The switched-through transistor Γ5 thus applies a potential close to UBO to the anodes of the diodes D2 and D 3. The diode D 2 does not allow enough current to pass that the potential at the base of the transistor Tl rises significantly above UBO , since the resistor R 17 biases the transistor Tl negatively. The transistor 7 thus conducts, so that the output Q receives a potential close to UBO. The diode D 3 also does not conduct, whereby the transistor 7 "8 blocks, which has the consequence that the output Q is connected to the positive pole + UB of the voltage source via the load resistor /? 20 and thus, since there is no significant voltage drop, is at a corresponding logical "1" potential. The transistor 7 "6 is connected to the symmetrical ground UBO via the resistor R 14 and conducts, since the diode D 1 has a decoupling effect. Thus, there is at the anodes of the diodes D 4 and D 5 3 so that they do not conduct a voltage close UBO ₁ similar to the diodes D 2 and D and changes the gating behavior of the transistors Tl and Γ8 nothing.

In the second case (with respect to LJBO + OJ V positive potential on line A) nothing changes in the behavior of transistor T5 , since diode D 1 is switched in the reverse direction in this case. For this, a positive potential arises at the base of the transistor 7 "6, which blocks the transistor. As a result, the anodes of the diodes D 4 and D 5 are connected to the positive pole + UB of the voltage source via the resistor R 16, so that the diodes conduct As a result, a potential positive with respect to UBO arises at the base of transistor Tl (voltage divider R 16, R 17), which is why transistor Tl blocks. As a result, output Q is connected to + UB via load resistor R 19 and leads a potential corresponding to logic "1." Via the diode D 5 and the series resistor R 18, a positive potential is also carried to the base of the transistor TS , which is connected as an inverter , so that it conducts, whereby the output Q receives a potential close to UBO.

In the third case (negative potential compared to UB 0-0.3 V at point A) , the transistor T5 is blocked because its base potential drops because the diode DX is now switched in the forward direction, which means that the diodes D 2 and D 3 get a positive potential close to + UB at their anodes via the resistor R 15 and conduct them. By conducting the diode D 2, the transistor Tl is blocked, since it now has a positive voltage at its base compared to the symmetrical ground UBO , whereby the output ζ) via the load resistor R 19 + UB accordingly leads to a logical "1". By conducting the diode D 3 , the transistor 7 "8, which is connected as an inverter, is opened via the series resistor R 18, so that it connects the output Q with the symmetrical ground UBO according to a logical" 0 ". A negative voltage at point A becomes the Transistor Γ6 blocked, so that diodes D4 and D5 do not conduct and thus no influence on the behavior of transistors 7 "7 and TS is exerted by transistor 7" 6.

The possible assignments of the inputs E1 to E4 for the implementation of switching functions can be found in the tables of FIGS. Each function is represented by that natural number, the binary representation of which is the function sequence in a value table of the input variables. A switching function of η variables is defined over all 2 "possible value combinations of the η input variables. Since the function can take the values 0 or 1 at any point, depending on how it is defined, there are 2 ² " different switching functions from /; Variables. Every function can therefore be uniquely characterized by a Α-ε {0,1 2 ² "- 1), where

/ Il

with

./'(.ν v ") for

Σ-

Otherwise undefined

where * i, X2, ... x _{n are} the η variables and / "their function . Examples of assignments: (functions of two 4) variables)

■ V | .Vi ./■ 2- " ' ■ i θ Jt: 0 ■ 8 OR j A: 0 · 8th NOR A: A: ■ 8 EXOR ΝΛΝΙ) A: 1 -I- ■ 8 0 0 0 8th 0 j-j • -1 0 +! · ,1 1 ■ 4 1 + 1 • 4 0 1 1 4th 1 + 1 • 2 1 + '■ 2 () ι A
ι \ J • 2 1 +0 • 2 1 0 2 2 1 +0 ■ 1 1 H-1 - 1 (i +0 • 1 1 • 1 1 1 3 1 0 6th ] 7th 0 +0 8th 0 14th Variables: A: Examples for functions three AND, -V ₁ j 3 Xj

0 0 0 0 128 0 0- Ι 28 0 0- 128 0 0 1 1 64 0 + 0- 64 1 +1 - 64 0 1 0 2 32 0 +0 ■ 32 1 +1 - 32 0 1 I. 3 16 0 + 0- 16 0 + 0- 16 1 0 0 4th 8th 0 + Ο 8th 1 +1 ■

Il

12th

■> "ι /

AND. i: \ ok-,

1 5 4th 0 +0 4th 0 +0 ■ 4th 0 6th 2 0 +0 2 0 +0 ■ 2 1 7th 1 1 + 1 1 I. + 1 1

1 105

Conversely, the number A of the l-'uiiction according to the method of converting de / imalen / or in binary numbers the value sequence of this function can be obtained.

Examples:

A 21 ')

IU-s IU-M:

219-128

91-64

27-32

27-16

11-8

3-4

3-2

1-1

91

27

= 0

With this very space-saving coding, the logical 0-1 value of a variable or function is often equated to an arithmetic value. However, this is not harmful as it is the equation is an isomorphism.

The switching element realizes an RS flip-flop element in that E 1 with Q, E2 with 5, the SET pulse, E 3 with R, the RESET pulse, and EA with the constant log. "1" must be assigned.

Even more different switching functions can be realized with the invention by adding two further npn transistors and two resistors to the input stage 1 in such a way that one transistor is connected like transistor 7 "1 and the other like transistor TX, thus circuit six Has inputs and implemented around 250 different switching functions logically in one stage, including all of two variables and 106 of three variables.

In order to be able to realize even further switching functions with the invention, the circuit in the above described way by two more inputs., whereby the tolerance of the resistors in the input stage May not exceed 2%.

List of reference symbols and type designations / u F i g. 1

transistor 7Ί = BC 109 transistor Tl = BC 109 transistor T3 = BC 109 transistor Γ4 = BC 109 transistor Γ5 = BC 109 transistor T6 = BC 179

1 Zl 97-128 ohm <(J I. Zl 97-64 ohm 33 0 Ri 33-32 ohm 1 1 R2 '-16 ohm <Ü 1 Ri 1-8 ohm <ü 0 A4 1-4 ohm <0 1 RS 1-2 ohm <0 1 /? 6 1-1 ohm = 0 Transistor > Rl - BC 179 ohm RH BC 109 ohm R9 = 1 N 914 ohm R \ Q = 1 N 914 ohm RIl - i N 914 ohm RIl = 1 N 914 ohm R 13 - 1 N 914 ohm RU = 3.3 volts ohm Λ 15 = 3.3 full ohm ^r 7 R 16 = 4 700 ohm Transistor 78 Marg = 4 700 ohm Diode /) I RlS = 4 700 ohm Diode Dl Λ 19 = 4 700 10% Diode /) 3 Λ 20 = 2,200 Diode /) 4 Resistors R 1 = 2,200 Diode 1) 5 = 10,000 / enerdiode = 10,000 / enerdiode = 10,000 resistance = 10,000 resistance 470 resistance 470 Contradiction = 20,000 resistance = 100,000 resistance 1000 resistance = 2,200 resistance = 22,000 resistance = 10000 resistance 470 resistance 470 resistance ... R 20: resistance resistance resistance resistance resistance resistance resistance resistance

For this purpose 3 sheets of drawings

Claims (5)

Patent claims: 1.Logical circuit for the implementation of logic functions with a logic switching element with a number of binary signal inputs and two binary signal outputs, consisting of an input stage with transistors and a processing amplifier with transistors, in which the input stage supplies a signal on a line that is dependent on the binary input signals can assume two or more different stable potential states, and the line is connected to the input of the processing amplifier, which generates the two binary output signals, characterized in that there are at least four binary signal inputs that the transistors (Ti, T2, T 3 , Γ4) of the input stage (1) in pairs with respect to the supply voltage (+ UB, UBO, - UB) are connected in series in such a way that two transistors (TM, T2) of the input stage (1) are connected with their collectors via a current limiting resistor (R 11) to the positive pole (+ UB) of the voltage source and their emitters are connected to the line (A) via the same resistors (R7, /? 8), while two further transistors (Γ3, Γ 4) of the input stage (1) via the same resistors (R9, RiO) with their collectors on the line (fly and with their emitter via a current limiting resistor (/? 12) directly to the negative pole (-UB ) are connected to the voltage source, so that they realize the logical link by means of difference formation depending on positive input signals at their base connections, provided that the voltage source represents a symmetrical voltage supply that the line (/ ^ directly with the base connection of a first pnp transistor (7 " 6) of the processing amplifier (2) and via a decoupling diode (Dl) to the base of a second npn transistor (Γ5) of the processing amplifier (2), the base connections of these transistors (75, 7 "6) being connected to the positive pole (+ UB) of the voltage source or the symmetrical ground (UBO) and the emitter via resistors (R 13, R 14) of the second transistor (Γ5) as well as the collector of the first transistor (Γ6) is connected to the symmetrical ground (CSO) and the collector of the second transistor (7 "5) via a load resistor (R 15) to the positive pole (+ UB ) and via a diode (D 2) to the base of a third pnp transistor (Tl), which is connected as an amplifying inverter and forms the output (Q) at the emitter, and via a further diode (D3) to the base of a likewise fourth npn transistor (TS) connected as an inverter, the collector connection of which forms the output (Q) , while the emitter of the first transistor (7 ~ 6) also connects to the base connections of the third and fourth transistors connected as an inverter via diodes (D4, D5) (TT, Γ8) is connected so that the processing Signal amplifier on line (A) , which can be positive or negative with respect to the symmetrical ground (UBO) , amplified and, if they are negative, also converted and thus generates a normalized signal for the logic state at output (Q), while the inverse signal is provided at output (Q). 2. Logic circuit according to claim 1, characterized in that by feedback of the inverse output (Q) to one of the inputs (E 1, E2, E3, £ 4) realized an RS flip-flop by the inverted output (Q) with the Input (Ei) and a line corresponding to the constant "1" is connected to input (E4) in such a way that input (E2) is the SET input and input (E3) is the RESET input 3. Logic circuit according to claim 1, characterized in that two further npn transistors and two further resistors with the value of the resistor (R7) in the input stage (1) are arranged in such a way that one of the two further npn transistors is connected is like transistor (Ti) and the other like transistor (T3), so that the circuit has six inputs (£ 1, ... ES) 4. Logic circuit according to claim 3, characterized in that the input stage (1) is expanded by two further transistors and two further resistors, the entire resistances of the input stage (1) except for the base series resistors (Ri, R2, R3 .. .) may only have a tolerance of max. 2% so that the circuit has eight inputs (El, ... £ T8). 5. Logic circuit according to claim 1 to 4, characterized in that for the purpose of decoupling the input stage (1) from tolerant voltage sources in the circuit, a simple series stabilization (3) consisting of two Zener diodes (Zl, Z2), one of which (Zl) is connected to the cathode with the positive pole (+ UB) de.v voltage source via the collector current limiting resistor (RH) of the transistors (7 "I, Γ2) of the input stage (1), which are connected to the positive pole (+ UB) and is connected to the anode to the symmetrical ground (UBO) , while the other Zener diode (Z2) is connected to the cathode to the symmetrical ground (UBO) and to the anode via the emitter current limiting resistor (R 12) of the transistors (7'3 , TA) of the input stage (1), which are connected to the negative pole (- UB) of the voltage source, is connected to the negative pole (- Cß ^, is present.