DE2952513A1 - Semiconductor memory - consisting of static induction transistor and superimposed capacitor - Google Patents

Abstract

A semiconductor memory consists of a source zone, a drain zone, and a channel zone to provide a path for the charge carriers. A gate structure surrounds the channel zone in a sandwich fashion. A capacitor has one plate in contact with the drain zone which it overlaps, with an insulating layer sepg. the other plate. Such a semiconductor memory has a greater storage capacity and packing density for compatibility purposes.

Description

Semiconductor memory device

The invention relates to a semiconductor memory, namely particularly to an improvement in the information storage capacitor disclosed in the memory cell structure is arranged with a static induction transistor is constructed.

A semiconductor memory formed using the static Induction type transistor is already known per se. Such a semiconductor memory device is described, for example, in the following magazine: zNikkei Electronics ", 1977, September 19 edition, pp. 38-41. An example of such a semiconductor memory device is described in DE-OS 28 07 181. According to this DE-OS, a semiconductor device formed in a semiconductor body and has at least one memory cell, made up of a source zone for the delivery and removal of load carriers is, wherein a storage zone and a channel zone are also provided are, which latter connects the source region and the memory region, and where further the channel zone builds up a potential barrier for the charge carriers and the source-channel and memory zones are arranged in the semiconductor body, the potential barrier is controlled by at least the voltage applied to the source zone and the source and memory regions substantially perpendicular to the surface of the Semiconductor body are arranged. A gate structure is also in the vicinity of the Channel zone arranged.

A conventional semiconductor memory arrangement constructed with memory cells of this type has a semiconductor body, a plurality of bit lines and a plurality of word lines as well as a plurality of semiconductor memory cells of those described above Type of construction at the desired crossing points of the bit lines and word lines are arranged.

In this known semiconductor memory cell structure, however, there is one of the electrodes of the information storage capacitor, which is at the drain zone the cell structure is arranged from the semiconductor of this drain zone per se. Accordingly, there is some disadvantage as the capacitance of the capacitor is bounded in an unavoidable manner by the area of the drain zone itself. The area of the drain zone of such a cell essentially corresponds to the cross-sectional area the canal zone.

A memory cell must have as small a surface area as possible have to improve the utilization efficiency and also the packing density of the semiconductor chip to increase.

Applying this requirement to the known Semiconductor memory cell devices Of course, the drain zone within the memory cell becomes very small or narrow, because of those required for intercellular isolation and for the gate zones Areas. As a result, the storage capacity of the capacitor decreases, which is a Deterioration in the storage characteristics of the memory cell and also a decrease the logical amplitude of the information read out. This leads to Necessity of providing a highly sensitive peripheral circuit and increases the complexity of the arrangement as well as the manufacturing costs.

Summary of the invention: The invention is therefore an object set out an improved semiconductor memory device using a static Induct induction type transistor, the above-mentioned disadvantages of the known Memory cells are avoided, and with an increase in storage capacity as well as the packing density for compatibility purposes is achieved.

Another object of the invention is to provide a semiconductor memory device of the type described above, the arrangement being made in such a way that that one of the electrodes of the capacitor, which are arranged on the drain zone and which are formed with conductive layers an area larger than that of the drain region owns. Another object of the invention is to provide a semiconductor memory device of the type described above to provide that an improvement in terms of Packing density is achieved by reducing the size of the drain region, namely by reducing the cell size accordingly, without reducing the charge carrier storage capacity of the capacitor this memory is deteriorated.

Further advantages, objects and details of the invention result in particular from the claims and from the description of exemplary embodiments based on the drawings; In the drawings: Fig. 1 shows a partially sectioned schematic plan view of a semiconductor memory cell arrangement using a static induction type transistor for constructing each memory cell, wherein an embodiment of the invention is shown here; Fig. 2 is an illustrative Section of a part of the memory cell arrangement corresponding to a single memory cell structure, the section was made along line II-II in FIG. 1; Fig. 3 is an equivalent Circuit of the memory cell structure shown in FIG.

It is now a preferred embodiment of the invention in individually described.

It is known that when a semiconductor body with a certain Impurity concentration (the term "semiconductor" includes an insulator in its usual sense) is brought into contact with another body from a different one Substance of the same material, but with a different concentration of impurities, or if the contact with the surrounding atmosphere takes place, so becomes caused a difference in contact potential, which is a potential barrier for which forms electrons or holes.

According to the prior art mentioned above, a charge carrier or an information storage cell, defined by such a potential barrier, is formed in a semiconductor body, and charge carriers are in this memory cell is put in or taken out of it so as to carry out the storage operation.

The term memory operation here includes writing, storing and readout. The zone for delivery and recovery of load carriers will be called the source zone. Between the source zone and the storage zone is a Potential barrier built up, at least a part of which through a semiconductor zone is formed with the same conductivity type as that of the source zone, but with a low concentration of impurities, or the formation takes place through a semiconductor zone with a conductivity type opposite to that of the source zone, but essentially in the "pinch-off" mode, which increases the efficiency and the speed of carrier transport is increased. Furthermore, the storage zone and the source zone is arranged substantially perpendicular to the semiconductor surface to be an improvement in terms of operating speed, integration density and storage efficiency. Regardless of this potential barrier forming semiconductor zone type is the height of the potential barrier through the to the Storage zone or the source zone applied voltage lowered to the charge carriers to cause the potential barrier to be slightly exceeded.

Fig. 1 shows schematically in plan view the memory cell arrangement, formed with memory cells, each with a static induction transistor (in the hereinafter referred to as SIT for short) according to an exemplary embodiment of the invention is constructed. The basic concept of the invention is to provide a To use SIT structure to build a memory cell. As in detail in the DE-OS mentioned at the outset describe a SIT of such a type that the parasitic Gate (source-gate and gate-drain) capacitance is very small that the gate zone resistance can be very low that the charge carriers by an electric field of a Drift movement are subjected, and that the space charge storage effect is very small is. There are thus numerous areas of application where such an SIT can be used can. It should also be noted that regardless of the type of the potential barrier forming semiconductor zone, the height of the potential barrier is lowered by the voltage which is applied to the storage zone or the source zone, around the charge carriers to induce to easily go over the potential barrier, as shown in the introduction mentioned DE-OS is described.

The SIT has an extremely high potential for increasing the integration density and the speed of operation compared with conventional transistors. In the case of using the vertical type structure, what is more detailed with reference is described on the embodiment, the carrier transport takes place essentially in the bulk of a semiconductor body. Thus, the operation speed can due to the great mobility of the masses. In particular, it can be in the SIT structure a potential barrier is formed in the current path between the source and the drain will.

In Fig. 2 is a schematically explanatory section of a memory arrangement using a SIT shown in FIG. 1, namely the cutting line along line II-II.

In FIGS. 1 and 2, the reference numeral 10 generally denotes a semiconductor chip, made of silicon, called. On top of a p type layer 12 is an n-type epitaxial growth layer 16 is used up, with an intermediate layer an n + type embedded layer 14 which serves as a source region of the SIT and to which the function as a bit line is assigned.

On the surface of the epitaxial layer 16 is a p-type gate zone 18A is formed in such a pattern that a plurality of parts such as 16A of the epitaxial layer 16 is surrounded. This part 16A of the n type zone 16, which is carried out by surrounding the p type gate region 18A serves as the channel region of the SIT. On the top An n-type drain zone 20 is arranged in this channel zone. That way will a SIT formed by the embedded n + type source zone 14, the n type epitaxial channel zone 16, the n + type drain region and the p + type gate regions 18A.

After the p + type gate region 18A is formed, the surface becomes of the epitaxial growth layer 16 is selectively oxidized to the exclusion of the part the same, which corresponds locally to the n-type drain zone 20. The result are the oxidized surfaces of the epitaxial layer 16 are covered by silicon oxide films 22. After these silicon oxide films 22 are formed, the resulting surfaces become subjected to the deposition of a conductive substance, which in this embodiment polycrystalline silicon is the limit by using the photolithographic Method is patterned, and in this way a drain electrode layer 24 is trained. During or after the step of deposition of polycrystalline silicon becomes that of polycrystalline silicon Drain electrode layer 24 heavily with donor imperfections such as phosphorus endowed. Accordingly, as such, the drain electrode layer 24 is a low one Formed with resistance value having layer. Along with this, there is a doping of the Dontar disturbance causes, via the drain electrode layer 24 in the surface part of the monocrystal into which the silicon oxide films or layers 22 do not is covered. In this way, the n-type drain region 20 is formed. Be it notes that as a method of forming the drain electrode sheet 24 and the drain region Various other avenues are contemplated in addition to the above method can be, including the procedure, which a border sampling provides during the evaporative deposition of a metal such as of aluminum after selective diffusion of a donor impurity or donor imperfections. Such various methods can be used as necessary.

On the drain electrode layer 24 via an insulating layer 26 is a conductive layer 28 is formed to serve as the word line, this layer made of a metal such as aluminum. This insulating or separating layer 26 is intended to serve as a dielectric medium when an information storage capacitor is formed between the drain electrode sheet 24 and the conductive sheet 28. the Separation layer 26 can be made through the use of such a material as, for example Silicon oxide or phosphorus silicon glass (PSG) can be formed. The usage of However, silicon nitride is preferred from the standpoint of dielectric coefficient. By using the thermal oxidation process it is possible, with good precision, a SIO2 layer to a thickness of 10 to 100 nm manufacture, and it is also possible to have a considerable large capacity obtain.

It should be noted that the word lines and bit lines are made up of any conductive material, such as metal or a doped semiconductor can be. In the same way, the insulating layers can be made of any insulating material, such as silicon oxide, silicon nitride, aluminum oxide, polyimide or from another material with a high resistance value. The choice of material for the insulators and electrodes is determined by the intended purpose.

In order to obtain a memory device z, which the invention Functions, the corresponding typical parameters, i.e. the thickness and the impurity concentrations of the corresponding zones of the invention Memory cell selected as follows.

The impurity concentration of the p-type substrate 12 is approximately 1014-1016 cm ~ 3. The embedded n + type source zone 14 has an impurity concentration from 1018 - 1020 cm -3 and a thickness of 1 - 5 micrometers. The n type epitaxial layer 16 has an impurity concentration of 1012-1015 cm 3 and a thickness of 1 - 5 micrometers. The P type gate regions 18A have an impurity concentration from 1018 - 1021 cm 3 and a thickness of 0.5 - 3 micrometers. The 5102 insulating or Separating layer 22 has a thickness of 50-500 nm. The n-type drain zone 20 has an impurity concentration of 1018-1021 cm -3 and a thickness of 1 micrometer or smaller. The conductive layer 24, the in this embodiment made of polycrystalline silicon has an impurity concentration of 1018-1021 cm -3 and a thickness of 100-500 nm. This conductive layer 24 and The conductive layer 28 can also be made of a conductive metal, such as, for example Made of aluminum. The insulating layer 26 made of SIOZ has a thickness of 10 - 100 nm.

According to the structure described above, as by the equivalent circuit 3, a memory cell structure is obtained such that an information storage capacitor C is connected to the drain D of the SIT. In Fig. 3, the gate G corresponds to the p + Type gate zone 18 A of FIG. 2 and in the same way the source S corresponds to embedded n + type layer 14, and the drain D corresponds to the n + type zone 20, whereas one of the electrodes of the capacitor C of the drain electrode sheet 24 and the other of the electrodes of the capacitor of the conductive layer 28 corresponds.

The above description has focused primarily on a single memory cell structure referred to. In practice, however, a large number of such memory cells are in Matrix form on a semiconductor chip 10, as shown in Fig. 1, arranged. In particular there are a plurality of n-type epitaxial growth layers on the respective surfaces 16, which are defined by a plurality of elongated isolation or separation zones 30A, 30B, 30C, 30D, .... are separated, a plurality of p + type gate zones 18A, 18B, 18C, .... formed in such a way that these respective gate regions have a plurality of Form channel zones 16A. Together with this, there is a plurality of n + type zones 20 in matrix form designed in such a way that this corresponds to the points on the tops of the corresponding Channel zones 16A correspond. In addition, a variety of Drain electrode sheets 24 are provided, each having a large area or area arranged in such a way that this corresponds to the plurality of n + type zones 20. On the insulating film or the separation layer 26, there are a plurality of word lines serving conductive layers 28 arranged such that at right angles the p + Type gate zones 18A, 18B, 18C, .... are crossed.

In this way, at each crossing point of the conductive layers 28 of the word lines and the p type gate zones 18A, 18B, 18C an information storage capacitor C formed.

It should be noted that the one used to construct each of the above-mentioned cells The memory device typically used SIT to normally be in the off state which type belongs, but also normally which are in the on-state SITs can be used.

With the SIT memory cell arrangement described above, it is possible to not only to control the storage of information in the capacitor C, but also the reading out of this stored information by appropriate control the potential of both word lines 28 and bit lines 14, with a fixed bias potential applied to gate regions 18A to 18C will.

The semiconductor memory device according to the invention has the advantage that the storage capacity of the capacitor C is independent of such factors as Cross-sectional area of the channel zone can be increased.

That is, in the prior art, the storage capacity of the capacitor C through the area of the drain zone 20 (corresponding to the cross-sectional area the channel zone) of Fig. 1 is determined. Therefore, if it is intended, the packing density To enlarge the device by reducing the size of the cell, the The storage capacity of the capacitor C is correspondingly reduced in an unavoidable manner. In contrast, in the present invention, it is the storage capacity of the capacitor C is determined by the area of the drain electrode sheet 24 that can be expanded up to the limit that permits border sampling. Even in the case of the cell size restriction this therefore never leads to an increase in the packing density on a semiconductor chip directly to a reduction in storage capacity.

The possibility of increasing the information storage capacity of the Capacitor C, as described above, indicates that the leakage effect of the stored Charge is reduced, and that a large readout is thus determined or detected can be. Such a feature is to effect an improvement in the memory characteristic a storage device expedient. Furthermore, it makes the structure described above of the memory device possible to easily place a drain electrode to the outside of the To guide storage device by providing an electrode contact opening, and also because the SIT itself can be placed on the same chip, for purposes such as peripheral circuits.

It should be noted that the invention does not extend to that described above Embodiment is limited, but that rather modifications are possible. For example becomes the conductive one in the above embodiment Layer 28 is used as the word line, so a fixed bias potential is applied the p + type gate zones 18A, 18B, 18C, .... is applied. This pattern of arrangement and working method can be reversed. That is, the arrangement can be made in this way that a fixed bias potential is applied to the conductive layer 28, and the p + type gate regions 18A, 18B, 18C, ....

can be used as the word lines. The advantage of the possibility the increase in storage capacity, as in the embodiment described above, can be achieved in the same way in the last-mentioned embodiment. In this reverse type device, however, the conductive sheet 28 may be used as a single continuous sheet may be formed containing all of the drain electrode sheets covered.

The person skilled in the art recognizes that the respective zones can also be reversed Conductivity type can be built up.

In such a case, a similar effect can be achieved if the polarity of the applied voltage is changed appropriately.

In summary, the invention provides a semiconductor memory device before, with at least one memory cell, each cell by a static Induction transistor with a very small parasitic gate capacitance, a very low gate zone resistance and a very small space charge storage effect is formed, and it is further provided that the charge carriers by an electrical Field are subjected to a drift movement. This memory cell according to the invention provides that one of the two electrodes of a capacitor is formed at the drain zone of the transistor and connected to this drain zone for storing charge carriers educated is, with a connecting layer, directly connected to the drain zone, and that this Connection layer has an area larger than the area of the drain zone. These Arrangement has the advantage that when the cell size improves the packing density is decreased, the storage capacity is not directly affected because this capacity is determined by the expandable area of the conductive layer.

Claims (8)

Semiconductor memory device with at least one Storage cell, characterized in that the storage cell has the following: a source zone (14) for supplying and removing charge carriers, a drain zone (20), a channel zone (16A) for connecting the source zone and the drain zone To provide such a path for the charge carriers, one sandwiching the channel zone comprehensive gate structure to create a potential barrier for the charge carriers in the channel zone to build, with the source, channel and drain zones and the gate structure in one Semiconductor bodies are arranged and form a static induction transistor, and a capacitor "C" formed on the drain region connected thereto and to two conductive layers, which serve as electrodes, and which are separated from each other by a intermediate insulating layers are separated, and wherein one of the conductive layers communicates directly with the drain zone, and an area larger than that of the Has drain zone. 2. Semiconductor memory device according to claim 1, characterized in that that the drain zone is arranged in the vicinity of the surface of the semiconductor body is, that the source zone is arranged in the mass of the semiconductor body, and that the one of the conductive layers directly connected to the drain zone on a surface of the Covered drain zone and extends further beyond this drain zone. 3. Semiconductor memory device according to claim 1 and / or 2, characterized characterized in that the gate structure is provided with a further insulating or separating layer is covered, and that one of the conductive layers is connected to the drain region extends from the surface of the drain zone to the mentioned other insulating layer, to partially cover this latter insulating layer. 4. Semiconductor memory device according to claim 1, characterized in that that the other of the two conductive layers with one of a plurality of word lines that the source zone is connected to one of a plurality of bit lines is in connection, and that a fixed potential can be applied to the gate structure is. 5. Semiconductor memory device according to one or more of the preceding Claims, in particular according to claim 1, characterized in that the gate structure is connected to one of the plurality of word lines that the source zone is connected to one of a plurality of bit lines, and that the other of the both connection layers can be provided with a fixed potential. 6. Semiconductor memory device according to claim 5, characterized in that that the other of the two conductive layers is continuous with all of the plurality of the memory cells is arranged in an array. 7. Semiconductor memory device with at least one memory cell, characterized in that the memory cell comprises: a source region for delivery and removal and charge carriers, a drain zone, a channel zone for Connection of the source zone and the drain zone to generate a path for the Charge carriers, a gate structure that sandwiches the channel region to allow in the channel zone to provide a potential barrier for the charge carriers, the Source, channel and drain zones and the gate structure in a semiconductor body are arranged and form a static induction transistor, a first insulating layer, which covers the gate structure and leaves the channel zone and the drain zone, a first conductive layer which directly covers the drain zone and extends over the The drain zone extends out to partially cover the first insulating or separating layer, a second insulating or separating layer which is the first conductive layer and covering the first insulating layer, and a second conductive layer covering the second insulating layer covered, and finally being the first and second conductive Layers and the second insulating layer together form a capacitor that is connected to the Drain zone is connected to store the charge carriers. 8. Semiconductor memory device according to claim 7, characterized in that that the semiconductor body is formed from silicon and has the following: a Wafer having a high resistance layer of a conductivity type is a low resistance embedded layer of a first Conductivity type that serves as a source zone and a high resistance value having layer epitaxially formed on the source region, and the first Conductivity type has to provide the channel zone, and wherein the gate structure with layers of a second conductivity type having a low resistance value opposite to the first conductivity type is formed around the channel zone sandwiched, and further comprising the drain region with a low Resistance value having layer of the first conductivity type is formed, and wherein the first conductive layer is formed with polycrystalline silicon and the second conductive layer is formed from a conductive metal.