DE2941653A1 - MOS transistor technology - employs high dose ion implantation and simultaneous gate and field oxide growth - Google Patents

MOS transistor technology - employs high dose ion implantation and simultaneous gate and field oxide growth

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Publication number
DE2941653A1
DE2941653A1 DE19792941653 DE2941653A DE2941653A1 DE 2941653 A1 DE2941653 A1 DE 2941653A1 DE 19792941653 DE19792941653 DE 19792941653 DE 2941653 A DE2941653 A DE 2941653A DE 2941653 A1 DE2941653 A1 DE 2941653A1
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Germany
Prior art keywords
field oxide
oxide
high dose
gate
oxide growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19792941653
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German (de)
Inventor
Dipl.-Phys. Dr. Egon 8000 München Bußmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19792941653 priority Critical patent/DE2941653A1/en
Publication of DE2941653A1 publication Critical patent/DE2941653A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

This technology employs a method of producing MOS transistors whereby the field oxide and gate oxide are produced simultaneously, thus avoiding the problems of nitride separation, tension stresses and the white ribbon effect. This is accomplished by implanting high dose ions in the field oxide regions and then building up the gate-and field oxide in a temperature of between 550 deg.C and 700 deg.C simultaneously. The silicon substrate is masked with a photo-lacquer coating (2). The implanting of the high dose ions in the field oxide region results in the formation of regions (3) in the substrate. During the subsequent oxidation at a temperature of 620 deg.C an oxide growth ratio of 6 to 1 is achieved. Repetition of the process increases oxide growth even further.

Description

Verfahren zur Herstellung von MOS-Transstoren.Process for the production of MOS transistors.

Die Erfindung betrifft ein Verfahren zur Herstellung von MOS-Transistoren, bei denen eine dünne Oxidschicht auf die Gatefläche aufgebracht wird und eine dicke Oxidschicht auf dem Feldbereich erforderlich ist.The invention relates to a method for manufacturing MOS transistors, in which a thin oxide layer is applied to the gate area and a thick one Oxide layer on the field area is required.

Es hat sich gezeigt, daß man mit dem Isoplanarverfahren - auch LOCOS-Verfahren (local oxidation of silicon) genannt - in Verbindung mit einer besonderen Technologie zum Anbringen von P-dotierten Bereichen eine drastische Reduktion der erforderlichen Oberfläche erzielen kann.It has been shown that the isoplanar method - also LOCOS method (local oxidation of silicon) - in connection with a special technology for attaching P-doped areas a drastic reduction in the required Surface can achieve.

In der LOCOS-Technologie wird der Gatebereich mit einer Siliziumnitridschicht auf Siliziumdioxid und Silizium während des Feldoxidaufbaus abgedeckt. Nach Abätzen dieser Schichtkombination wird das Gateoxid gesondert aufgebaut.In LOCOS technology, the gate area is covered with a silicon nitride layer covered on silicon dioxide and silicon during field oxide build-up. After etching The gate oxide is built up separately from this layer combination.

Der Erfindung liegt die Aufgabe zugrunde, gleichzeitig Feldoxid und Gateoxid eines MOS-Transistors herzustellen.The invention is based on the object, at the same time field oxide and Manufacture gate oxide of a MOS transistor.

Dies geschieht nach der Erfindung dadurch, daß der Feldoxidbereich mit Ionen hoher Dosis implantiert und an- schließend in einem Temperaturbereich zwischen 55000 und 70000 gleichzeitig Gateoxid und Feldoxid aufgebaut werden. Auf diese Weise werden Gateoxid und Feldoxid in einem Schritt erzeugt. Es werden damit fehleranfällige Prozeßschritte, wie z. B. Oxidation, Nitridabscheidung, Dreistufenätzung und Reinigungen eingespart. Bei dem Verfahren nach der Erfindung dient die Implantation gleichzeitig als Channel-stop. Bei der angegebenen niederen Temperatur entstehen keine Kristallfehler. Ein weiterer Vorteil der Erfindung liegt darin begründet, daß bei Verwendung der Hochdruck-H20-Oxidation sich eine Zeitersparnis ergibt.This is done according to the invention in that the field oxide area implanted with ions of high dose and closing in a temperature range between 55,000 and 70,000 gate oxide and field oxide can be built up at the same time. on in this way, gate oxide and field oxide are produced in one step. It will be with it error-prone process steps, such as B. Oxidation, nitride deposition, three-step etching and cleanings saved. In the method according to the invention, the implantation is used at the same time as a channel stop. Formed at the specified low temperature no crystal defects. Another advantage of the invention is based on that when using the high pressure H20 oxidation there is a time saving.

Nach einer Weiterbildung der Erfindung kann bei einem zweiten Arbeitsvorgang neues Gate- und weiteres Feldoxid aufgebaut werden. Auf diese Weise ist ein dickeres Feldoxid zu erreichen. Der wesentliche Vorteil besteht darin, daß fzr diesen zweiten Arbeitsgang keine zusätzliche Maskierung erforderlich ist.According to a further development of the invention, in a second operation new gate and further field oxide are built. This way is a thicker one To achieve field oxide. The main advantage is that for this second No additional masking is required.

Die Erfindung wird anhand der Figuren erläutert. Es zeigen im Schnitt: Figur 1 ein Substrat mit einer Fotolackabdeckung, Figur 2 die Implantation und Figur 3 die Oxidation.The invention is explained with reference to the figures. It shows in section: 1 shows a substrate with a photoresist cover, FIG. 2 shows the implantation and FIG 3 the oxidation.

Die Figur 1 zeigt lediglich ein Siliziumsubstrat 1, das mit einer Maske 2 aus Fotolack abgedeckt ist. Anschließend wird, wie in der Figur 2 dargestellt ist, der Feldoxidbereich mit Ionen hoher Dosis implantiert.Figure 1 shows only a silicon substrate 1, which with a Mask 2 is covered from photoresist. Then, as shown in FIG the field oxide region is implanted with high dose ions.

Dabei bilden sich in dem Siliziumsubstrat, das N+ dotiert ist, Bereiche 3. Nach dem Entlacken erfolgt eine Oxidationsbehandlung im Temperaturbereich zwischen 55000 und 700 0C - bevorzugt 620 0c - wobei gleichzeitig Gateoxid 4 und Feldoxid 5 aufgebaut werden. Bei einem ersten Oxidationsgang lassen sich z. B. Unterschiede im Oxidwachstum im Verhältnis 6:1 erreichen. Ein Uberätzen des Gateoxids und nochmalige Oxidation erhöhen das Verhältnis weiter.Areas are formed in the silicon substrate which is doped with N + 3. After the paint has been stripped, an oxidation treatment takes place in the temperature range between 55000 and 700 0C - preferably 620 0c - with gate oxide at the same time 4 and field oxide 5 are built up. In a first oxidation process, for. B. Achieve differences in oxide growth in a ratio of 6: 1. Overetching of the gate oxide and re-oxidation further increase the ratio.

Die Erfindung ist nicht auf das beschriebene Ausführungs beispiel und nicht ausschließlich auf die Herstellung von MOS-Transistoren beschränkt. Dieses Verfahren kann z. B. für jede selektive Oxidation von Halbleiterbereichen genutzt werden, in denen die Nachteile der Nitridabscheidung, Spannungsstress und "White Ribbon-Effekt", vermieden werden sollen.The invention is not based on the embodiment described, for example and not exclusively limited to the manufacture of MOS transistors. This Process can e.g. B. used for any selective oxidation of semiconductor areas in which the disadvantages of nitride deposition, voltage stress and "white Ribbon Effect "should be avoided.

2 Patent ansprüche 3 Figuren2 claims 3 figures

Claims (2)

Patentansprüche. ~ 1. Verfahren zur Herstellung von MOS-Transistoren, bei denen eine dünne Oxidschicht auf die Gatefläche aufgebracht wird und eine dicke Oxidschicht auf dem Feldbereich erforderlich ist, d a d u r c h g e k e n n -z e i c h n e t , daß der Feldoxidbereich mit Ionen hoher Dosis implantiert (Figur 2) und im Temperaturbereich zwischen 5500C und 7000C gleichzeitig Gateoxid (4) und Feldoxid (5) aufgebaut werden (Figur 3).Claims. ~ 1. Method of manufacturing MOS transistors, in which a thin oxide layer is applied to the gate area and a thick one Oxide layer on the field area is required, d u r c h e k e n n -z e i c h n e t that the field oxide region is implanted with high dose ions (Figure 2) and in the temperature range between 5500C and 7000C at the same time gate oxide (4) and Field oxide (5) are built up (Figure 3). 2. Verfahren nach Anspruch 1, d a d u r c h g e -k e n n z e i c h n e t , daß nach einem Uroeratzen des Gateoxids bei einem zweiten Oxidationsvorgang nochmals Gateoxid und Feldoxid aufgebaut werden.2. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that after uretching of the gate oxide in a second oxidation process gate oxide and field oxide are built up again.
DE19792941653 1979-10-15 1979-10-15 MOS transistor technology - employs high dose ion implantation and simultaneous gate and field oxide growth Withdrawn DE2941653A1 (en)

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Application Number Priority Date Filing Date Title
DE19792941653 DE2941653A1 (en) 1979-10-15 1979-10-15 MOS transistor technology - employs high dose ion implantation and simultaneous gate and field oxide growth

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DE19792941653 DE2941653A1 (en) 1979-10-15 1979-10-15 MOS transistor technology - employs high dose ion implantation and simultaneous gate and field oxide growth

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5571736A (en) * 1987-12-03 1996-11-05 Texas Instruments Incorporated Fabricating a high density EPROM cell by removing a portion of the field insulator regions
US5733813A (en) * 1996-05-09 1998-03-31 National Semiconductor Corporation Method for forming planarized field isolation regions
US5918116A (en) * 1994-11-30 1999-06-29 Lucent Technologies Inc. Process for forming gate oxides possessing different thicknesses on a semiconductor substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5571736A (en) * 1987-12-03 1996-11-05 Texas Instruments Incorporated Fabricating a high density EPROM cell by removing a portion of the field insulator regions
US5918116A (en) * 1994-11-30 1999-06-29 Lucent Technologies Inc. Process for forming gate oxides possessing different thicknesses on a semiconductor substrate
US5733813A (en) * 1996-05-09 1998-03-31 National Semiconductor Corporation Method for forming planarized field isolation regions

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