DE2930779A1 - Contact layer for semiconductor chip - consists of three or four metal layers giving firm bond and including gold-germanium alloy layer for soldering - Google Patents
Contact layer for semiconductor chip - consists of three or four metal layers giving firm bond and including gold-germanium alloy layer for solderingInfo
- Publication number
- DE2930779A1 DE2930779A1 DE19792930779 DE2930779A DE2930779A1 DE 2930779 A1 DE2930779 A1 DE 2930779A1 DE 19792930779 DE19792930779 DE 19792930779 DE 2930779 A DE2930779 A DE 2930779A DE 2930779 A1 DE2930779 A1 DE 2930779A1
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- Germany
- Prior art keywords
- gold
- alloy
- germanium
- metal layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
Haible itervorrichtungHaible iter device
Beschreibung Die Erfindung betrifft eine Haibleitervorrichtung gemäß dem Oberbegriff des Patentanspruches 1. Insbesondere bezieht sie sich auf eine Haibleitervorrichtung mit einer verbesserten Möglichkeit zum Befestigen der Halbleiterelemente auf den Chipbefestigungs- bzw. Anschlußteilen (pfads). Description The invention relates to a semiconductor device according to the preamble of claim 1. In particular, it relates to a semiconductor device with an improved ability to attach the semiconductor elements to the Chip mounting or connection parts (paths).
Fig. 1 stellt einen Teil einer bekannten Halbleitervorrichtung dar, bei dem ein Halbleiterelement 1 aus Silicium (im folgenden "Siliciumchip" genannt) auf einem Chipbefestigungsteil 2 wie einem Leiterrahmen und einem Stiel befestigt ist. Der Kollektorbereich des Siliciumchips 1 ist mit dem Chipbefestigungsteil 2 verbunden. Die Basis-und Emitterbereiche des Chips 1 sind mittels Befestigungsdrähten 3 mit Leitungsstücken 4 verbunden.Fig. 1 illustrates part of a known semiconductor device, in which a semiconductor element 1 made of silicon (hereinafter "silicon chip" called) on a chip mounting part 2 such as a lead frame and a stem is attached. The collector area of the silicon chip 1 is with the chip mounting part 2 connected. The base and emitter areas of the chip 1 are secured by means of fastening wires 3 connected to line pieces 4.
Es sind verschiedene Verfahren bekannt, um ein Siliciumchip auf einem Chipbefestigungsteil zu befestigen. Von diesen Verfahren werden die folgenden im allgemeinen angewandt: a) Es wird zwischen einem Siliciumchip und einem Chipbefestigungsteil eine Goldfolie oder eine Goldlegierungsfolie von etwa 10 ijm Dicke eingefügt. Dann wird das Chip und das Befestigungsteil mit der zwischenliegenden Folie auf eine Temperatur erhitzt, die höher als die eutektische Temperatur von Gold-Silicium ist, d. h. höher als 373 °C. Zwischen dem Chip und der Befestigungsplatte wird damit eine Gold-Silicium-Legierung gebildet und hierdurch das Siliciumchip auf dem Chipbefestigungsteil befestigt.Various methods are known to produce a silicon chip on a To attach chip mounting part. Of these methods, the following are provided in the Generally applied: a) It is applied between a silicon chip and a chip mounting part a gold foil or a gold alloy foil about 10 µm thick is inserted. then the chip and the fastening part with the intermediate film on one Heated temperature higher than the eutectic temperature of gold-silicon, d. H. higher than 373 ° C. This is used between the chip and the mounting plate a gold-silicon alloy is formed and thereby the silicon chip on the chip mounting part attached.
b) Zwischen einem Siliciumchip und einem Chipbefestigungsteil wird eine eutektische Gold-Silicium-Schicht gebildet, indem eine Gold- oder eine Goldlegierungsschicht auf dem Siliciuincüip erhitzt wird. Zwischen die e tische Schicht und das Chipbeft tigungsteil wird Goldfolie oder eine Goldlegierungsrolie eingefügt- Das Chip, das Befestigungsteil, die # cutektiche Schicht w ~osrn die Folie werden zusammengefügt und dann au eine Temperatur oberhalb der eutektischen Temperatur 1 von Gold-Silicium erhitzt, wodurch das c?#tp all dem Befestigungteil befestigt wird.b) Between a silicon chip and a die attach part a eutectic gold-silicon layer is formed by adding a gold or gold alloy layer on the Siliciuincüip is heated. Between the table layer and the chip mounting part gold foil or gold alloy foil is inserted - the chip, the fastening part, the cutectic layer w ~ o the foil are put together and then on one Temperature above the eutectic temperature 1 of gold-silicon heated, whereby the c? #tp is attached to all the mounting part.
c) Auf einer Oberfläche eines Siliciurnsitstrats wird eine Gold-Silicium-Legierungsschicht einer geeigneten Dicke gebildet. Das Siliciumsubstrat wird dann zu Chips geschnitten. Unter Verwendung der Legierungsschicht als Lötmittel wird das jeweilige Siliciumchip auf dem Chipbefestigungsteil befestigt.c) A gold-silicon alloy layer is formed on a surface of a silicon substrate a suitable thickness. The silicon substrate is then cut into chips. Using the alloy layer as solder, the respective silicon chip attached to the chip mounting part.
d) Eine Gold-Germanium-Legierungsschicht bzw. eine Gold-Antimon-Legierungsschicht geeigneter Dicke wird auf einer Oberfläche eines Siliciumsubstrats gebildet.d) A gold-germanium alloy layer or a gold-antimony alloy layer appropriate thickness is formed on a surface of a silicon substrate.
Das Siliciumsubstrat wird dann zu Chips geschnitten. The silicon substrate is then cut into chips.
Unter Verwendung der Legierungsschicht als Lötmittel wird das Siliciumchip auf dem Chipbefestigungsteil befestigt. Using the alloy layer as a solder, the silicon chip is made attached to the chip mounting part.
Das Verfahren a) weist Mängel in folgender Hinsicht auf: 1) Da die Folie viel größer ist als das Siliciumchip, ist die Genauigkeit der Positionierung des Chips schlecht. Dies verursacht unvermeidbar Schwierigkeiten bei den darauffolgenden Herstellungsprozessen der Halbleitervorrichtung.Procedure a) has shortcomings in the following respects: 1) Since the foil is much larger than the silicon chip, the accuracy of the positioning is lower of the chip bad. This inevitably causes trouble in the subsequent ones Manufacturing processes of the semiconductor device.
2) Um die Folie auf dem Chipbefestigungsteil anzubringen, ist eine Vorrichtung hoher Genauigkeit erforderlich.2) To attach the film to the chip mounting part, a High accuracy device required.
3) Es ist eine große Menge an Gold erforderlich, das sehr teuer ist.3) It takes a large amount of gold, which is very expensive.
4) Es ist schwierig, eine ausreichend starke Bindung zwischen dem Chip und dem Befestigungsteil herzustellen.4) It is difficult to have a strong enough bond between the Manufacture chip and the fastening part.
Die Haftfestigkeit ist von Ifalbleitervorrichtung zu Halbleitervorrichtung verschieden. Die Erzeugnisse sind deshalb nicht ausreichend zuverlässig. The adhesive strength varies from semiconductor device to semiconductor device different. The products are therefore not sufficiently reliable.
Das Verfahren (b) ist zwar gegenüber dem Verfahren a) vorteilhaft insofern, als es eine stärkere Haftung zwischen dem Siliciumchip und dem Chipbefestigungsteil ermöglicht.Process (b) is advantageous over process a) in that there is stronger adhesion between the silicon chip and the chip mounting part enables.
Es haften ihm aber auch noch die unter 1) bis 3) angegebenen Mängel an.The defects specified under 1) to 3) are also liable to him at.
Das Verfahren gemäß c) erlaubt es, die Kosten der Halbleitervorrichtung herabzusetzen, da es keine Goldfolie benutzt. Aus diesem Grund benötigt es auch keine Vorrichtung zum Positionieren einer Folie auf dem Chipbefestigungsteil. Es ist bei diesem Verfahren aber außerordentlich schwierig, ein gutes Zerteilen des Siliciumsubstrats in Würfel zu erzielen. Da die eutektische Gold-Silicium-Schicht ein jim oder dicker ist, wird das Substrat längs Würfellinien von der Oberfläche aus geschnitten, auf der die eutektische Schicht gebildet ist, wie dies in der japanischen Patentveröffentlichung 13 27 78/77 beschrieben ist. In der Praxis ist es jedoch außerordentlich schwierig, das Substrat exakt längs der Würfellinien zu schneiden.The method according to c) makes it possible to reduce the cost of the semiconductor device as it does not use gold foil. Because of this, it also needs no device for positioning a film on the die attach part. It is extremely difficult with this method, a good division of the Silicon substrate in cubes. Because the eutectic gold-silicon layer a jim or thicker, the substrate is diced along cube lines from the surface cut out on which the eutectic layer is formed, as is done in Japanese Patent publication 13 27 78/77 is described. In practice, however, it is extremely difficult to cut the substrate exactly along the cube lines.
In den meisten Fällen wird das Substrat längs einer Linie geschnitten, die 100 am oder mehr von der Würfellinie entfernt ist.In most cases the substrate is cut along a line, 100 am or more from the dice line.
Das Verfahren d) weist insofern Mängel auf, als die Bindung zwischen der Legierungsschicht und dem Siliciumsubstrat nicht ausreichend stark ist. Als Folge besteht die Gefahr, daß sich die Legierungsschicht während des Würfelschneidens vom Substrat ablöst. Falls sich die Legierungsschicht nicht vom Substrat löst, ist das erhalt-ene Produkt infolge der schlechten Bindung zwischen der Legierungsschicht und dem Siliciumsubstrat unzuverlässig.The method d) has deficiencies in that the bond between the alloy layer and the silicon substrate are not sufficiently thick. as As a result, there is a risk that the alloy layer will break down during dicing separates from the substrate. If the alloy layer does not come off the substrate, it is the product obtained as a result of the poor bond between the alloy layer and the silicon substrate unreliable.
Ziel dieser Erfindung ist eine Haibleitervorrichtung, bei de das Halbleiterelement auf dem Chipbefestigungsteil e:::iJ-t positioniert ist, das mit geringen Kosten hergestellt werden kann und das eine starkeBindung zwischen dem Halbleiterelement und dem Chipbefestigungsteil aufweist.The object of this invention is a semiconductor device in which the semiconductor element is positioned on the chip mounting part e ::: iJ-t, that with low cost can be made and that a strong bond between the semiconductor element and the die attach part.
Die Erfindung ist durch die Merkmale des Anspruches 1 gekennzeichnet. Vorteilhafte Ausgestaltungen der Erfindung sind den Unteransprüchen zu entnehmen.The invention is characterized by the features of claim 1. Advantageous refinements of the invention can be found in the subclaims.
Die Erfindung wird durch Ausführungsbeispiele anhand von 5 Figuren näher erläutert. Es zeigen: Fig. 1 eine perspektivische Ansicht eines Teils einer bekannten Halbleitervorrichtung, bei der ein Siliciumchip auf einem Leiterrahmen befestigt ist; Fig. 2 eine Querschnittsansicht eines Siliciumsubstrats gemäß dieser Erfindung; Fig. 3 eine Querschnittsansicht einer Halbleitervorrichtung gemäß dieser Erfindung, bei der auf einem Chipbefestigungsteil ein Siliciumchip befestigt ist; Fig. 4 ein Diagramm, das die Verteilung des thermischen Widerstandes in einer erfindungsgemäßen Halbleitervorrichtung zeigt; und Fig. 5 eine Querschnittsansicht eines weiteren Siliciumsubstrats gemäß dieser Erfindung.The invention is illustrated by exemplary embodiments on the basis of 5 figures explained in more detail. 1 shows a perspective view of part of a known semiconductor device in which a silicon chip is mounted on a lead frame is attached; Fig. 2 is a cross-sectional view of a silicon substrate according to this Invention; 3 is a cross-sectional view of a semiconductor device according to this Invention in which a silicon chip is mounted on a chip mounting part; Fig. 4 is a diagram showing the distribution of thermal resistance in an inventive Shows semiconductor device; and Fig. 5 is a cross-sectional view of another Silicon substrate according to this invention.
Eine Halbleitervorrichtung gemäß dieser Erfindung enthält ein Chipbefestigungsteil und ein Halbleiterelement mit drei Metallschichten, die zwischen dem Befestigungsteil und dem Element eingefügt sind. Die erste Metallschicht ist auf eine Oberfläche des Halbleiterelementes aufgebracht und aus einem Metall hergestellt, das aus der Gruppe Vanadium, Aluminium, Titan, Chrom, Molybdän und Nickel-Chrom-Legierung ausgewählt ist. Die zweite Metallschicht, die auf die erste Metallschicht aufgebracht ist, ist aus einem Metall hergestellt, das aus der Gruppe Kupfer, Legierung auf Kupferbasis, Nickel und Legierung auf Nickelbasis ausgewählt ist. Die dritte Metallschicht, die auf die zweite Metallschicht aufgebracht ist, ist aus einer Gold-Germanium-Legierung oder aus einer Legierung auf der Basis von Gold-Germanium hergestellt. Die dritte Metallschicht wirkt als Lötmaterial, das das Halbleiterelement am Chipbefestigungsteil befestigt.A semiconductor device according to this invention includes a die attach part and a semiconductor element having three metal layers interposed between the fixing part and the element are inserted. The first metal layer is on a surface of the semiconductor element applied and made of a metal that consists of the Vanadium, aluminum, titanium, chromium, molybdenum and nickel-chromium alloy group are selected is. The second metal layer, which is applied to the first metal layer, is made of a metal belonging to the group copper, copper-based alloy, Nickel and nickel-based alloy is selected. The third layer of metal that is applied to the second metal layer is made of a gold-germanium alloy or made from an alloy based on gold-germanium. The third Metal layer acts as a solder that attaches the semiconductor element to the die attach part attached.
Die erste und die zweite Metallschicht bewirken eine Verstärkung der Bindung zwischen dem Halbleiterelement und der dritten Metallschicht.The first and second metal layers reinforce the Bond between the semiconductor element and the third metal layer.
Die dritte Metallschicht kann,während sie gebildet wird, oxidiert werden. Falls dies geschieht, wird die Haftfestigkeit zwischen der dritten Metallschicht und dem Chipbefestigungsteil herabgesetzt. Um eine solche Verminderung der Haftfestigkeit zu vermeiden, kann die dritte Metallschicht mit einer vierten Metallschicht bedeckt werden, die aus der Gruppe Gold, Silber und Platin ausgewählt ist.The third metal layer may be oxidized as it is formed will. If this happens, the bond strength between the third metal layer will be reduced and the chip attaching part lowered. To such a decrease in bond strength To avoid this, the third metal layer can be covered with a fourth metal layer that will come from the Group gold, silver and platinum is selected.
Als Legierung auf Kupferbasis und als Legierung auf Nickelbasis, d. h. als Material der zweiten Metallschicht, können eine Kupfer-Nickel-Legierung und eine Ni#kel-Chrom-Legierung verwendet werden. Als Legierung auf Gold-Germanium-Basis, d. h. als Material der dritten Metallschicht, kann eine Gold-Germanium-Antimon-Legierung oder eine Gold-Germar.ium-Gallium-Legierung verwendet werden. Das Antimon in der Gold-Germanium-Antimon-Legierung dient dazu, die Kollektor-Emitter-Sättigungsspannung Vces der Halbleitervorrichtung herabzusetzen.As a copper-based alloy and a nickel-based alloy, i. H. as the material of the second metal layer, a copper-nickel alloy and a nickel-chromium alloy can be used. As an alloy based on gold-germanium, d. H. A gold-germanium-antimony alloy can be used as the material of the third metal layer or a gold-germarium-gallium alloy can be used. The antimony in the Gold-germanium-antimony alloy serves to reduce the collector-emitter saturation voltage Decrease Vces of the semiconductor device.
Wird eine Gold-Germanium-Antlmon-Legierung auf einer Nickelschicht oder einer Legierungsschicht auf der Basis von Nickel abgeschieden, dann wird zuerst Antimon abgeschieden, da der Dampfdruck von Antimon höher als der von Gold oder Germanium ist. Das niedergeschlagene Antimon reagiert mit Nickel in der Weise, daß es eine Erhöhung des thermischen Widerstandes Rth der Halbleitervorrichtung verursacht. Um diese Reaktion zwischen Nickel und Antimon zu vermeiden, kann zwischen der Nickelschicht bzw. der LegieruncJsschicht auf Nickelbasis und der Gold-Germanium-Antimon-Schicht Gold, Germanium oder eine Gold-Germanium-Legierung gebildet werden.Is a gold-germanium-antlmon alloy on a nickel layer or a nickel-based alloy layer is then deposited first Antimony deposited because the vapor pressure of antimony is higher than that of gold or Is germanium. The precipitated antimony reacts with nickel in such a way that it causes an increase in the thermal resistance Rth of the semiconductor device. In order to avoid this reaction between nickel and antimony, between the nickel layer or the alloy layer based on nickel and the gold-germanium-antimony layer Gold, germanium or a gold-germanium alloy can be formed.
Ferner kann zwischen der dritten und der vierten Metallschicht ebenfalls eine Gold-Germanium-Schicht gebildet werden.Furthermore, between the third and the fourth metal layer Likewise a gold-germanium layer can be formed.
Vorzugsweise liegt der Germanium-Anteil in der Gold-Germanium-Legierung im Bereich zwischen 4 und 20 Gew.-%. Ist der Germanium-Anteil geringer als 4 Gew.-%, dann wird die Legierung so weich, daß das Schneiden in WUrfel schwierig wird. Übersteigt der Anteil 20 Gew.-90, dann kann die dritte Metallschicht keine ausreichende Bindung mehr zwischen dem Halbleiterelement und dem Chipbefestigungsteil herstellen. Vorzugsweise sollte der Germanium-Anteil im Bereich zwischen 6 und 12 Gew.-% liegen. Am vorteilhaftesten ist es, wenn er bei 12 Gew.-% liegt, so daß ein Gold-Germanium-Eutektikum gebildet wird. Der Antimon-Anteil der Gold-Germanium-Antimon-Legierung liegt vorzugsweise im Bereich zwischen 0,005 und 1,0 Gew.-%, beruhend auf der Menge an Gold-Germanium. Am vorteilhaftesten ist es, wenn der Antimon-Anteil im Bereich zwischen 0,03 bis 0,2 Gew.-t liegt. Die erste Metallschicht sollte 50 bis 2.000 Å dick sein, die zweite Metallschicht 300 bis 5.000 Å, die dritte Metallschicht 0,8 bis 3,5 tim und die vierte Metallschicht 500 bis 5.000 Å. Es werden nun anhand der Zeichnung mehrere Beispiele dieser Erfindung erläutert.The germanium content is preferably in the gold-germanium alloy in the range between 4 and 20% by weight. If the germanium content is less than 4% by weight, then the alloy becomes so soft that it is difficult to cut into cubes. Exceeds if the proportion is 20% by weight, the third metal layer cannot bond sufficiently establish more between the semiconductor element and the die attach part. Preferably the germanium content should be in the range between 6 and 12% by weight. Most beneficial it is when it is 12% by weight, so that a gold-germanium eutectic is formed will. The antimony content of the gold-germanium-antimony alloy is preferably in the range between 0.005 and 1.0 wt% based on the amount of gold germanium. It is most advantageous if the antimony content is in the range between 0.03 to 0.2 wt. T. The first metal layer should be 50 to 2,000 Å thick, the second Metal layer 300 to 5,000 Å, the third metal layer 0.8 to 3.5 tim and the fourth metal layer 500 to 5,000 Å. There are now several Examples of this invention illustrated.
Beispiel 1 Wie in Fig. 2 dargestellt, wurde eine erste Metallschicht 12 von ungefähr 300 Å Dicke aus Saaadium,und damit geeignet auf einer Siliciumschicht gut befestigt zu werden, auf einer Oberfläche eines Siliciumsubstrats 11, in dem pNP-Transistorchips lla, 11b, 11c und 11d gebildet wurden, aus der Gasphase abgeschieden. Auf der ersten Metallschicht 12 wurde eine zweite Metallschicht 13 aufgedampft, die aus Nickel hergestellt war und eine Dicke von etwa 1.000 A hatte. Auf der zweiten Metallschicht 13 wurde eine dritte Metallschicht 14 aufgedampft bzw. aus der Gasphase abgeschieden, die aus einer Gold-Germanium-Legierung (Germanium-Anteil: 12 Gew.-%) hergestellt war und eine Dicke von etwa 1 ßm hatte. Das Siliciumsubstrat 11 wurde dann mittels eines Diamantschneiders auf der anderen Oberfläche angerissen. Danach wurde das Substrat 11 in Chips geteilt. Jedes Chip wurde auf einem silberplatierten Leiterrahmen 2 befestigt, wie dies in Fig. 3 dargestellt ist, wobei die dritte Metallschicht 14 als Lötmaterial diente. Auf diese Weise wurden Halbleitervorrichtungen, von denen jede ein Halbleiterchip enthielt, hergestellt.Example 1 As shown in Fig. 2, a first metal layer was formed 12th of about 300 Å thick of saaadium, and therefore suitable of a silicon layer on a surface of a silicon substrate 11, in which pNP transistor chips 11a, 11b, 11c and 11d were formed, from the gas phase deposited. A second metal layer 13 was placed on the first metal layer 12 vapor deposited, which was made of nickel and had a thickness of about 1,000 Å. A third metal layer 14 was vapor-deposited on the second metal layer 13 or deposited from the gas phase, which consists of a gold-germanium alloy (germanium content: 12% by weight) and had a thickness of about 1 µm. The silicon substrate 11 was then scribed on the other surface with a diamond cutter. Thereafter, the substrate 11 was divided into chips. Each chip was plated on a silver Leadframe 2 attached as shown in Fig. 3, the third metal layer 14 served as soldering material. In this way, semiconductor devices were made of which each containing a semiconductor chip.
Die Ausbeute war größer als bei den nach bekannten Verfahren hergestellten Produkten. Außerdem zeigten die Vorrichtungen eine niedrigere Kollektor-Emitter-Sättigungsspannung Vces und einen niedrigeren thermischen Widerstand Rth als die nach bekannten Verfahren hergestellten Halbleitervorrichtungen. Genauer gesagt lag Vces der Vorrichtungen zwischen 0,15 und 0,20 Volt, während V ces der nach bekannten Verfahren hergestellten Halbleitenvorrichtungen zwischen 0,2 und 0,3 Volt lag. Fig. 4 zeigt die Verteilung des thermischen Widerstandes in den Halbleitervorrichtungen A1 und A2, die nach bekannten Verfahren hergestellt worden sind, sowie in der Halbleitervorrichtung B gemäß Beispiel 1. Wie Fig. t klar erkennen läßt, war der thermische Widerstand der Halbleitervorrichtungen nach Beispiel 1 niedrig und variierte nur wenig von Vorrichtung zu Vorrichtung im Vergleich zu den bekannten Halbleitervorrichtungen.The yield was greater than that of those produced by known processes Products. In addition, the devices exhibited a lower collector-emitter saturation voltage Vces and a lower thermal resistance Rth than those obtained by known methods manufactured semiconductor devices. More precisely, Vces of the devices lay between 0.15 and 0.20 volts, while V ces of semiconductor devices made by known methods was between 0.2 and 0.3 volts. Fig. 4 shows the distribution of thermal resistance in the semiconductor devices A1 and A2 manufactured by known methods as well as in the semiconductor device B according to Example 1. As shown in FIG shows was the thermal resistance of the semiconductor devices according to Example 1 low and varied little from device to device compared to the known semiconductor devices.
Beispiel 2 Es wurden in der gleichen Weise wie bei Beispiel 1 Halbleitervorrichtungen hergestellt mit der Ausnahme, daß in dem Siliciumsubstrat NPN-Transistorchips gebildet wurden und die erste Metallschicht, die zweite Metallschicht und die dritte Metallschicht aus Titan, Kupfer bzw. einer Gold-Germanium-Antimon-Legierung (Antimon-Anteil: 0,1 Gew.-% beruhend auf der Menge an Gold-Germanium) hergestellt waren.Example 2 In the same manner as in Example 1, semiconductor devices were manufactured manufactured except that NPN transistor chips are formed in the silicon substrate and the first metal layer, the second metal layer and the third metal layer made of titanium, copper or a gold-germanium-antimony alloy (antimony content: 0.1 Wt .-% based on the amount of gold germanium) were produced.
Die Ausbeute war höher als bei den nach bekannten Verfahren hergestellten Erzeugnissen. Ähnlich wie bei Beispiel 1 zeigten die Halbleitervorrichtungen eine kleinere Kollektor-Emitter-Sättigungsspannung Vces und einen kleineren thermischen Widerstand Rth als die nach bekannten Verfahren hergestellten Halbleitervorrichtungen. Der thermische Widerstand Rth variierte nur ein wenig von Vorrichtung zu Vorrichtung.The yield was higher than that produced by known processes Products. Similar to Example 1, the semiconductor devices exhibited a smaller collector-emitter saturation voltage Vces and a smaller thermal one resistance Rth than those made by known methods Semiconductor devices. The thermal resistance Rth varied only a little from Device to device.
Zufolge des Antimon-Anteils in der Gold-Germanium-Antimon-Legierung war die Spannung Vces niedriger als bei den Halbleitervorrichtungen nach Beispiel 1.As a result of the proportion of antimony in the gold-germanium-antimony alloy the voltage Vces was lower than that of the semiconductor devices of the example 1.
Beispiel 3 Es wurden in der gleichen Weise wie bei Beispiel 1 Halbleitervorrichtungen hergestellt mit der Ausnahme, daß, wie in Fig. 5 dargestellt, auf die dritte Metallschicht 14 eine vierte Metallschicht 15 aus Gold, deren Dicke 500 A betrug, aufgedampft wurde. Die vierte Metallschicht 15 verhinderte eine Oxidation der dritten Metallschicht 14. Die Bindung zwischen der dritten Metallschicht 14 und dem Leiterrahmen 2 wurde deshalb nicht so stark beeinträchtigt.Example 3 In the same manner as in Example 1, semiconductor devices were manufactured except that, as shown in Fig. 5, on the third metal layer 14 a fourth metal layer 15 made of gold, the thickness of which was 500 Å, vapor deposited became. The fourth metal layer 15 prevented oxidation of the third metal layer 14. The bond between the third metal layer 14 and the lead frame 2 has been established therefore not so badly affected.
Die Ausbeute war höher als bei nach bekannten Verfahren hergestellten Erzeugnissen. Ähnlich wie bei Beispiel 1 zeigten die Halbleitervorrichtungen eine niedrigere Kollektor-Emitter-Sättigungsspannung Vces und einen niedrigeren thermischen Widerstand Rth als die nach bekannten Verfahren hergestellten Halbleitervorrichtungen. Der thermische Widerstand R th variierte nur wenig von Vorrichtung zu Vorrichtung.The yield was higher than that produced by known processes Products. Similar to Example 1, the semiconductor devices exhibited a lower collector-emitter saturation voltage Vces and a lower thermal Resistance Rth than the semiconductor devices manufactured by known methods. The thermal resistance R th varied little from device to device.
Beispiel 4 Es wurden in der gleichen Weise wie bei Beispiel 2 Halbleitervorrichtunqen hergestellt, mit der Ausnahme, daß, wie in Fig. 5 dargestellt, auf die dritte Metallschicht 14 eine vierte Metallschicht 15 aus Gold, die eine Dicke von 500 Å aufwies, aufgedamyçft wurde. Die vierte Metallschicht 15 verhinderte eine Oxidation der dritten Metallschicht 14.Example 4 In the same manner as in Example 2, semiconductor devices were manufactured except that, as shown in Fig. 5, on the third metal layer 14 a fourth metal layer 15 made of gold, which had a thickness of 500 Å, was deposited became. The fourth metal layer 15 prevented oxidation of the third metal layer 14th
Die Bindung zwischen der dritten rsetallschicht 14 und dem Leiterrahmen 2 wurde deshalb nicht ungünstig beeinflußt.The bond between the third metallic layer 14 and the lead frame 2 was therefore not adversely affected.
Die Ausbeute war höher als bei den nach bekannten Verfahren hergestellten Erzeugnissen. Wie bei Beispiel 1 zeigten die Halbleitewvorrichtungen eine niedrigere Kollektor-Emitter-Sättigungsspannung Vces und einen niedrigeren thermischen Widerstand Rth als die nach bekannten Verfahren hergestellten Halbleitervorrichtungen. Der thermische Widerstand Rth variierte nur etwas von Vorrichtung zu Vorrichtung. Zufolge des Antimon-Anteils in der Gold-Germanium-Antimon-Legierung war die Spannung V niedriger als bei den nach den Beices spielen 1 und 3 hergestellten Halbleitervorrichtungen.The yield was higher than that produced by known processes Products. As in Example 1, the semiconductor w devices showed a lower one Collector-emitter saturation voltage Vces and a lower thermal resistance Rth than the semiconductor devices manufactured by known methods. Of the thermal resistance Rth varied only slightly from device to device. As a result of the antimony content in the gold-germanium-antimony alloy, the voltage V was lower than the semiconductor devices manufactured according to Beices 1 and 3.
Die Halbleitervorrichtung nach der Erfindung weist die folgenden Vorteile auf: 1) Da anstelle einer Goldfolie eine extrem kleine Menge an einer Gold-Germanium-Legierung verwendet ist, um die Siliciumchips auf den Chipbefestigungsteilen zu befestigen, werden die Chips so exakt positioniert, daß beim Anbringen der Drähte keine Schwierigkeiten entstehen.The semiconductor device according to the invention has the following advantages on: 1) There instead of a gold foil an extremely small amount of a gold-germanium alloy is used to mount the silicon chips on the chip mounting hardware, the chips are positioned so precisely that there are no difficulties in attaching the wires develop.
2) Da keine Goldfolie benutzt wird, ist der Verfahrensschritt eine Goldfolie auf einem Chipbefestigungsteil zu plazieren oder eine Einrichtung zur Durchführung dieses Vorgangs nicht erforderlich.2) Since no gold foil is used, the process step is one To place gold foil on a die attach part or a device for It is not necessary to carry out this process.
3) Da die Menge an Gold, das ein sehr teures Metall ist und welches bei der Erfindung in Form einer Gold-Germanium-Legierung verwendet wird, außerordentlich gering ist, kann die Vorrichtung mit niedrigen Kosten hergestellt werden.3) As the amount of gold, which is a very expensive metal and which one is used in the invention in the form of a gold-germanium alloy, extraordinarily is small, the device can be manufactured at a low cost.
4) Da zwischen ein Siliciumsubstrat und eine Gold-Germanium-Legierungsschicht Metallschichten eingefügt werden, die gut sowohl mit Silicium als auch mit der Gold-Germanium-Legierung verbunden werden können, wird eine ausreichend starke Bindung bzw. Haftung zwischen dem Siliciumchip und dem Chipbefestigungsteil erzielt, wodurch die Zuverlässigkeit der Vorrichtung verbessert wird.4) Because between a silicon substrate and a gold-germanium alloy layer Metal layers are inserted that good with both silicon and can also be connected to the gold-germanium alloy, one will be sufficient strong bond between the silicon chip and the chip mounting part achieved, whereby the reliability of the device is improved.
5) Da als Lötmaterial eine Gold-Germanium-Legierung anstelle einer Gold-Silicium-Legierung verwendet wird, kann das Siliciumsubstrat auf einfache Weise in Chips unterteilt werden und das Siliciumsubstrat kann auf der oberen Fläche längs Würfellinien angerissen werden, nicht auf den Legierungsschichten. Die Verwendung der Gold-Germanium-Legierung erleichtert das Brechen des Siliciumsubstrats in Chips aus dem folgenden Grund. Der Siliciumgehalt in der eutektischen Gold-Silicium-Verbindung beträgt 2,85 Gew.-%, während der Germaniumgehalt in der eutektischen Gold-Germanium-Verbindung 12 Gew.-% beträgt. Die spezifischen Dichten von Gold, Silicium und Germanium sind 19,3; 2,42 bzw. 5,46. Somit nimmt volumenmäßig Silicium 19 % der eutektischen Gold-Silicium-Legierung ein, während Germanium 33 % der Gold-Germanium-Legierung einnimmt. Offensichtlich ist damit volumenmäßig der Goldgehalt in der eutektischen Gold-Germanium-Legierung viel kleiner als in der eutektischen Gold-Silicium-Legierung.5) Since a gold-germanium alloy instead of a Gold-silicon alloy is used, the silicon substrate can be easily can be divided into chips and the silicon substrate can be longitudinally on the upper surface Cube lines are marked, not on the alloy layers. The usage The gold-germanium alloy makes it easier to break the silicon substrate into chips for the following reason. The silicon content in the eutectic gold-silicon compound is 2.85 wt .-%, while the germanium content in the eutectic gold-germanium compound Is 12% by weight. The specific densities of gold, silicon and germanium are 19.3; 2.42 and 5.46, respectively. Thus, silicon takes up 19% by volume of the gold-silicon eutectic alloy while germanium makes up 33% of the gold-germanium alloy. Apparently is thus the gold content in volume terms in the eutectic gold-germanium alloy much smaller than in the eutectic gold-silicon alloy.
6) Im allgemeinen wird das Metall aus der Gasphase unter einem Druck von 10 1 bis 10 2 Torr niedergeschlagen bzw.6) In general, the metal is released from the gas phase under pressure from 10 1 to 10 2 Torr.
abgeschieden. Die Temperatur, bei der Gold einen derartigen Dampf- bzw. Gasdruck aufweist, ist nahezu gleich der Temperatur, bei der Germanium einen solchen Dampfdruck hat. Mit anderen Worten sind die Dampfdrücke von Gold und Germanium bei einer für die Dampfabscheidung von Gold und Germanium geeigneten Temperatur nahezu gleich groß. Anders als bei Gold-Silicium oder Gold-Antimon kann Gold-Germanium leicht ohne fraktionelles Verdampfen aufgedampft werden.deposited. The temperature at which gold produces such a vapor or gas pressure, is almost equal to the temperature at which germanium has a has such vapor pressure. In other words, they are the vapor pressures of gold and germanium at a temperature suitable for the vapor deposition of gold and germanium almost the same size. Unlike gold-silicon or gold-antimony, gold-germanium can easily vaporized without fractional evaporation.
Z. B. hat der Dampfdruck von Gold und Germanium bei 2000 K den Wert 5,5 x 10 Torr (siehe RCA-Review, Juni 1969, 5. 292 und 293). Der Dampfdruck von Silicium hat bei 2000 K einen Wert von 3,0 x 10 Torr.For example, the vapor pressure of gold and germanium has the value at 2000 K. 5.5 x 10 Torr (see RCA Review, June 1969, pp. 292 and 293). The vapor pressure of Silicon has a value of 3.0 x 10 Torr at 2000 K.
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DE3124879A1 (en) * | 1980-07-18 | 1982-03-18 | Naamloze Vennootschap Philips' Gloeilampenfabrieken, 5621 Eindhoven | "SEMICONDUCTOR ARRANGEMENT" |
DE3110080A1 (en) * | 1981-03-16 | 1982-09-30 | Siemens AG, 1000 Berlin und 8000 München | Method of joining a semiconductor body to a metallic system carrier, and semiconductor arrangement produced thereby |
FR2531106A1 (en) * | 1982-07-29 | 1984-02-03 | Ates Componenti Elettron | METHOD FOR METALLIZING THE REAR SIDE OF A SILICON WAFER |
EP0457344A2 (en) * | 1990-05-18 | 1991-11-21 | Kabushiki Kaisha Toshiba | Semiconductor light-emitting device |
DE4107660A1 (en) * | 1991-03-09 | 1992-09-17 | Bosch Gmbh Robert | METHOD FOR MOUNTING SILICON PLATES ON METAL MOUNTING SURFACES |
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EP0585084A1 (en) * | 1992-08-28 | 1994-03-02 | AT&T Corp. | Permanent metallic bonding method |
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Cited By (27)
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DE3124879A1 (en) * | 1980-07-18 | 1982-03-18 | Naamloze Vennootschap Philips' Gloeilampenfabrieken, 5621 Eindhoven | "SEMICONDUCTOR ARRANGEMENT" |
DE3110080A1 (en) * | 1981-03-16 | 1982-09-30 | Siemens AG, 1000 Berlin und 8000 München | Method of joining a semiconductor body to a metallic system carrier, and semiconductor arrangement produced thereby |
FR2531106A1 (en) * | 1982-07-29 | 1984-02-03 | Ates Componenti Elettron | METHOD FOR METALLIZING THE REAR SIDE OF A SILICON WAFER |
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US6761420B2 (en) | 1998-09-03 | 2004-07-13 | Ge Novasensor | Proportional micromechanical device |
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US7851910B2 (en) | 2003-04-01 | 2010-12-14 | Infineon Technologies Ag | Diffusion soldered semiconductor device |
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US9772235B2 (en) | 2012-03-16 | 2017-09-26 | Zhejiang Dunan Hetian Metal Co., Ltd. | Method of sensing superheat |
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