DE2929597A1 - Alarm indication signal recognition circuit - connects digital signal from transmitter to first input of NOR-circuit, whose output goes to counter input - Google Patents

Abstract

The alarm indication signal to be recognised is distorted by bit defects and appears instead of a digital signal, while the circuit also recognises the drop-out of a digital signal despite appearing interference pulses. The digital signal (J1) from the transmitter is supplied to the first input of a NOR-circuit (01). The latter output is coupled to an input (Cp) of a counter (Z1), whose output is coupled to the D-input of a flip-flop circuit. The clock pulse (Tp), determining the measuring time periods, is connected to the clock pulse inputs of two flip-flop circuits (D - FF1, D- FF2), as well as to the input of a delay stage (T). The latter output is coupled to the inputs of two counters (Z1,Z2). The decoded and inverted digital signal (J2) lies at the first input of an AND-circuit (U), at whose second input lies the clock pulse derived from the digital signal (J1). The AND-circuit output is connected to further logic circuitry for obtaining the PCM signal drop-out criterium.

Description

Circuit arrangement for recognizing an AIS signal

and the failure of a digital signal. The invention relates to a Circuit arrangement according to the preamble of claim.

In a PCM system, when one occurs, the entire multiplex signal relevant error at the next interface through the entire multiplex signal replaced an AIS signal (Alarm Indication Signal). This consists of a continuous Sequence of bits of the status "1". However, bit errors occur during transmission Even with the AIS signal bits with the status "O" have a correct AIS detection make more difficult. The correct detection of a PCM signal failure is also made more difficult. if pulses are still received due to bit errors.

From DE-AS 27 50 011 a circuit arrangement is known which can detect an AIS signal and a PCM signal failure. This circuit is relative elaborate as they are two Low pass filter used. In addition, the Circuit has the disadvantage that the AlS criterion or the PCM signal failure criterion present at the output of the circuit as a dynamic variable, which is important for further processing these signals is not favorable.

The invention is based on the object of a circuit arrangement for the reliable detection of an AIS signal and the failure of a digital signal specify which can be implemented with little effort and for which the AIS criterion respectively.

digital signal failure criterion is present as a status signal at the output.

The object is achieved as described in the claim.

The invention is explained in more detail below with reference to the figures.

Fig. 1 shows an embodiment of the arrangement according to the invention.

Fig. 2a shows a timing diagram for signal failure, so that an alarm is triggered will.

Fig. 2b shows a timing diagram for a signal with no alarm is triggered.

Fig. 2c shows a pulse plan in which an AIS signal is detected and Alarm is triggered.

Fig. 2d shows a pulse plan in which no AIS signal is detected and so that no alarm is triggered either.

Within the test time, which is determined by the clock Tp, counts the counter Z1 the binary "1" pulses of the digital signal J1. According to the The number of cells in the counter Z1 must be correspondingly large within the test time binary "1" pulses are present so that a binary "1" can be present. If the counter reaches this State within the test time, then the counter input Cp via the NOR circuit Q1 on the state held binary "O" so that the counter Z1 can no longer count. The binary 1 at the output Q12 of the counter Z1, the positive edge of the clock pulse Tp controlled in the flip-flop D-FF1 and appears at the Q output of the flip-flop as a binary i "state, which means no alarm", i.e. the message flow is not interrupted.

At the same time, the Q output of the first flip-flop D-FF1 the second flip-flop D-FF2 enabled.

If fewer binary "1" pulses occur in the message signal J1, then so that the counter Z1 does not count up to the intended cell, then the output remains Q12 in the binary "O" state.

This state is with the clock pulse Tp in the flip-flop D-FF1 taken over, so that the state binary "O" appears at the Q output of the flip-flop D-FF1. This means "alarm", i.e. the digital signal is not received. Corresponding the second trigger circuit D-FF2 is blocked via the Q output of the trigger circuit D-FF1, so that an AIS alarm cannot be given by mistake.

If an AIS signal is received instead of the digital signal, then there is the HDB3 decoded and inverted signal J2 consists essentially of binary "O", the are only interrupted by glitches. If these glitches occur at the same time the binary "1" of the clock T derived from the message signal, then become the interference pulses from counter Z2 are counted. If there are few interference pulses within the test time so that the counter Z2 does not count up to the intended place Q22, then will the Q output of the flip-flop D-FF2 is set to binary "O". This means "AIS alarm", i.e. the AIS signal is recognized.

If many glitches occur within the test time, then counts the counter corresponds to Q22 and the Q output of the flip-flop is a binary one 1 at. This does not mean an AIS alarm ", i.e. it is assumed that the digital signal was sent.

The delay circuit T ensures that the count comes first from Z1 or Z2 to the flip-flop circuit D-FF1 or

D-FF2 is accepted before the counters are reset and from start counting again.

Claims (1)

Method for recognizing the occurrence of a with bit flawed AIS signal instead of a digital signal and for detection a failure of the digital signal despite the occurrence of glitches, whereby within of a test cycle determining the error rate, state 11011 of the digital signal for AIS detection and the status "1" of the digital signal for signal detection is counted via a counter, and with one under a defined Result lying value either with predominant occurrence of the status "1" AIS signal, AISK, and if the status "O" predominantly occurs, signal failure, F to K, is reported is, characterized in that the coming from the transmitter digital signal (J1) dem first input of a first NOR circuit (01) is supplied that the output of the first NOR circuit (01) connected to the counting input (Cp) of a first counter (Z1) is that an output of the first counter (Z1) with the D input of a first flip-flop (01) is connected that the measuring times defining clock (Tp) with the clock input of the first flip-flop (D-FF1) and with the clock input of a second flip-flop (D-FF2) and connected to the input of a delay stage (T) that the output the delay stage with the R input of the first counter (Z1) and with the R input a second counter (Z2) is connected that the decoded and inverted digital Signal (J2) is present at the first input of an AND circuit (U) that the second input the AND circuit (U) the clock (T) derived from the digital signal (J1) is applied is that the output of the AND circuit (U) with the first input of a second NOR circuit (02) is connected that the output of the second NOR circuit with the counting input (Cp) of the second counter (Z2) is connected that an output of the Counter (Z2) with the D input of the second flip-flop (D-FF2) and with the second Input of the second NOR circuit (02) is connected that the Q output of the first Flip-flop (D-FF1) connected to the R input of the second flip-flop (D-FF2) is that at the Q output of the first flip-flop (D-FF1) the PCM signal failure criterion (F to K) and that the AIS criterion at the Q output of the second flip-flop (D-FF2) (AISK) is present.