DE2920079C2 - Circuit arrangement for amplifying a low-frequency pulse-width-modulated square-wave signal - Google Patents

Description

50

The invention deals with a so-called class D amplifier, as it is also called a PDM or known as a PWW amplifier. In this context reference is made to "Elektor" (December 1978), pages 36 to 39.

A low-frequency (audio frequency) pulse-width-modulated amplifier is connected to the input of such an amplifier Rectangular sign! created. At the output, the amplified low-frequency signal is transmitted via an integrating Low-pass filter obtained, so that a loudspeaker is then directly connected to the low-pass filter can be.

This differs from conventional AF output stages, which are also used in so-called switching amplifiers as modified, complementary emitter sequence are formed, this circuit arrangement consists of two switches that the Switch consumers alternately to the negative pole or the positive pole of the operating voltage. Though that Principle of the PDM amplifier has been known for a long time, its implementation has failed so far due to the relative long switching times of the available semiconductor components. With the appearance of However, VMOS and DMOS field effect transistors with switching times of less than 5 ns are PDM amplifiers possible with clock frequencies from 100 to 500 kHz.

Preferably, therefore, when realizing the circuit arrangement according to the invention, VMOS- and DMOS field effect transistors are used, although other field effect transistors are also used with similarly favorable switching times are useful.

The invention thus relates to a circuit arrangement for amplifying a pulse width modulated with low frequency Square-wave signal according to the preamble of claim 1, as derived from the above Reference "Elektor" (December 1978) was known.

The object of the invention is to provide a simple and less complex circuit arrangement whose Function is largely independent of the voltage of the power supply. In addition, the output power should be of the circuit arrangement with the same input signal essentially depends on the resistance value the load resistance, d. H. of the loudspeaker and the operating voltage.

This object is achieved according to the invention by what is stated in the characterizing part of claim 1 Circuit measures solved.

The circuit arrangement according to the invention and its advantages are described below with reference to the figures The circuits shown in the drawing are explained.

In the circuit arrangement according to the invention, the source-drain paths of a P-channel field effect transistor Tp and an N-channel field effect transistor Tn are connected in series, the drain electrodes D being connected and the connection point of the two field effect transistors as the output of the circuit arrangement is to be considered according to the invention. An integrating low-pass filter consisting of the coil L and the capacitor CA is connected to this output in a known manner. switched in front of the loudspeaker Sp . According to FIG. 1 is a separating capacitor CZ in series with this arrangement.

The source electrode 5 of the P-channel field effect transistor Tp is connected to the positive pole + Ub and the source electrode S of the N-channel field effect transistor is connected to the negative pole (-). The negative pole can, for example, be connected to ground, as indicated in the figure. While the gate electrode of the P-channel field effect transistor Tp is connected to its source electrode via a parallel connection of a discharge resistor RA with a clamping diode D 2 , the gate-source path of the N-channel field effect transistor Dn is in the same way by means of the Parallel connection of a further discharge resistor R 3 bridged with a further clamping diode DX. The two clamping diodes DX and D 2 are polarized so that in the P-channel field effect transistor 7p the clamping diode D 2 in the flow direction from the gate electrode to the source electrode Sund the clamping diode DX in the N-channel field effect transistor Tn in the direction of the source electrode S to the gate electrode in the direction of flow. As a result, the P-channel field effect transistor Tp is controlled with negative and the N-channel field effect transistor Tn with positive voltage pulses. This control takes place capacitively in phase via the two coupling capacitors C1 and C2 at the fan input

the gate electrodes of the field effect transistors via the two protective resistors R 1 and R 2, which in one embodiment of the circuit arrangement according to the invention had a resistance value of 33 ohms, while the coupling capacitances C 1 and CI were 0.1 μΡ s. In the exemplary embodiment of the circuit arrangement according to the invention, the discharge resistors R 3 and R 4 have resistance values of 100 k ohms.

The isolating capacitor C3 can be omitted (bridged) if two identical, series-connected operating voltage sources (+ Ub, - Ub) are used, between their connection point and the low-pass filter, the loudspeaker is connected, as shown in FIG. 2 illustrates

The field effect transistors used were BD 512 (P-channel VMOS field effect transistor) for Tp and BD 522 (N-channel VMOS field effect transistor) for Tn

The switch-on resistances Ron of the two »switching branches should be the same as possible. However, since the Ron resistances of P-channel VMOS transistors are much larger (approx. Twice as large) as those of N-channel of the same power, correspondingly more P-channel VMOS field effect transistors are connected in parallel of the invention also to the use of at least one further field effect transistor of the same conductivity type, which is connected in parallel to at least one of the field effect transistors Tn or Tp. So many of the N- or P-channel field effect transistors have to be connected in parallel that a switching resistor Ron is preferably less than a tenth of the output resistance or the loudspeaker resistance. Efficiency levels of more than 90% can then be achieved. The maximum output power is calculated according to the equation

whereby the switch-on resistance Ron of the field effect transistors is not taken into account.

An advantage of the circuit arrangement according to the invention is that the pulse-width-modulated signal is only required with an amplitude of 12 to 15 V single-phase. Efficiencies of 80 to 97% Distortion factors of less than 0.2% (without negative feedback!) Can be achieved. If there is no control signal Both transistors are blocked, so that the circuit arrangement protects itself and if there is no control no electricity can flow.

1 sheet of drawings

Claims (3)

Patent claims: 1.Circuit arrangement for amplifying a low frequency pulse width modulated square wave signal, which is applied to the input of the circuit arrangement and two working in antiphase in series field effect transistors located between the positive and negative pole of the power supply controls, wherein the connection point of the field effect transistors as the output of the circuit arrangement serves, characterized that complementary field effect transistors (Tp, Tn) of the enhancement type are used as field effect transistors, that the source electrode (S) of the PK.anal field effect transistor (Tp) on the positive pole (+ Ub) and the source electrode (S) of the N-channel field effect transistor (Tn) on the negative pole (-) of the power supply, that in each of the field effect transistors the gate electrode capacitively with the input (E) of the circuit arrangement and via a respective clamping diode (D 1, D 2) and a resistor (R 3, R 4) connected in parallel to the source electrode (S) is connected in such a way that with the P-channel field effect transistor (Tp) the clamping diode (D 2) in the flow direction between the gate electrode and the source electrode (S) and with the N-channel field effect transistor (Tn) the clamping diode ( Di) lie in the flow direction between the source electrode ^ and the gate electrode, so that the P-channel field effect transistor (Tp) is controlled with a negative voltage pulse and the N-channel field effect transistor (Tn) with a positive voltage pulse. 2. Circuit arrangement according to claim 1, characterized in that at least one of the field effect transistors (Tn. Tp) is connected in parallel with at least one further field effect transistor of the same conductivity type of the enhancement type. 3. Circuit arrangement according to claim 2, characterized in that so many N-channel field effect transistors or P-channel field effect transistors are connected in parallel that the input resistance Ron of each of the parallel connection of the field effect transistors of the same conductivity type is less than '/ ίο of the load resistance or the loudspeaker -Resistance is.