DE2853161A1 - DIGITAL DEVICE FOR DETERMINING THE STATIONAL VALUE OF AN ANALOG SIGNAL - Google Patents

Description

Dipl.-P ¹ "/ - K. Luyken

"β M Ü NC" '- "EN a · TAL' 2 7

JE [Γ., -. .. ', - -' eEXW3 53S

Institut kibernetiki Akademii Nauk Urakinskoj SSR Kiev / USSR

P 73 798-E-61 December 8, 1978 L / Kdg

DIGITAIE FACILITY 2-UR DETERMINING THE STATIONARY O WEB2ES AN ANALOG SIGNAL

The invention relates to digital computer technology and relates in particular to digital devices ζ for determining the steady-state value of an analog signal

The invention can be used in information systems.

processing used ..being in which the information

for parameters

is recorded by - donors of technological processes, in particular for the determination of digital

E.g. jS-y

r, valley shape) of the temperature of liquid steel, which with a

Immersion thermocouple is measured.

In the technology of information preprocessing systems There are a number of tasks that require the steady-state value of an analog signal to determine in a disorder background and that To present the result in digital form

Such a task arises in particular when measuring the temperature of liquid η metal, for example steel a temperature sensor that is briefly immersed in the metal

BATH ORIGINAL

285316!

will «In this is; it needed to be determined by donors ^he ~ midsection signal value in digital form which is established after the completion of an inertia caused by behavior of the temperature sensor transition process ·

There is known a digital computing device which is used for parameter control of liquid metal

O This device can be used to determine (in the digital

Talform / of the stationary value of the analog signal, e.g. B ₉ can be used to measure the temperature of liquid metal with an immersion thermocouple.

This device contains a converter of the

one
Analog signals in pulse number code, one output

of the code pulses, which correspond to a positive increase in the analog signal, and an output of the code pulses, which correspond to a negative increase in the analog signal, s ~ \ , a clock pulse generator, a synchronizing

part that determines the timing of code-and-clock pulses is, and its inputs to the outputs of the converter of the analog signal in the pulse number code and on the output of the clock pulse generator is switched on · To determine local increases in the analog signal A first and a second threshold counter are used, their digit outputs to the inputs of the zero state deciphering

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-f-

when the silence counter is switched on · The outputs the deciphers are connected to the computation blocking inputs switched on when subtracting the corresponding threshold counter. The establishment shows also a time interval discriminator for the selection of Intervals between successive points in time, if a local increase in the analog signal is a specified Size reached. Inputs of the initial setting of the ^ eit ^ interval discrirainators are connected to the overflow outputs of the The threshold counter switched on. With the little entrance of the

Zeitintervalldikrlminators is the output for synchronized Clock pulses of the synchronizing part electrical tied together. The outputs for. synchronized code pulses of the synchronization part are electrically connected to the threshold counters and a ke ve rs ie r counter. The last ■: '. is used to generate a parallel code of the result. A Hegister whose information input to the job openings of the reversing counter and its control input connected to the output of the time interval discriminator guarantees the retention of the calculation

to .

result. The reimbursement stored in the register

The result is a digital display panel in digital form displayed.

When the temperature of a metal is measured, a code is generated in the Keversiarz counter, which is the one on the temperature sensor

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read running indications of the analog signal is proportional. If positive or negative signal increases exceed a given uncertainty threshold S ₀ against the signal deviations from a steady-state value, which are caused by disturbances, then pulses are generated at the overflow outputs of the threshold counter.

- * valldiskriminator, which controls the synchronized clock pulses

counts, in the initial state «If during a specified period of time T <>, which is set with the time interval discriminator, the signal increase does not exceed the given threshold S ₀ , a signal occurs at the output of the time interval discriminator. This indicates that the analog signal has reached the stationary value. The parallel code, which is contained in the Keversier counter at this point in time, allows the stationary vVert of the analog signal to be evaluated. The signal that comes from the output of the time interval discriminator to the control input of the register enters the last information about the stationary value of the analog signal

1st be observed that the parallel code registered in the register of the can. Analogsignais by ± 0.5 o different from a code of the stationary value ·

0300,28 / 0021

■ '.γ

The maximum error in the determination of the steady-state value of the analog signal by the device described must therefore not be less than 0.5 & c

will increase the insensitivity threshold ζ> _ΰ,

. this

as follows from what has been said, leads to a

at

Maximum error would increase in the determination of the stationary value of the analog signal. The accuracy of the determination the steady-state value of the analog signal therefore depends essentially on the application of the described device. - borrowed, from-an interference level.

Thus, ₂ 'as in the temperature measurement of molten steel by the known temperature sensor used in the liquid. Steel are dipped (short-term), the interference level of a deviation of the analog signal of about 1O ⁰ C be equivalent · In this case, it is necessary to set a deadband threshold 6 ₀ of 1O ^e C, which liquid to an error of temperature measurement steel of Jt, 5 ^e C can lead · When melting and casting ^of Ver C "uali

an in

In fact, such temperature measurement errors are not permitted.

The purpose of the invention is to eliminate the specified deficiency, and in particular the measurement accuracy of the steady-state value of the analog signal in the background of the fault

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reason to increase

The invention is based on the object of a. due to the simplest components and units the digital computer built up

direction for determining the steady-state value to create an analog signal that allows the steady-state value evaluate the analog signal as an average value between the maximum and minimum values of the analog signal, the changes of which do not exceed a specified value during a specified period of time

This object is achieved in that the digital

one

Device for determining the steady-state value of analog signals, the one converter of the analog signal into a pulse number code, which has an output for a positive increase of the analog signal corresponding code pulses and an output for a negative increase in the analog signal has corresponding code pulses, a (clock pulse generator, a reversing counter for generating a parallel

the

lelcodes ^for calculation results, an iahlance part for displaying the calculation result, which is electrically connected to the digit outputs of the ke ver it r counter

a
den is, first and second threshold numbers that go to

Determination of local analog signal increases are used, zero state decoders of the first and second threshold counter, the input of which is connected to digit outputs of the threshold

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2553161

-y-

, / fe.

counters and their outputs are connected to inputs of the computation blocking during the subtraction of the first and second threshold counter, an is it inter valldiskriminator for the selection of intervals between two successive times _f if the local

Increase in analog signal reaches a specified size, where from

the inputs, the beginning of which is connected to the overflow outputs of the threshold ^{counter and} a synchronization part for the time distribution of code and clock

contains,

pulses, ^{of which} two inputs are connected to the outputs of the converter of the analog signal into the pulse number code $ l-

while
the third input of the synchronized ils U-St /

connected to an input of the clock pulse ^{generator and} outputs ^for synchronized code pulses of the synchronization part ^ are> electrically connected to the threshold counters and the ßversiersaähler; and an output for synchronized. Clock pulses of the synchronization part list with which

lis t, n ^

Time interval! Discriminator electrically connected ^

according to the invention a frequency divider in

.. and

ratio 1 $ 2, has three NOT circuits, seven AND circuits, whereby

In the device according to the invention, the time interval discriminator has an information output, to the first outputs of the first, second, third, fourth AND circuit and via the «rst« NOT-Sohal-

030028/00 21

■ Λ-

device to the first input of the fifth AND circuit

while

is off, the output for synchronized The clock pulse «of the synchronizing part ^ is at the second Input of the first AND circuit switched on, the threshold counter have additional subtraction inputs,

to which the output of the first AND circuit is connected

one
is, electrical coupling of the outputs of the synchronized code pulses of the synchronization part with the threshold counters and the reversing counter is provided by the sixth and seventh AND circuit

and the output for synchronized code pulses corresponding to a positive increase in the analog signal to the first input of the sixth AND circuit, the output for synchronized code pulses corresponding to a negative increase in the analog signal to the first input of the seventh AND circuit is switched on, f ~ \ the second inputs of the sixth and seventh AND circuit / are ') connected together with the first input of the fifth AND circuit ¹ , the output of the sixth AND circuit to addition inputs of the lie ve r they r count rs and The output of the seventh AND circuit is connected to subtraction inputs of the reversing counter and the first threshold counter and to an addition input of the second

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ORIGINAL INSPECTED

/ 13-

is turned on, a threshold counter! electrical doubling of the Output for synchronized clock pulses of the synchronization part with the iieitintervalldiskriminator '

" is provided

the fifth AND circuit, at whose second input the

Output of the synchronizing part switched on

while ..

is, the output of the fifth AND circuit ^ isVan the

Kitchen input of the time interval discriminator switched on ', the second inputs of the second and the third AND circuit via the frequency divider in proportion

1 ': 2 at the output for synchronized clock pulses of the

. are

Synchronizing part switched on, the output of the zero state decipherer of the first threshold counter 'to the third input of the third AND circuit, end second input of the fourth AND circuit and via the second mCHT circuit to the third input of the two

■ is
th AND circuit switched on, the output of the zero

was on the second threshold counter

the fourth input of the second AND circuit to which third input of the fourth AND circuit and via the third NOT circuit to the fourth input of the third

is
th AND circuit switched on, the outputs of the second

or third AND * Sohultunken an exnen

additional subtraction input and an additional

are and

Addxtion input of the Keversier counter switched on

knows

Number display part a tax input on the at

let the output of the fourth AND circuit be connected.

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In the following, the gist of the invention will be clarified by detailed description of the invention with reference explained on the accompanying drawings It shows:

1 shows a structural circuit of the digital device according to the invention for determining the stationary value of the analog signal;
s, FIG. 2 shows a characteristic curve section of

Analog signal change in the event that the point of the characteristic curve segment in which the response of the time interval discriminator took place in which Midway between the points of the maximum and minimum value of the analog signal on the section;

in . Fig. 3 is essentially the same as Fig. 2, however

in the event that the point of the characteristic curve section in which the response of the time interval discriminator takes place lies above the center line between -J the points of the maximum and minimum value of the analog signal on the section;

in however .. Fig. 4 essentially the same as Fig. Z, for

the case that the point of the characteristic curve section, in which the response of the time interval discriminator takes place, below the center line between the points of the maximum and minimum value of the analog signal lies on the section. The digital device for determining the stationary

030028/0021

Value of the analog signal, as shown in Fi ^. 1 "is shown, contains a converter 1 of the analog signal into a pulse number code, a clock pulse generator 2, a synchronizing part 3y which is intended for the time distribution of the code and clock pulses, threshold counter 4, 5, a zero state decipherer 6 of the threshold counter 4, a zero state decipherer 7 äse threshold counter 5, a 2ielt interval discriminator 8, a reversing counter 9, a number display part 10, three NOT circuits 11, 12, 13, seven AND circuits 14, 15, "16, 17, 18, 19, 20 and a frequency divider 21 in relation 1: 2.

The converter 1 of the analog signals in the number of pulses <code contains an input 22, an output 23, which for Output of the code pulses, which correspond to a positive increase in the analog signal, and an output

O 24, which is used to output the code pulses that a

^The negative increases in the analog signal correspond to · Outputs 23 and 24 are connected to the synchronizing part J5. The output 2 $ of the clock pulse generator 2 is also connected to the synchronization part 3. The output 26 for synchronized clock pulses of the synchronization part 3 is connected to the input of the AND circuit 14, to the input of the AND circuit 15 and to the input of the frequency divider 21 in a ratio of 1s2. The output 27 of the synchronizing

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-τέ- ■ / 16.

sierteils 3 »that for the output of the synchronized code impulses serves that a positive increase of the .Analogsignals correspond at the input 22 of the converter 1 is connected to the input of the AND circuit 19. The exit 28 of the bynchronisierteils 3i to issue the synchronized code pulses that have a negative -. Increase in the analog signal at input 22 of converter 1

is to the input of the AND circuit 20

the
turned on. Inputs 29 »30, 31 of the AND circuits

20, 19t 14 * are connected together · The output 32 of the AND circuit 14 is connected to the Re ehe neingang of the time interval discriminator 8 · The output 33 of the AND circuit 15 is connected to additional inputs of the threshold counter 4, 3 · The output 34 of the AND circuit 19 is connected to the addition input of the tail counter 5, to the subtraction input of the threshold counter 4 and to the addition input of the Kevers ie count rs 9. The output 35 of the AND circuit 20 is connected to the subtraction input of the threshold counter 5 »sji the addition input of the surge counter 4 and to the subtraction input of the Keversier counter 9.

the
switched. Digit outputs 3 & of the threshold counter 4 are connected to the inputs of the decipherer 6. Dqs overflow input of threshold counter 4 is to input 37 of the initial setting of the 2 * 3 it inter valldiskrimi-

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ORIGINAL INSPECTED

nators 8 switched on. The output of the decipherer 6 is at the input ^ 8 of the calculation blocking at the Subtract the threshold counter 4 to input 39 the AND circuit 16, connected to the input 40 of the NOT circuit 13 and to the input 41 of the AND circuit 18. The digit outputs 42 of the threshold counter 5 are connected to the inputs of the decipherer 7. The overflow input of the threshold counter 5 is * to the Input 43 of the initial setting of the time interval discriminator 8 switched on. The output of the decipherer 7 is at the input 44 of the computation blocking the subtraction of the threshold counter 5t to the input 45 of the NOT circuit 12 to the input 46 of the AND circuit 17 and connected to the input 47 of the AND circuit 18. The information output of the time interval discriminator 8 is the NOT-Schal-O at input 48 device 11 and to the inputs 49, 50, Jj1 of the AND circuits

16, 17, 18 switched on accordingly. The outcome of the NOT circuit 11 is connected to input 31 of the AND circuit 14 switched on j the output of the NOT circuit 12 is connected to the input 52 of the AND circuit 16, and the output of the NOT circuit 13 is connected to the input 53 of the AND circuit 17 is turned on. The output of the frequency divider 21 in the ratio 1 * 2 is to the input

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■ / if

or gears 54, 55 of the AND circuits 16 17 accordingly

turned on. The output 56 of the AND circuit 16 is connected to the additional subtraction input of the reversing counter 9 and the output 57 of the AND circuit 17 is connected to the additional addition input of the reversing counter 9. The output 58 of the AND circuit 18 is connected to the control input of the number display - ^ J partly 10 switched on. The position exits 59 of the reverse

metering counter 9 are connected to the information input of the number display part 10 switched on

^The single-wave counters 4, 5 are designed as counting circuits that are set to the counting factor that corresponds to the specified insensitivity threshold $ _c to signal deviations from the stationary value caused by interference.

The time interval discriminator 8 is in the form executed a counting circuit whose counting factor corresponds to a given time interval.

The digital device for determining the stationary

one
nary value of the analog signal works as follows · A

Analog signal arrives at input 22 of converter 1

unifying analog signal in pulse number code · Depending on the character of the analog signal increase, the code pulses are either at output 23 or at output 24 of converter 1 of the analog signal in the pulse number code generates

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ORIGINAL INSPECTED

JJ.

number of code pulses is an increase in the analog signal proportional · The code pulses arrive at the outputs 23 and 24 at the first and second inputs of the synchronization part 3 · To the third input of the Synchronizing part 3 get the clock pulses from the output 25 of the clock pulse generator 2 · In the synchronization part 3 the time distribution of the code and clock pulses takes place. the synchronized (time-distributed) code-and-clock pulses are correspondingly at the outputs 26, 27 and at the output 28 of the synchronizing part 3 generated The time interval discriminator is used for the initial state 8 ^ in the initial state ^ with the button of the initial setting (not shown in the drawing) or automatically 'set As a result, at the information exit of the time interval discriminator 8 a low one Prevention potential generated by the UMD circuits Q 15, 16, 17 and 18 blocks and via the NOT circuit 11

the AND circuits 14, 19 and 20 unlocked.

The synchronized code pulses come from the synchronization part 3 via the open AND circuits 19, 20 to the addition input or to the subtraction input of the Reverse Counter 9 · As a result it becomes in him the parallel code of an instantaneous value of the analog signal The same code pulses are sent to the Addl

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I O I

. 20 ·

tion and subtraction inputs of the threshold counter 4, 5 If the increase in the analog signal is positive, the code pulses from the output 34 of the UWD circuit 19 reach the addition input of the revision counter 9 and the subtraction input of the threshold counter 4 Is the Increase in the analog signal negative ₍ the code pulses from the output 35 of the AND circuit 20 to the subtraction input of the EeVersiex counter 9 »the subtraction input of the threshold counter 5 and the addition input of the threshold counter 4. If a zero is generated in the threshold counter 4 Another subtraction calculation is blocked in this counter with the help of the decipherer 6. In the same way /, if a zero is generated in the threshold counter 3, (another subtraction calculation is blocked in this selector with the help of the decipherer 7 A code is thus created in the threshold counter 5 that a local positive growth in .Analogsignals in · relation to t ^he local minimum ^ ^ea signal s r ve run corresponds, and in the threshold counter 4, a code is generated, the log a local negative growth of .ana Signa Is corresponds with respect to d ^as local maximum of the waveform "If any of these local increases the specified threshold & überschreibet is the overflow output of a corresponding speed counter generates a pulse that the

030028/0021

ORIGINAL INSPECTED

- y? - • 34 ·

Time interval discriminator 8 set to the initial state · The line input of the time interval discriminator 8 is supplied with synchronized clock pulses via the open AND circuit 14. On the lnforraationsausgang of Zeitintervalldiskriininators 8, a triggering potential only be generated when, during a given period of time L _Q with a pulse he ,. which arrives from the overflow output of one of the threshold Ie η counter 4, b , is set in the initial state ^ iicht ^. In the course of the change in the analog signal, the. Time interval discriminator 8 is set to the initial state ^ edesraai ^ as soon as the increase in the analog signal during a specified period of time L exceeds a size β>. After the analog signal reaches the steady state value, exceed its positive and negative growth is not a size S ₀ · After the course ei ** ner period L _q9 £ era9 ^ss qji state of the last setting of Zeitintervalldiskriminators 8 in the beginning, is being built on its Information output the trigger potential The prevention potential that is generated at the output of the NOT circuit 11 blocks the AND circuits 14, 19, 20, as a result of which they arrive

to

the Kodeimpulsejzum reverse counter 9 and the threshold counters 4, 5 * not * the same time, stops outputting the clock pulses ^to the ßecheneingang of Zeitintervalldis-

0300 287 0021

kriminators δ from, whereby the .Auslösungspotential an its information output until the next measurement cycle of the stationary value of the analog signal is retained «In addition, unlocks the trigger potential that on the information output of the time interval discriminator 8 is generated, the AND circuit 15 · The synchronized Clock pulses come from the output 26 of the Synchrunisierteils 3 via the AND circuit 15 on the additional subtraction inputs of the threshold counter 4 and 5

Is the value of the analog signal at which the blocking des. Keve r sie r count rs 9 and the threshold counter and 5 by a signal from the time interval discriminator 8 took place., In the middle between the points of the maximum and minimum value of the analog signal on the charak teristic section of the curve showing the time-dependent O speed of the signal (Fig. 2), so is the content

Δ X ^ of the threshold counter 5 when blocking is the same the content Δ Xp of the threshold counter 4

The clock pulses, which are sent via the AND circuit 15 to the additional subtraction inputs of the threshold counter 4 and 5 change the content of these threshold counters · As soon as a zero is generated in the threshold counters block the bull state decoders 6 and 7 the threshold counters 4 and 5 the subtraction inputs

030028/0021 ORIGINAL INSPECTED

28S316

gears of this counter and carry out tripping S'-potentials at the same time the inputs 41 and 47 of the AND circuit 18 to. Since the input 51 of this circuit also has a trigger potential from the information output of the 2-time interval discriminator 8 is supplied, a triggering potential is generated at the output 58 of the AND circuit 18, that by clicking on the control input of the number display part 10 arrives, the transmission of the information from the Keversier counter 9 in the number display part 10 brings about.

he ..

In the last one, a large size of the stationary one is in digital form Value of the analog signal, which is the average size between the points of the maximum and minimum value of the analog signal on said characteristic section of the curve of the change of this Corresponds to the signal.

If the point on the curve of the change in Ana-O log signal (Fig. 3), in which the blocking of the reverse

sierounter 9 with the potential on the information output of the time interval discriminator 8 came about is, above the center line between the points of the maximum and minimum value of the analog signal on the characteristic section of this curve lies, so'-will when generating the signal on the information output of the Time interval discriminator 8 the content Λ Xj of the threshold

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ιοι

counter 5 be greater than the content A X _{2 of} ^the threshold counter 4, the deviation / \ X ^ of the blocking point with respect to the center line between the points of the maximum and minimum value of the analog signal on the characteristic section of this curve determined with the following relationship can be:

O ^x i ⁼ (D

The synchronized clock pulses ι which arrive at the additional subtraction inputs of the threshold counter 4 and 5 from the output 33 of the AND circuit 15 will also change the content of the threshold counter 4 and 5, as described above, but NuIl is first generated in the threshold counter 4 In contrast, a code will be present in the threshold counter 5 which corresponds to _{the difference between Δ X ^ and Δ X 2.} When ("\ Null appears in the threshold counter 4, the nuil state de-

cipher 6 the threshold counter 4 and leads trigger potentials to the UHD circuits 16, 18. The gauze state deodorator 7 of the Schwelien counter 5 leads with the help the NOT circuit 12 to the trigger potential to the input 52 of the AND circuit 16. There on the entrance 49 this AND circuit also has a trigger potential is that on the information output of the time ink rval! discriminator s 8 was generated, the syn-

030028/0021 ORIGINAL INSPECTED

285316V

chronized clock pulses, the frequency of which has been divided in the frequency divider 21 in the ratio 2s1, via the AND circuit 16 to the additional subtraction input of the reversing counter 9 threshold counter is generated 4 · the triggering potential at the output of the Dechiffrators 7 thereby locks via the NOT circuit 12, the AND circuit 16. In the He versierzähler 9 is thus such a number of reach of pulses to be calculated of the according to the relation (1) As a result, the content of the reversing counter 9 is automatically corrected to a required value that is equal to the average value between the maximum and minimum value of the analog signal on the characteristic section of the analog signal curve.When zero appears in the threshold counter 5 the AND circuit 18 is opened, the di e transmission of the information via the analog signal value in the number display part 10 brings about

In the event ^that the point at which the blocking of the reversing counter 9 with the potential on the information output of the Zeitintervaildiskriminators 8 has come about, below the center line between the Punk th of the maximum and minimum value of the analog signal

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. Ä6-

is located on the characteristic curve section (Fig. 4), the content ΔΧ, the threshold counter 5 is the oignals be smaller than the content Δ Xp ^of Schwellenza'hlers 4- in the generation on the information output of the Zeitintervalldiskriminators 8 · The deviation / IX '' this blocking point from the center line between the points of the maximum and minimum value of the inalog * ' J signal on the characteristic curve section

in this case determined according to the following relationship:

ΔX ₀ * '= AX ₂ - AX ₁ (2)

The synchronized clock pulses that are sent to the additional subtraction inputs of the threshold counters 4 and i? change their content · As soon as zero is generated in the threshold counter 5, a code is generated in the threshold counter 4 which represents a difference between Δ Xp and Δ X _x . corresponds · s ~ \ The Dechiffrator 7 thereby blocking the subtraction of the threshold counter 5 and opens the AND circuit 17 · The synchronized clock pulses pass through the frequency divider 10 in a ratio of 1: 2 and the AND circuit Ί7 to d _s additional summing input of the Reversierzählers 9 You will get ^to the mentioned additional addition input of the correcting counter 9 until zero is generated in the threshold counter 4 as well as in the threshold counter 5 * The decipherer 6, which controls the subtraction

03 002 8/0021

ORIGINAL INSPECTED

• η.

input of threshold counter 4 blocked, blocked via the NOT circuit 13 the AND circuit 17 the same Deohiffra gate 6 simultaneously opens the AND circuit 18. In the Reversing counter 9 will get a number of pulses which corresponds to a quantity ΔΧ '' which is nuch the relation (2) is calculated - as a result, the

Contents of the territory counter 9 automatically except for one corrected required size that corresponds to a point, that on the center line between the points of the maximum and minimum value of the analog signal on the characteristic Curve section lies. The corrected content of the reversing counter 9 is included in the number display part 10 a signal transmitted from the output 58 of the AND circuit 18 arrives and is displayed in it in digital form.

This constructive implementation of the digital device for determining the stationary value an analog signal makes it possible to achieve a more precise evaluation of the steady-state value of the analog signal.

at

The error in determining the steady-state value of the analog signal does not depend on a disturbance level, but is only made possible by triggering ever may η of the converter of the analog signal into the pulse number code. The use of simple slements and building

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■ as-

groups of digital rights ^en ~ technology in the facility ensures a high level of reliability with low manufacturing costs and small external dimensions · The use of the digital

Device for determining the stationary value of a

digital
Analog signal, e.g. for temperature measurement

of liquid steel with a thermoptiar that is briefly immersed in the liquid steel, ensures high measuring accuracy

So · * · B, when using a

one one

Converter analog signal in pulse number code with

a tripping capacity of 1 ⁰ C is the maximum error,

which is introduced into the measuring system by the device, not greater than ± 0.5 ⁰ G,

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ORIGINAL INSPECTED

Lee rse.ite

Claims (1)

PATENT CLAIM Digital device for determining the stationary one
Value of the analog signal, which a converter of the analog , .a ". ■ ,,, -,. a" .. _Tr , signals in pulse number code, the output for code pulses * the analogous to a positive increase and one
signals correspond to output for code pulses that ei * A clock pulse generator, a reversing counter for generating a parallel code of the calculation result, a number display part for displaying the sprinkling result, which is electrically connected to the digit outputs of the reversing counter, a first ^or second threshold counter. a time interval discriminator to determine local increases in the analog signal zero state decoders for the first and second (3 'threshold counters, whose inputs are connected to the digit outputs of the threshold counters and whose outputs are connected to the inputs of the calculation blocking when subtracting the first or second threshold counter for the selection of intervals between two successive points in time when the local increase in the analog signal where for reaches a specified size, the inputs of which an » initial setting to the overflow outputs of the threshold 030028/0021 ORIGINAL BATHROOM a- contains counters are connected to a synchronization part, the is used for the time distribution of code and clock pulses, of the two inputs to the outputs of the ina converter logsignals are switched into the pulse number code, the third input of the synchronization part to the off is, where output of the clock pulse generator is switched on, the outputs for synchronized code pulses of the synchronization part (are> with the threshold counters and the re vex they r counters ^ 7 for electrically connected, and the output synchronized Clock pulses of the oynchronisierteils ^^ Lsti with the time interval discriminator electrically connected,, thereby oinon characterized in that it uses frequency divider (21) and ratio 1: 2, three NOT circuits (11, 12, 13) seven AND circuits (14, 15, 16, 17, 18, 19, 20) contains ^that the time interval discriminator (8) provides information shows
output, which is connected to the first inputs of the first, C or ·> Second, third, fourth AND circuit (15, 16, 17, 18) and via the first NOT circuit (11) to the first input of the fifth AND circuit (14) that for is switched, the output (26) synchronized clock pulses of the synchronized ils (., J) (IStUm the second input is connected to the AND circuit (15) ⁴ that the threshold counters (5, Jfj / have ^ additional subtraction inputs on the output (33) the first AND 030028/0021
BATH ORIGINAL 2893161 that a circuit (15) is switched on, electrical coupling for
the outputs (27, 28) synchronized code pulses of the synchronization part (3) with the threshold counters (5, 4) and the reversing counter (9) by the sixth ^or * seventh AND circuit (19, 20) provided int, for
the output (27) being synchronized code pulses, which correspond to a positive increase in the analog signal, to the first input of the sixth AND circuit (19) for is switched, the output (28) synchronizes * code pulses, which correspond to a negative increase in the analog signal *. to the first input of the seventh AND circuit (2Ö) and
is switched on, the second inputs of the sixth and seventh AND circuit (19, 20) (, Ξΐηά ^ ιη ^ connected to the first input of the fifth AND circuit (14), while the output (34) of the sixth AND circuit (19) the addition inputs of the reversing counter (9) and the first threshold counter (5) and to the subtraction input of the second threshold counter (4) and the output (35) of the seventh AND circuit (20) the subtraction inputs of the population counter (9) and the first threshold number rs (5) as well as to the addition input is that exne of the second threshold counter (4) connected, electrical Coupling of the output (26) for synchronized Clock pulses of the synchronization part (3) with the Zeitxntervalldiskriminators (8) through the f 030028/0021 2853181 device (14) vorp; esehen isfc, at the second input of which the .Output (26) of the synchronized ils (3) switched on is the output (32) of the fifth IM) circuit (14) (4st \ an ^ ^θη Kecheneinüang des ίιβ it inter valldiskrimi- ^ - ^ that nators (8) switched on, the second inputs of the second and the third AND circuit (16, 17) via the Frequency divider (21) in a ratio of 1: 2 to the output (26) synchronized clock pulses of the synchronization part are that
(3) is switched on, the .output (44) of the zero state decoder frators (7) of the first threshold counter to the third input of the third AND circuit (17) i to the second Input of the fourth UUD circuit (18) and via the second NOT circuit (12) to the third input of the is that second AND circuit (17) turned on the output (38) of the zero state decipher (6) of the second threshold counter (4) to the fourth input of the second AND- / ~ n circuit (16), the third input of the fourth AND circuit (18) and via the third NOT circuit (13) to the fourth input of the third AND circuit (17) to »· is that
switched the outputs (56, 57) of the second or the third AND circuit (16, 17) to the additional subtraction condition and additional addi- Eind and that tion input of the reversing counter (9) switched on, the number display part (10). has a control input, cUr connected to the output (58) of the fourth AND circuit (18) is· 030028/0021